mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
84 lines
3.3 KiB
INI
84 lines
3.3 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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################################################################################
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# Atmel AT91SAM9260-EK eval board
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#
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
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#
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# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
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# OSCSEL configured for external 32.768 kHz crystal
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#
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# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
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#
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################################################################################
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# We add to the minimal configuration.
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source [find target/at91sam9260.cfg]
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# By default S1 is open and this means that NTRST is not connected.
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# The reset_config in target/at91sam9260.cfg is overridden here.
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# (or S1 must be populated with a 0 Ohm resistor)
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reset_config srst_only
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$_TARGETNAME configure -event reset-start {
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# At reset CPU runs at 32.768 kHz.
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# JTAG Frequency must be 6 times slower if RCLK is not supported.
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jtag_rclk 5
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halt
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# RSTC_MR : enable user reset, MMU may be enabled... use physical address
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mww phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
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sleep 10 ;# wait 10 ms
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mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
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sleep 20 ;# wait 20 ms
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mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
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sleep 10 ;# wait 10 ms
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# Increase JTAG Speed to 6 MHz if RCLK is not supported
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jtag_rclk 6000
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
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mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
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mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
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}
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