mirror of
https://git.code.sf.net/p/openocd/code
synced 2024-11-25 04:06:24 +00:00
52fbb85d2e
Add Ampere Altra ("Quicksilver") and Ampere Altra Max ("Mystique")
target/board configuration files.
The target configuration file supports silicon and emulation.
The board configuration files support 1 and 2 socket platforms.
Tested on Ampere emulation and silicon
Change-Id: I036c798a50624e30ab51ccd2895b6f60c40be096
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5591
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
101 lines
2.1 KiB
INI
101 lines
2.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
#
|
|
# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and
|
|
# Ampere Altra Max ("Mystique") processors
|
|
#
|
|
# Copyright (c) 2019-2021, Ampere Computing LLC
|
|
|
|
# Argument Description
|
|
#
|
|
# JTAGFREQ
|
|
# Set the JTAG clock frequency
|
|
# Syntax: -c "set JTAGFREQ {freq_in_khz}"
|
|
#
|
|
# SYSNAME
|
|
# Set the system name
|
|
# If not specified, defaults to "qs"
|
|
# Syntax: -c "set SYSNAME {qs}"
|
|
#
|
|
# Life-Cycle State (LCS)
|
|
# If not specified, defaults to "Secure LCS"
|
|
# LCS=0, "Secure LCS"
|
|
# LCS=1, "Chip Manufacturing LCS"
|
|
# Syntax: -c "set LCS {0}"
|
|
# Syntax: -c "set LCS {1}"
|
|
#
|
|
# CORELIST_S0
|
|
# Specify available physical cores by number
|
|
# Example syntax to connect to physical cores 16 and 17 for S0
|
|
# Syntax: -c "set CORELIST_S0 {16 17}"
|
|
#
|
|
# COREMASK_S0_LO
|
|
# Specify available physical cores 0-63 by mask
|
|
# Example syntax to connect to physical cores 16 and 17 for S0
|
|
# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}"
|
|
#
|
|
# COREMASK_S0_HI
|
|
# Specify available physical cores 64 and above by mask
|
|
# Example syntax to connect to physical cores 94 and 95 for S0
|
|
# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}"
|
|
#
|
|
# PHYS_IDX
|
|
# Enable OpenOCD ARMv8 core target physical indexing
|
|
# If not specified, defaults to OpenOCD ARMv8 core target logical indexing
|
|
# Syntax: -c "set PHYS_IDX {}"
|
|
|
|
#
|
|
# Configure JTAG speed
|
|
#
|
|
|
|
if { [info exists JTAGFREQ] } {
|
|
adapter speed $JTAGFREQ
|
|
} else {
|
|
adapter speed 100
|
|
}
|
|
|
|
#
|
|
# Set the system name
|
|
#
|
|
|
|
if { [info exists SYSNAME] } {
|
|
set _SYSNAME $SYSNAME
|
|
} else {
|
|
set _SYSNAME qs
|
|
}
|
|
|
|
#
|
|
# Configure Resets
|
|
#
|
|
|
|
jtag_ntrst_delay 100
|
|
reset_config trst_only
|
|
|
|
#
|
|
# Configure Targets
|
|
#
|
|
|
|
if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {
|
|
set CHIPNAME ${_SYSNAME}0
|
|
if { [info exists CORELIST_S0] } {
|
|
set CORELIST $CORELIST_S0
|
|
} else {
|
|
if { [info exists COREMASK_S0_LO] } {
|
|
set COREMASK_LO $COREMASK_S0_LO
|
|
} else {
|
|
set COREMASK_LO 0x0
|
|
}
|
|
|
|
if { [info exists COREMASK_S0_HI] } {
|
|
set COREMASK_HI $COREMASK_S0_HI
|
|
} else {
|
|
set COREMASK_HI 0x0
|
|
}
|
|
}
|
|
} else {
|
|
set CHIPNAME ${_SYSNAME}0
|
|
set COREMASK_LO 0x1
|
|
set COREMASK_HI 0x0
|
|
}
|
|
|
|
source [find target/ampere_qs_mq.cfg]
|