mirror of
https://git.code.sf.net/p/openocd/code
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4157732bd8
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/board | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7028
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
72 lines
1.8 KiB
INI
72 lines
1.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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source [find target/alphascale_asm9260t.cfg]
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reset_config trst_and_srst
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$_TARGETNAME configure -event reset-init {
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echo "Configure clock"
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# Enable SRAM clk
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mww 0x80040024 0x4
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# Enable IRQ clk
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mww 0x80040034 0x100
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# Enable DMA0,1 clk
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mww 0x80040024 0x600
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# Make sysre syspll is enabled
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mww 0x80040238 0x750
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#CPU = PLLCLK/2
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mww 0x8004017C 0x2
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#SYSAHBCLK = CPUCLK/2
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mww 0x80040180 0x2
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# Set PLL freq to 480MHz
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mww 0x80040100 480
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# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
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sleep 100
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# select PLL as main source
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mww 0x80040120 0x1
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# disable and enable main clk to update changes?
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mww 0x80040124 0x0
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mww 0x80040124 0x1
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echo "Configure memory"
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#enable EMI CLK
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mww 0x80040024 0x40
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# configure memory controller for internal SRAM
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mww 0x80700000 0x1188
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# change default emi clk delay
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mww 0x8004034C 0xA0503
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# make sure chip_select_register2_low has correct value (why?)
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mww 0x8070001c 0x20000000
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# set type to sdram and size to 32MB
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mww 0x8070005c 0xa
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# configure internal SDRAM timing
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mww 0x80700004 0x024996d9
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# configure Static Memory timing
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mww 0x80700094 0x00542b4f
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echo "Configure uart4"
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# enable pinctrl clk
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mww 0x80040024 0x2000000
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# mux GPIO3_0 and GPIO3_1 to UART4
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mww 0x80044060 0x2
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mww 0x80044064 0x2
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# configure UART4CLKDIV
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mww 0x800401a8 0x1
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# enable uart4 clk
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mww 0x80040024 0x8000
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# clear softrst and clkgate on uart4
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mww 0x80010008 0xC0000000
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# set bandrate 115200 12M
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mww 0x80010030 0x00062070
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# enable Rx&Tx
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mww 0x80010024 0x301
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# clear hw control
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mww 0x80010028 0xc000
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}
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$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
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$_TARGETNAME arm7_9 fast_memory_access enable
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$_TARGETNAME arm7_9 dcc_downloads enable
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