43e137091b
Changes in 4.9.310 arm64: errata: Provide macro for major and minor cpu revisions arm64: Remove useless UAO IPI and describe how this gets enabled arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35 arm64: capabilities: Update prototype for enable call back arm64: capabilities: Move errata work around check on boot CPU arm64: capabilities: Move errata processing code arm64: capabilities: Prepare for fine grained capabilities arm64: capabilities: Add flags to handle the conflicts on late CPU arm64: capabilities: Clean up midr range helpers arm64: Add helpers for checking CPU MIDR against a range arm64: capabilities: Add support for checks based on a list of MIDRs clocksource/drivers/arm_arch_timer: Remove fsl-a008585 parameter clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure arm64: arch_timer: Add infrastructure for multiple erratum detection methods arm64: arch_timer: Add erratum handler for CPU-specific capability arm64: arch_timer: Add workaround for ARM erratum 1188873 arm64: arch_timer: avoid unused function warning arm64: Add silicon-errata.txt entry for ARM erratum 1188873 arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT arm64: Add part number for Neoverse N1 arm64: Add part number for Arm Cortex-A77 arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: Add Cortex-X2 CPU part definition arm64: Add helper to decode register from instruction arm64: entry.S: Add ventry overflow sanity checks arm64: entry: Make the trampoline cleanup optional arm64: entry: Free up another register on kpti's tramp_exit path arm64: entry: Move the trampoline data page before the text page arm64: entry: Allow tramp_alias to access symbols after the 4K boundary arm64: entry: Don't assume tramp_vectors is the start of the vectors arm64: entry: Move trampoline macros out of ifdef'd section arm64: entry: Make the kpti trampoline's kpti sequence optional arm64: entry: Allow the trampoline text to occupy multiple pages arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations arm64: Move arm64_update_smccc_conduit() out of SSBD ifdef arm64: entry: Add vectors that have the bhb mitigation sequences arm64: entry: Add macro for reading symbol addresses from the trampoline arm64: Add percpu vectors for EL1 KVM: arm64: Add templates for BHB mitigation sequences arm64: Mitigate spectre style branch history side channels KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated arm64: add ID_AA64ISAR2_EL1 sys register arm64: Use the clearbhb instruction in mitigations Linux 4.9.310 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I689d7634aebe9d9ffba8d72d1d76bb237ca228a4
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2022 ARM Ltd.
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*/
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#ifndef __ASM_VECTORS_H
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#define __ASM_VECTORS_H
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#include <linux/bug.h>
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#include <linux/percpu.h>
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#include <asm/fixmap.h>
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#include <asm/mmu.h>
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extern char vectors[];
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extern char tramp_vectors[];
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extern char __bp_harden_el1_vectors[];
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/*
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* Note: the order of this enum corresponds to two arrays in entry.S:
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* tramp_vecs and __bp_harden_el1_vectors. By default the canonical
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* 'full fat' vectors are used directly.
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*/
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enum arm64_bp_harden_el1_vectors {
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#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
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/*
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* Perform the BHB loop mitigation, before branching to the canonical
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* vectors.
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*/
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EL1_VECTOR_BHB_LOOP,
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/*
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* Make the SMC call for firmware mitigation, before branching to the
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* canonical vectors.
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*/
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EL1_VECTOR_BHB_FW,
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/*
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* Use the ClearBHB instruction, before branching to the canonical
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* vectors.
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*/
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EL1_VECTOR_BHB_CLEAR_INSN,
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#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
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/*
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* Remap the kernel before branching to the canonical vectors.
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*/
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EL1_VECTOR_KPTI,
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};
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#ifndef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
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#define EL1_VECTOR_BHB_LOOP -1
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#define EL1_VECTOR_BHB_FW -1
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#define EL1_VECTOR_BHB_CLEAR_INSN -1
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#endif /* !CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
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/* The vectors to use on return from EL0. e.g. to remap the kernel */
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DECLARE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector);
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#ifndef CONFIG_UNMAP_KERNEL_AT_EL0
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#define TRAMP_VALIAS 0
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#endif
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static inline const char *
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arm64_get_bp_hardening_vector(enum arm64_bp_harden_el1_vectors slot)
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{
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if (arm64_kernel_unmapped_at_el0())
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return (char *)TRAMP_VALIAS + SZ_2K * slot;
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WARN_ON_ONCE(slot == EL1_VECTOR_KPTI);
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return __bp_harden_el1_vectors + SZ_2K * slot;
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}
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#endif /* __ASM_VECTORS_H */
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