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kernel-49/arch/arm64/include/asm/arch_timer.h
Greg Kroah-Hartman 43e137091b Merge 4.9.310 into android-4.9-q
Changes in 4.9.310
	arm64: errata: Provide macro for major and minor cpu revisions
	arm64: Remove useless UAO IPI and describe how this gets enabled
	arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35
	arm64: capabilities: Update prototype for enable call back
	arm64: capabilities: Move errata work around check on boot CPU
	arm64: capabilities: Move errata processing code
	arm64: capabilities: Prepare for fine grained capabilities
	arm64: capabilities: Add flags to handle the conflicts on late CPU
	arm64: capabilities: Clean up midr range helpers
	arm64: Add helpers for checking CPU MIDR against a range
	arm64: capabilities: Add support for checks based on a list of MIDRs
	clocksource/drivers/arm_arch_timer: Remove fsl-a008585 parameter
	clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure
	arm64: arch_timer: Add infrastructure for multiple erratum detection methods
	arm64: arch_timer: Add erratum handler for CPU-specific capability
	arm64: arch_timer: Add workaround for ARM erratum 1188873
	arm64: arch_timer: avoid unused function warning
	arm64: Add silicon-errata.txt entry for ARM erratum 1188873
	arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT
	arm64: Add part number for Neoverse N1
	arm64: Add part number for Arm Cortex-A77
	arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
	arm64: Add Cortex-X2 CPU part definition
	arm64: Add helper to decode register from instruction
	arm64: entry.S: Add ventry overflow sanity checks
	arm64: entry: Make the trampoline cleanup optional
	arm64: entry: Free up another register on kpti's tramp_exit path
	arm64: entry: Move the trampoline data page before the text page
	arm64: entry: Allow tramp_alias to access symbols after the 4K boundary
	arm64: entry: Don't assume tramp_vectors is the start of the vectors
	arm64: entry: Move trampoline macros out of ifdef'd section
	arm64: entry: Make the kpti trampoline's kpti sequence optional
	arm64: entry: Allow the trampoline text to occupy multiple pages
	arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations
	arm64: Move arm64_update_smccc_conduit() out of SSBD ifdef
	arm64: entry: Add vectors that have the bhb mitigation sequences
	arm64: entry: Add macro for reading symbol addresses from the trampoline
	arm64: Add percpu vectors for EL1
	KVM: arm64: Add templates for BHB mitigation sequences
	arm64: Mitigate spectre style branch history side channels
	KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated
	arm64: add ID_AA64ISAR2_EL1 sys register
	arm64: Use the clearbhb instruction in mitigations
	Linux 4.9.310

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I689d7634aebe9d9ffba8d72d1d76bb237ca228a4
2022-04-14 18:57:54 +03:00

155 lines
3.6 KiB
C

/*
* arch/arm64/include/asm/arch_timer.h
*
* Copyright (C) 2012 ARM Ltd.
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_ARCH_TIMER_H
#define __ASM_ARCH_TIMER_H
#include <asm/barrier.h>
#include <asm/sysreg.h>
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/jump_label.h>
#include <linux/types.h>
#include <clocksource/arm_arch_timer.h>
#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
extern struct static_key_false arch_timer_read_ool_enabled;
#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
#define needs_unstable_timer_counter_workaround() false
#endif
enum arch_timer_erratum_match_type {
ate_match_dt,
ate_match_local_cap_id,
};
struct arch_timer_erratum_workaround {
enum arch_timer_erratum_match_type match_type;
const void *id;
const char *desc;
u32 (*read_cntp_tval_el0)(void);
u32 (*read_cntv_tval_el0)(void);
u64 (*read_cntvct_el0)(void);
};
extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
if (needs_unstable_timer_counter_workaround()) \
_val = timer_unstable_counter_workaround->read_##reg();\
else \
_val = read_sysreg(reg); \
_val; \
})
/*
* These register accessors are marked inline so the compiler can
* nicely work out which register we want, and chuck away the rest of
* the code.
*/
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntp_ctl_el0);
break;
case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntp_tval_el0);
break;
}
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntv_ctl_el0);
break;
case ARCH_TIMER_REG_TVAL:
write_sysreg(val, cntv_tval_el0);
break;
}
}
isb();
}
static __always_inline
u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntp_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntp_tval_el0);
}
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
return read_sysreg(cntv_ctl_el0);
case ARCH_TIMER_REG_TVAL:
return arch_timer_reg_read_stable(cntv_tval_el0);
}
}
BUG();
}
static inline u32 arch_timer_get_cntfrq(void)
{
return read_sysreg(cntfrq_el0);
}
static inline u32 arch_timer_get_cntkctl(void)
{
return read_sysreg(cntkctl_el1);
}
static inline void arch_timer_set_cntkctl(u32 cntkctl)
{
write_sysreg(cntkctl, cntkctl_el1);
}
static inline u64 arch_counter_get_cntpct(void)
{
/*
* AArch64 kernel and user space mandate the use of CNTVCT.
*/
BUG();
return 0;
}
static inline u64 arch_counter_get_cntvct(void)
{
isb();
return arch_timer_reg_read_stable(cntvct_el0);
}
static inline int arch_timer_arch_init(void)
{
return 0;
}
#endif