308 lines
8.7 KiB
Diff
308 lines
8.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 20 Jan 2021 22:15:36 +0100
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Subject: [PATCH] wip h3/h5 cvbs
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 111 +++++++++++++++++++++++++++-
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 14 +++-
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drivers/gpu/drm/sun4i/Makefile | 2 +-
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drivers/gpu/drm/sun4i/sun8i_mixer.c | 42 ++++++++++-
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drivers/gpu/drm/sun4i/sun8i_mixer.h | 5 +-
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5 files changed, 165 insertions(+), 9 deletions(-)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index f6b9d8a738d0..c5c53e7bf3bc 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -119,7 +119,7 @@ osc32k: osc32k_clk {
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de: display-engine {
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compatible = "allwinner,sun8i-h3-display-engine";
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- allwinner,pipelines = <&mixer0>;
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+ allwinner,pipelines = <&mixer0>, <&mixer1>;
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status = "disabled";
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};
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@@ -156,11 +156,50 @@ ports {
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#size-cells = <0>;
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mixer0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <1>;
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- mixer0_out_tcon0: endpoint {
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+ mixer0_out_tcon0: endpoint@0 {
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+ reg = <0>;
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remote-endpoint = <&tcon0_in_mixer0>;
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};
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+
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+ mixer0_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mixer1: mixer@1200000 {
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+ compatible = "allwinner,sun8i-h3-de2-mixer-1";
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+ reg = <0x01200000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER1>,
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+ <&display_clocks CLK_MIXER1>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_WB>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ mixer1_out_tcon0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&tcon0_in_mixer1>;
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+ };
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+
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+ mixer1_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer1>;
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+ };
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};
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};
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};
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@@ -189,11 +228,19 @@ ports {
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#size-cells = <0>;
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tcon0_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0>;
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- tcon0_in_mixer0: endpoint {
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+ tcon0_in_mixer0: endpoint@0 {
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+ reg = <0>;
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remote-endpoint = <&mixer0_out_tcon0>;
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};
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+
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+ tcon0_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon0>;
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+ };
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};
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tcon0_out: port@1 {
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@@ -209,6 +256,49 @@ tcon0_out_hdmi: endpoint@1 {
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};
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};
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+ tcon1: lcd-controller@1c0d000 {
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+ compatible = "allwinner,sun8i-h3-tcon-tv",
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+ "allwinner,sun8i-a83t-tcon-tv";
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+ reg = <0x01c0d000 0x1000>;
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+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TVE>;
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+ clock-names = "ahb", "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON1>;
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+ reset-names = "lcd";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon1_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon1_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon1>;
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+ };
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+
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+ tcon1_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon1>;
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+ };
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+ };
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+
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+ tcon1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ tcon1_out_tve: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tve_in_tcon1>;
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+ };
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+ };
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+ };
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+ };
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+
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mmc0: mmc@1c0f000 {
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/* compatible and clocks are in per SoC .dtsi file */
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reg = <0x01c0f000 0x1000>;
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@@ -822,6 +912,21 @@ csi: camera@1cb0000 {
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status = "disabled";
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};
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+ tve: tv-encoder@1e00000 {
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+ compatible = "allwinner,sun8i-h3-tv-encoder",
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+ "allwinner,sun4i-a10-tv-encoder";
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+ reg = <0x01e00000 0x1000>;
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+ clocks = <&ccu CLK_BUS_TVE>;
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+ resets = <&ccu RST_BUS_TVE>;
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+ status = "disabled";
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+
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+ port {
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+ tve_in_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_out_tve>;
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+ };
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+ };
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+ };
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+
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hdmi: hdmi@1ee0000 {
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#sound-dai-cells = <0>;
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compatible = "allwinner,sun8i-h3-dw-hdmi",
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 7e629a4493af..334b7edea3b7 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -456,8 +456,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
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CLK_SET_RATE_PARENT);
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static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
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-static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
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- 0x120, 0, 4, 24, 3, BIT(31), 0);
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+struct ccu_div tve_clk = {
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+ .enable = BIT(31),
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+ .div = _SUNXI_CCU_DIV(0, 4),
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+ .mux = _SUNXI_CCU_MUX(24, 3),
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+ .fixed_post_div = 16,
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+ .common = {
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+ .reg = 0x120,
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+ .features = CCU_FEATURE_FIXED_POSTDIV,
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+ .hw.init = CLK_HW_INIT_PARENTS("tve", tve_parents,
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+ &ccu_div_ops, 0),
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+ },
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+};
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static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
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diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
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index 0d04f2447b01..7b151994e904 100644
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--- a/drivers/gpu/drm/sun4i/Makefile
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+++ b/drivers/gpu/drm/sun4i/Makefile
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@@ -16,7 +16,7 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o
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sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
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sun8i_vi_layer.o sun8i_ui_scaler.o \
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- sun8i_vi_scaler.o sun8i_csc.o
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+ sun8i_vi_scaler.o sun8i_csc.o sun4i_tv.o
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sun4i-tcon-y += sun4i_crtc.o
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sun4i-tcon-y += sun4i_dotclock.o
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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index ba239b20a639..536ff2d15926 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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@@ -32,6 +32,12 @@ struct de2_fmt_info {
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u32 de2_fmt;
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};
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+static const u32 sun8i_rgb2yuv_coef[12] = {
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+ 0x00000107, 0x00000204, 0x00000064, 0x00004200,
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+ 0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200,
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+ 0x000001c2, 0x00001e87, 0x00001fb7, 0x00020200,
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+};
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+
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static const struct de2_fmt_info de2_formats[] = {
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{
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.drm_fmt = DRM_FORMAT_ARGB8888,
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@@ -341,9 +347,28 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
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return planes;
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}
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+static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
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+{
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+ DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
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+
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+ regmap_bulk_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(0),
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+ sun8i_rgb2yuv_coef, 12);
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+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
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+}
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+
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+static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
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+{
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+ DRM_DEBUG_DRIVER("Disabling color correction\n");
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+
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+ /* Disable color correction */
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+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
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+}
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+
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static const struct sunxi_engine_ops sun8i_engine_ops = {
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- .commit = sun8i_mixer_commit,
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- .layers_init = sun8i_layers_init,
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+ .commit = sun8i_mixer_commit,
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+ .layers_init = sun8i_layers_init,
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+ .apply_color_correction = sun8i_mixer_apply_color_correction,
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+ .disable_color_correction = sun8i_mixer_disable_color_correction,
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};
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static bool sun8i_mixer_volatile_reg(struct device *dev, unsigned int reg)
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@@ -608,6 +633,15 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
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.vi_num = 1,
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};
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+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
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+ .ccsc = 1,
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+ .mod_rate = 432000000,
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+ .scaler_mask = 0x3,
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+ .scanline_yuv = 2048,
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+ .ui_num = 1,
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+ .vi_num = 1,
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+};
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+
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static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
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.ccsc = 0,
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.mod_rate = 297000000,
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@@ -676,6 +710,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
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.compatible = "allwinner,sun8i-h3-de2-mixer-0",
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.data = &sun8i_h3_mixer0_cfg,
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},
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+ {
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+ .compatible = "allwinner,sun8i-h3-de2-mixer-1",
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+ .data = &sun8i_h3_mixer1_cfg,
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+ },
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{
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.compatible = "allwinner,sun8i-r40-de2-mixer-0",
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.data = &sun8i_r40_mixer0_cfg,
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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index e7eebe7dd1af..dc45a37ae56e 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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@@ -120,6 +120,10 @@
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/* format 20 is packed YVU444 10-bit */
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/* format 21 is packed YUV444 10-bit */
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+/* The DCSC sub-engine is used to do color space conversation */
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+#define SUN8I_MIXER_DCSC_EN 0xb0000
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+#define SUN8I_MIXER_DCSC_COEF_REG(x) (0xb0010 + 0x4 * (x))
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+
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/*
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* Sub-engines listed bellow are unused for now. The EN registers are here only
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* to be used to disable these sub-engines.
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@@ -130,7 +134,6 @@
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#define SUN8I_MIXER_PEAK_EN 0xa6000
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#define SUN8I_MIXER_ASE_EN 0xa8000
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#define SUN8I_MIXER_FCC_EN 0xaa000
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-#define SUN8I_MIXER_DCSC_EN 0xb0000
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#define SUN50I_MIXER_FCE_EN 0x70000
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#define SUN50I_MIXER_PEAK_EN 0x70800
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