34 lines
1.1 KiB
Diff
34 lines
1.1 KiB
Diff
From c4b9d6d8feaf91a9b83285052ac7b4f45580ddb0 Mon Sep 17 00:00:00 2001
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From: Jerome Brunet <jbrunet@baylibre.com>
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Date: Tue, 14 Apr 2020 10:45:08 +0200
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Subject: [PATCH 61/88] WIP: clk: meson: g12a: fix hifi pll lock
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The HIFI pll of the g12a sometimes takes a long time to report the lock in
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HIFI_PLL_CNTL0 bit 31. The would eventually be reported but the delay may
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be so long that the driver consider it a lock failure.
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Bit 30 seems to do the same job but more quickly, let's try this instead.
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Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
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Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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---
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drivers/clk/meson/g12a.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
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index a805bac93c11..c22611d3669a 100644
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--- a/drivers/clk/meson/g12a.c
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+++ b/drivers/clk/meson/g12a.c
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@@ -1783,7 +1783,7 @@ static struct clk_regmap g12a_hifi_pll_dco = {
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},
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.l = {
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.reg_off = HHI_HIFI_PLL_CNTL0,
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- .shift = 31,
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+ .shift = 30,
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.width = 1,
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},
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.rst = {
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--
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2.17.1
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