140 lines
5.0 KiB
Diff
140 lines
5.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Fri, 25 Dec 2020 02:05:58 -0600
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Subject: [PATCH] ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc
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All IRQs that can be used to wake up the system must be routed through
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r_intc, so they are visible to firmware while the system is suspended.
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In addition to the external NMI input, which is already routed through
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r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++++
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arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 ++++
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arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +++
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +++
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4 files changed, 14 insertions(+)
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--- a/arch/arm/boot/dts/sun6i-a31.dtsi
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+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
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@@ -611,6 +611,7 @@
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun6i-a31-pinctrl";
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reg = <0x01c20800 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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@@ -802,6 +803,7 @@
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lradc: lradc@1c22800 {
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compatible = "allwinner,sun4i-a10-lradc-keys";
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reg = <0x01c22800 0x100>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -1299,6 +1301,7 @@
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc32k>;
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@@ -1383,6 +1386,7 @@
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun6i-a31-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
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--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
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+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
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@@ -338,6 +338,7 @@
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pio: pinctrl@1c20800 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c20800 0x400>;
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+ interrupt-parent = <&r_intc>;
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/* interrupts get set in SoC specific dtsi file */
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
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clock-names = "apb", "hosc", "losc";
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@@ -473,6 +474,7 @@
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lradc: lradc@1c22800 {
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compatible = "allwinner,sun4i-a10-lradc-keys";
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reg = <0x01c22800 0x100>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -709,6 +711,7 @@
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun8i-a23-rtc";
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reg = <0x01f00000 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clock-output-names = "osc32k", "osc32k-out";
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@@ -805,6 +808,7 @@
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun8i-a23-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
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clock-names = "apb", "hosc", "losc";
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--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
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+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
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@@ -708,6 +708,7 @@
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun8i-a83t-pinctrl";
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1150,6 +1151,7 @@
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r_lradc: lradc@1f03c00 {
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compatible = "allwinner,sun8i-a83t-r-lradc";
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reg = <0x01f03c00 0x100>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -1157,6 +1159,7 @@
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun8i-a83t-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
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<&osc16Md512>;
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -413,6 +413,7 @@
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pio: pinctrl@1c20800 {
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/* compatible is in per SoC .dtsi file */
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reg = <0x01c20800 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
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@@ -870,6 +871,7 @@
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rtc: rtc@1f00000 {
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/* compatible is in per SoC .dtsi file */
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reg = <0x01f00000 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clock-output-names = "osc32k", "osc32k-out", "iosc";
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@@ -927,6 +929,7 @@
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun8i-h3-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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+ interrupt-parent = <&r_intc>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
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clock-names = "apb", "hosc", "losc";
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