forked from libretro/Lakka-LibreELEC
257 lines
8.6 KiB
Diff
257 lines
8.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 10 Oct 2020 15:32:19 +0000
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Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328
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recalc_rate
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no_c is not used in any calculation, lets remove it.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +----
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1 file changed, 1 insertion(+), 4 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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index 15a008a1ac7b..4b936ca19920 100644
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--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
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{
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struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
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unsigned long frac;
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- u8 nd, no_a, no_b, no_c, no_d;
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+ u8 nd, no_a, no_b, no_d;
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u64 vco;
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u16 nf;
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@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
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no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
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no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
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no_b += 2;
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- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
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- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
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- no_c = 1 << no_c;
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no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
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do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Huicong Xu <xhc@rock-chips.com>
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Date: Sat, 10 Oct 2020 15:32:20 +0000
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Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on
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Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
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not in pixel clock rate.
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When the hdmiphy clock is configured with the same pixel clock rate using
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clk_set_rate() the clock framework do not signal the hdmi phy driver
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to set_rate when switching between 8-bit and Deep Color.
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This result in pre/post pll not being re-configured when switching between
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regular 8-bit and Deep Color video formats.
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Fix this by calling set_rate in power_on to force pre pll re-configuration.
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Signed-off-by: Huicong Xu <xhc@rock-chips.com>
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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index 620961fcfc1d..2f01259823ea 100644
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--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
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@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
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struct clk_hw hw;
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struct clk *phyclk;
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unsigned long pixclock;
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+ unsigned long tmdsclock;
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};
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struct pre_pll_config {
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@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
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dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
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+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
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+
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ret = clk_prepare_enable(inno->phyclk);
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if (ret)
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return ret;
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@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy)
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clk_disable_unprepare(inno->phyclk);
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+ inno->tmdsclock = 0;
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+
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dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
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return 0;
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@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
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dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
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__func__, rate, tmdsclock);
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+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
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+ return 0;
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+
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cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
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if (IS_ERR(cfg))
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return PTR_ERR(cfg);
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@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
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}
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inno->pixclock = rate;
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+ inno->tmdsclock = tmdsclock;
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return 0;
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}
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@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
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dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
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__func__, rate, tmdsclock);
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+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
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+ return 0;
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+
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cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
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if (IS_ERR(cfg))
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return PTR_ERR(cfg);
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@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
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}
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inno->pixclock = rate;
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+ inno->tmdsclock = tmdsclock;
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return 0;
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}
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 17 Feb 2019 22:14:38 +0000
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Subject: [PATCH] mmc: core: set initial signal voltage on power off
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Some boards have SD card connectors where the power rail cannot be switched
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off by the driver. If the card has not been power cycled, it may still be
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using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
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will fail to boot from a UHS card that continue to use 1.8V signaling.
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Set initial signal voltage in mmc_power_off() to allow re-boot to function.
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This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
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same issue have been seen on some Rockchip RK3399 boards.
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I am sending this as a RFC because I have no insights into SD/MMC subsystem,
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this change fix a re-boot issue on my boards and does not break emmc/sdio.
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Is this an acceptable workaround? Any advice is appreciated.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/mmc/core/core.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
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index ef53a2578824..d4c53074154a 100644
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--- a/drivers/mmc/core/core.c
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+++ b/drivers/mmc/core/core.c
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@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host)
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if (host->ios.power_mode == MMC_POWER_OFF)
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return;
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+ mmc_set_initial_signal_voltage(host);
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+
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+ /*
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+ * This delay should be sufficient to allow the power supply
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+ * to reach the minimum voltage.
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+ */
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+ mmc_delay(host->ios.power_delay_ms);
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+
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mmc_pwrseq_power_off(host);
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host->ios.clock = 0;
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Wed, 23 Jun 2021 16:59:18 +0200
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Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328
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RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some
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boards have sdio wifi connected to it. In order to use it
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one would have to add the pinctrls from sdmmc0ext group which
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is done on board level.
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index 49ae15708a0b..60348d517efb 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -993,6 +993,20 @@ usb_host0_ohci: usb@ff5d0000 {
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status = "disabled";
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};
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+ sdmmc_ext: mmc@ff5f0000 {
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+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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+ reg = <0x0 0xff5f0000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
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+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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+ fifo-depth = <0x100>;
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+ max-frequency = <150000000>;
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+ resets = <&cru SRST_SDMMCEXT>;
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+ reset-names = "reset";
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+ status = "disabled";
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+ };
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+
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usbdrd3: usb@ff600000 {
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compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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reg = <0x0 0xff600000 0x0 0x100000>;
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Wed, 23 Jun 2021 17:02:08 +0200
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Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for
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RK3328
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The DW MCI controller driver will use them to reset the IP block before
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initialisation.
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Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs")
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index 60348d517efb..d7e44d174d7b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -871,6 +871,8 @@ sdmmc: mmc@ff500000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_MMC0>;
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+ reset-names = "reset";
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status = "disabled";
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};
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@@ -883,6 +885,8 @@ sdio: mmc@ff510000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_SDIO>;
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+ reset-names = "reset";
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status = "disabled";
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};
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@@ -895,6 +899,8 @@ emmc: mmc@ff520000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_EMMC>;
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+ reset-names = "reset";
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status = "disabled";
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};
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