forked from libretro/Lakka-LibreELEC
109 lines
3.4 KiB
Diff
109 lines
3.4 KiB
Diff
From c2af9b24bfa69ffb12e72153f89ed3bb3245fafb Mon Sep 17 00:00:00 2001
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From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Date: Fri, 22 Nov 2019 10:00:56 +0200
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Subject: [PATCH 40/49] drm/imx/dcss: use the external 27MHz phy clock
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The 27MHz external oscillator offers a high precision low jitter clock and
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is suitable for high pixel clocks modes(ie 4K@60).
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Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
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---
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drivers/gpu/drm/imx/dcss/dcss-dev.c | 25 +++++++++++++++++++------
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drivers/gpu/drm/imx/dcss/dcss-dtg.c | 11 +++++++++++
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2 files changed, 30 insertions(+), 6 deletions(-)
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diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c b/drivers/gpu/drm/imx/dcss/dcss-dev.c
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index c849533ca83e..1977f6b058f8 100644
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--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
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+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
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@@ -17,6 +17,11 @@
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static void dcss_clocks_enable(struct dcss_dev *dcss)
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{
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+ if (dcss->hdmi_output) {
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+ clk_prepare_enable(dcss->pll_phy_ref_clk);
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+ clk_prepare_enable(dcss->pll_src_clk);
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+ }
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+
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clk_prepare_enable(dcss->axi_clk);
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clk_prepare_enable(dcss->apb_clk);
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clk_prepare_enable(dcss->rtrm_clk);
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@@ -31,6 +36,11 @@ static void dcss_clocks_disable(struct dcss_dev *dcss)
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clk_disable_unprepare(dcss->rtrm_clk);
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clk_disable_unprepare(dcss->apb_clk);
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clk_disable_unprepare(dcss->axi_clk);
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+
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+ if (dcss->hdmi_output) {
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+ clk_disable_unprepare(dcss->pll_src_clk);
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+ clk_disable_unprepare(dcss->pll_phy_ref_clk);
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+ }
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}
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static void dcss_disable_dtg_and_ss_cb(void *data)
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@@ -133,17 +143,20 @@ static int dcss_clks_init(struct dcss_dev *dcss)
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struct {
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const char *id;
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struct clk **clk;
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+ bool required;
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} clks[] = {
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- {"apb", &dcss->apb_clk},
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- {"axi", &dcss->axi_clk},
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- {"pix", &dcss->pix_clk},
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- {"rtrm", &dcss->rtrm_clk},
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- {"dtrc", &dcss->dtrc_clk},
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+ {"apb", &dcss->apb_clk, true},
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+ {"axi", &dcss->axi_clk, true},
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+ {"pix", &dcss->pix_clk, true},
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+ {"rtrm", &dcss->rtrm_clk, true},
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+ {"dtrc", &dcss->dtrc_clk, true},
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+ {"pll_src", &dcss->pll_src_clk, dcss->hdmi_output},
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+ {"pll_phy_ref", &dcss->pll_phy_ref_clk, dcss->hdmi_output},
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};
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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*clks[i].clk = devm_clk_get(dcss->dev, clks[i].id);
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- if (IS_ERR(*clks[i].clk)) {
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+ if (IS_ERR(*clks[i].clk) && clks[i].required) {
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dev_err(dcss->dev, "failed to get %s clock\n",
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clks[i].id);
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return PTR_ERR(*clks[i].clk);
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diff --git a/drivers/gpu/drm/imx/dcss/dcss-dtg.c b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
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index 30de00540f63..b70785d69ad9 100644
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--- a/drivers/gpu/drm/imx/dcss/dcss-dtg.c
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+++ b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
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@@ -83,6 +83,7 @@ struct dcss_dtg {
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u32 ctx_id;
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bool in_use;
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+ bool hdmi_output;
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u32 dis_ulc_x;
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u32 dis_ulc_y;
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@@ -159,6 +160,7 @@ int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base)
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dcss->dtg = dtg;
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dtg->dev = dcss->dev;
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dtg->ctxld = dcss->ctxld;
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+ dtg->hdmi_output = dcss->hdmi_output;
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dtg->base_reg = ioremap(dtg_base, SZ_4K);
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if (!dtg->base_reg) {
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@@ -221,6 +223,15 @@ void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
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vm->vactive - 1;
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clk_disable_unprepare(dcss->pix_clk);
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+ if (dcss->hdmi_output) {
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+ int err;
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+
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+ clk_disable_unprepare(dcss->pll_src_clk);
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+ err = clk_set_parent(dcss->pll_src_clk, dcss->pll_phy_ref_clk);
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+ if (err < 0)
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+ dev_warn(dcss->dev, "clk_set_parent() returned %d", err);
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+ clk_prepare_enable(dcss->pll_src_clk);
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+ }
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clk_set_rate(dcss->pix_clk, vm->pixelclock);
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clk_prepare_enable(dcss->pix_clk);
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--
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2.29.2
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