forked from libretro/Lakka-LibreELEC
197 lines
6.0 KiB
Diff
197 lines
6.0 KiB
Diff
From f15f4f36e023aaaeacdbebe16736119d1be3ac6b Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 9 Oct 2021 17:12:57 -0500
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Subject: [PATCH 07/13] sunxi: psci: Add support for H3 CPU 0 hotplug
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Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
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written, resuming CPU 0 requires using the "Super Standby" code path in
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the BROM instead of the hotplug path. This path requires jumping to an
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eGON image in SRAM.
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Add support to the build system to generate this eGON image and include
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it in the FIT, and add code to direct the BROM to its location in SRAM.
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Since the Super Standby code path in the BROM initializes the CPU and
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AHB1 clocks to 24 MHz, those registers need to be restored after control
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passes back to U-Boot. Furthermore, because the BROM lowers the AHB1
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clock divider to /1 before switching to the lower-frequency parent,
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PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at
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600 MHz. Otherwise, this locks up the SoC.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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Makefile | 17 +++++++++++++++++
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arch/arm/cpu/armv7/sunxi/psci.c | 31 +++++++++++++++++++++++++++++++
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arch/arm/dts/sunxi-u-boot.dtsi | 23 ++++++++++++++++++++++-
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include/configs/sun8i.h | 4 ++++
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4 files changed, 74 insertions(+), 1 deletion(-)
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diff --git a/Makefile b/Makefile
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index f911f7034430..9edcadfa9c47 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -984,6 +984,23 @@ endif
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endif
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endif
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+ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
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+INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
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+
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+MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
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+
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+u-boot-resume.img: u-boot-resume.bin
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+ $(call if_changed,mkimage)
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+
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+OBJCOPYFLAGS_u-boot-resume.bin := -O binary
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+
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+u-boot-resume.bin: u-boot-resume.o
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+ $(call if_changed,objcopy)
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+
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+u-boot-resume.S: u-boot
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+ @sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
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+endif
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+
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INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
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$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
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$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)
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diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
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index 3448fe2edcaa..299bd3ba65e0 100644
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--- a/arch/arm/cpu/armv7/sunxi/psci.c
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+++ b/arch/arm/cpu/armv7/sunxi/psci.c
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@@ -10,6 +10,7 @@
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#include <common.h>
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#include <asm/cache.h>
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+#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cpucfg.h>
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#include <asm/arch/prcm.h>
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@@ -141,6 +142,13 @@ static void __secure sunxi_set_entry_address(void *entry)
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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writel((u32)entry, &cpucfg->priv0);
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+
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+ if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) {
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+ /* Redirect CPU 0 to the secure monitor via the resume shim. */
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+ writel(0x16aaefe8, &cpucfg->super_standy_flag);
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+ writel(0xaa16efe8, &cpucfg->super_standy_flag);
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+ writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
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+ }
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}
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#endif
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@@ -255,9 +263,12 @@ out:
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int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
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u32 context_id)
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{
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+ struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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u32 cpu = (mpidr & 0x3);
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+ u32 cpu_clk;
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+ u32 bus_clk;
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/* store target PC and context id */
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psci_save(cpu, pc, context_id);
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@@ -274,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
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/* Lock CPU (Disable external debug access) */
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clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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+ if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
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+ /* Save registers that will be clobbered by the BROM. */
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+ cpu_clk = readl(&ccu->cpu_axi_cfg);
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+ bus_clk = readl(&ccu->ahb1_apb1_div);
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+
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+ /* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
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+ setbits_le32(&ccu->pll6_cfg, BIT(25));
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+ }
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+
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/* Power up target CPU */
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sunxi_cpu_set_power(cpu, true);
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/* De-assert reset on target CPU */
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writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
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+ if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
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+ /* Spin until the BROM has clobbered the clock registers. */
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+ while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
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+
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+ /* Restore the registers and turn off PLL_PERIPH0 bypass. */
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+ writel(cpu_clk, &ccu->cpu_axi_cfg);
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+ writel(bus_clk, &ccu->ahb1_apb1_div);
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+
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+ clrbits_le32(&ccu->pll6_cfg, BIT(25));
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+ }
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+
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/* Unlock CPU (Disable external debug access) */
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setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
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index ad1f97632979..a2c74da81aa9 100644
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--- a/arch/arm/dts/sunxi-u-boot.dtsi
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+++ b/arch/arm/dts/sunxi-u-boot.dtsi
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@@ -6,7 +6,11 @@
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#define ARCH "arm"
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#endif
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-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
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+#if defined(CONFIG_MACH_SUN8I_H3)
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+#ifdef CONFIG_ARMV7_PSCI
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+#define RESUME_ADDR SUNXI_RESUME_BASE
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+#endif
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+#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
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#define BL31_ADDR 0x00044000
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#define SCP_ADDR 0x00050000
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#elif defined(CONFIG_MACH_SUN50I_H6)
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@@ -74,6 +78,20 @@
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};
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#endif
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+#ifdef RESUME_ADDR
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+ resume {
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+ description = "Super Standby resume image";
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+ type = "standalone";
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+ arch = ARCH;
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+ compression = "none";
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+ load = <RESUME_ADDR>;
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+
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+ blob-ext {
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+ filename = "u-boot-resume.img";
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+ };
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+ };
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+#endif
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+
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#ifdef SCP_ADDR
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scp {
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description = "SCP firmware";
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@@ -107,6 +125,9 @@
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firmware = "uboot";
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#endif
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loadables =
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+#ifdef RESUME_ADDR
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+ "resume",
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+#endif
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#ifdef SCP_ADDR
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"scp",
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#endif
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diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
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index 563635636624..2f0d69bdfce2 100644
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--- a/include/configs/sunxi-common.h
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+++ b/include/configs/sunxi-common.h
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@@ -15,6 +15,12 @@
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#include <asm/arch/cpu.h>
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#include <linux/stringify.h>
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+#ifdef SUNXI_SRAM_A2_SIZE
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+#define SUNXI_RESUME_BASE (CONFIG_ARMV7_SECURE_BASE + \
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+ CONFIG_ARMV7_SECURE_MAX_SIZE)
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+#define SUNXI_RESUME_SIZE 1024
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+#endif
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+
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/* Serial & console */
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#define CONFIG_SYS_NS16550_SERIAL
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/* ns16550 reg in the low bits of cpu reg */
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--
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2.33.0
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