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title, description
title description
EN7523 Family (EN7562CT) The EN7523 family documentation based on device tree analysis.

I sell my dev-broad, So, I can't continue to develop the Item. But if someone interest on it, use it freely.

The EN7523 family consists of the following devices:

Chip AFE/LD Description
EN7523(OT) EN7571N 2 CORE@1GHz xPON
EN7529(CT) EN7571N 2 CORE@1GHz xPON
EN7562(CT) AN7562 2 CORE@1GHz Gateway
EN7563(PT) AN7563 2 CORE@1GHz Gateway
  • EN7523 Family

EN7523DT EN7523DTM EN7523DU EN7523GU EN7523SU

  • EN7529 Family

EN7529CT EN7529CTM EN7529CU EN7529DT EN7529DTM EN7529DU EN7529GTH EN7529GTS EN7529IT EN7529ITM

  • EN7562 Family

EN7562CT EN7562CTM EN7562CU EN7562DT EN7562DTM EN7562DU EN7562GTH EN7562GTS

GPL SOURCE

We can get code directly from GPL OPENSOURCE

like:

  • NETGEAR EXS27(an7563pt, be5000), Based on OpenWrt 21.02 mediatek feed, Kernel 5.4
  • Zyxel PX3321-t1(an7529ct, ax3000), Based on OpenWrt 14.07 OEM custumed, kernel 4.4

Device Tree

diff -urN linux-4.4.115.orig/linux-ecnt/arch/arm/boot/dts/en7523.dts linux-4.4.115.sdk/linux-ecnt/arch/arm/boot/dts/en7523.dts
--- linux-4.4.115.orig/linux-ecnt/arch/arm/boot/dts/en7523.dts	1970-01-01 08:00:00.000000000 +0800
+++ linux-4.4.115.sdk/linux-ecnt/arch/arm/boot/dts/en7523.dts	2022-08-03 17:03:24.000000000 +0800
@@ -0,0 +1,488 @@
+
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+	compatible = "econet,en7523";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { 
+		bootargs = "root=/dev/mtdblock3 ro console=ttyS0,115200n8 earlycon init=/sbin/init";
+		stdout-path = &uart1;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		atf-reserved-memory@80000000 {
+			compatible = "econet,en7523-atf-reserved-memory";
+			no-map;
+			reg = <0x80000000 0x40000>;
+		};
+
+		npu_reserved: npu_binary@84000000 {
+			no-map;
+			reg = <0x84000000 0x100000>;
+		};
+
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	gic: interrupt-controller@09000000 {
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x09000000 0x20000>,
+			  <0x09080000 0x80000>;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+		its: gic-its@09020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cell = <1>;
+			reg = <0x090200000 0x20000>;
+		};
+	};
+
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <25000000>;
+	};
+
+	pmu {
+		//compatible = "arm,armv8-pmuv3";
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	npu@1e800000 {
+		compatible = "econet,ecnt-npu";
+		reg = <0x1e800000 0x60000>,		//NPU 384K SRAM
+			  <0x1e900000 0x313000>;	//NPU 16K SRAM, Registers
+		memory-region = <&npu_reserved>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 102+16 tr done
+                    <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 105+16 hadap irq0
+                    <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; //mbox2host irq
+	};
+
+	apb_timer1: apb_timer1@1fbf0100 {
+		compatible = "econet,ecnt-timer";
+		reg = <0x1fbf0100 0x40>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,					 
+			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;		
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	rbus@1fa00000 {
+		compatible = "econet,ecnt-rbus";
+		reg = <0x1fa00000 0x1000>;			//RBus Core
+	};
+
+	sram@1fa40000 {
+		compatible = "econet,ecnt-sram";
+		reg = <0x1fa40000 0x8000>,		//GDMP SRAM
+			  <0x08000000 0x40000>,		//L2C SRAM (only for CPU internal access)
+			  <0x1EFC0000 0x40000>,		//L2C SRAM (only for CPU/NPU/GDMA/SPI/Crypto/WOE external access via pbus)
+			  <0x1E880000 0x40000>,		//L2C SRAM (only for CPU/NPU/HSDMA/PCIE external access via npu_rbus)
+			  <0x1fbe3000 0x200>;		//I2C_SLAVE SRAM
+	};
+
+	scu@1fb00000 {
+		compatible = "econet,ecnt-scu";
+		reg = <0x1fb00000 0x960>,			//NP SCU
+			  <0x1fa20000 0x360>,			//CHIP SCU
+			  <0x1fa2FF30 0x10>;			//Rbus clk ctl for FPGA
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;			  
+	};
+
+	pcie@0x1fa91000 {
+	  compatible = "ecnt,pcie-en7523";
+	  device_type = "pci";
+	  reg = <0x1fa91000 0x1000>,
+		      <0x1fa92000 0x1000>,
+		      <0x1fa90000 0x1000>,	/* pcie top*/
+		      <0x1a100000 0x1000>,	/* switch lane */
+		      <0x1a148000 0x1000>,	/* 4, rc0 phy base, for change xtal setting */
+		      <0x1a14a000 0x1000>;	/* 5, rc1 phy base, for change xtal setting */
+    interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,  //23+16
+          		   <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;  //24+16
+	  bus-range = <0x00 0xff>;
+	  #address-cells = <3>;
+	  #size-cells = <2>;
+	  /* change xtal for 40M, default is 25M */
+	  /* change-xtal; */
+	  /* disable io coherent for RC and EP default. */
+	  /*dma-coherent;*/
+	  ranges = <0x82000000 0 0x20000000  0x20000000  0 0x10000000>;
+
+	  pcie0: pcie@0,0 {
+	    device_type = "pci";
+	    reg = <0x0000 0 0 0 0>;
+	    #address-cells = <3>;
+	    #size-cells = <2>;
+	    #interrupt-cells = <1>;
+	    ranges;
+	    interrupt-map-mask = <0 0 0 7>;
+	    interrupt-map = <0 0 0 1 &pcie_intc0 1>,
+			    		        <0 0 0 2 &pcie_intc0 2>,
+					            <0 0 0 3 &pcie_intc0 3>,
+					            <0 0 0 4 &pcie_intc0 4>;
+	    pcie-port = <0>;
+	    num-lanes = <1>;
+	    status = "okay";
+	    pcie_intc0: interrupt-controller {
+	          	      interrupt-controller;
+				            #address-cells = <0>;
+				            #interrupt-cells = <1>;
+			            };
+	  };
+
+	  pcie1: pcie@1,0 {
+			device_type = "pci";
+			reg = <0x0800 0 0 0 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 1>,
+			            		<0 0 0 2 &pcie_intc1 2>,
+					            <0 0 0 3 &pcie_intc1 3>,
+					            <0 0 0 4 &pcie_intc1 4>;
+			pcie-port = <1>;
+			num-lanes = <1>;
+			status = "okay";
+			pcie_intc1: interrupt-controller {
+				            interrupt-controller;
+				            #address-cells = <0>;
+				            #interrupt-cells = <1>;
+			            };
+		};
+	};
+
+	wdma{    
+    compatible = "en751221,wdma"; 
+    reg = <0x1fa06000 0x400 >,
+     			<0x1fa06400 0x400 >;    
+    interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,   
+      					 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,  
+        				 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,  
+        				 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,  
+        				 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,  
+        				 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 
+  };   
+    
+  wed{    
+    compatible = "en751221,wed";    
+    wed_num = <2>;
+    pci_slot_map = <0>, <1>;
+    reg = <0x1fa02000 0xb00 >,
+     			<0x1fa03000 0xb00 >;    
+    interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,   
+     						 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 
+  };  
+    
+  wed2{    
+    compatible = "en751221,wed2";    
+    wed_num = <2>;
+    pci_slot_map = <0>, <1>;
+    reg = <0x1fa02000 0xb00 >,
+     			<0x1fa03000 0xb00 >;    
+    interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 
+       					 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;  
+  };   
+  
+  wed_test{    
+    compatible = "en751221,wed_test";    
+    wed_num = <2>;
+    reg = <0x1fa02b00 0x100 >,
+     			<0x1fa03b00 0x100 >;    
+  };   
+
+
+
+	i2c@1fbf8000 {
+		compatible = "econet,ecnt-i2c";
+		reg = <0x1fbf8000 0x65>;	
+	};
+
+	gdump@1fbf9000 {
+		compatible = "econet,ecnt-gdump";
+		reg = <0x1fbf9000 0x84>;	
+	};
+	
+	crypto_k@1fb70000 {
+		compatible = "econet,ecnt-crypto_k";
+		reg = <0x1fb70000 0x804>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;			
+	};
+
+	trng@1faa1000 {
+		compatible = "econet,ecnt-trng";
+		reg = <0x1faa1000 0xc04>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;			
+	};
+	
+	gdma@1fb30000 {
+		compatible = "econet,ecnt-gdma";
+		reg = <0x1fb30000 0x2b0>;
+	};
+	
+	xsi@1fa60000 {
+		compatible = "econet,ecnt-xsi";
+		reg = <0x1fa60000 0x300>,	  //hsgmii ae
+		      <0x1fa70000 0x300>,   //hsgmii pcie0
+		      <0x1fa71000 0x300>,	  //hsgmii pcie1
+		      <0x1fa80000 0x300>;	  //hsgmii usb
+	};
+
+	i2c_slave@1fbe3300 {
+		compatible = "econet,ecnt-i2c_slave";
+		reg = <0x1fbe3300 0x10>;
+		dev0_addr = <0x60>;
+		dev1_addr = <0x62>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+	};
+	
+	uart1: serial@1fbf0000 {
+		compatible = "econet,ecnt-uart1";
+		reg = <0x1fbf0000 0x30>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		//status = "disabled";
+	};
+    uart2: serial@1fbf0300 {
+        compatible = "econet,ecnt-uart2";
+        reg = <0x1fbf0300 0x30>;
+        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+        //status = "disabled";
+    };
+	gpio@1fbf0200 {
+		compatible = "econet,ecnt-gpio";
+		reg = <0x1fbf0200 0x80>;
+	};
+
+	spi_ctrl: spi_controller@1fa10000 {
+		compatible = "econet,ecnt-spi_ctrl";
+		reg = <0x1fa10000 0x140>,		//SPI Controller Base
+			  <0x00000000 0x1000>;		//SPI Controller auto read interrupt test
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	spi_spi2nfi: spi_spi2nfi@1fa11000 {
+		compatible = "econet,ecnt-spi2nfi";
+		reg = <0x1fa11000 0x160>;	//NFI2SPI
+	};
+
+	spi_ecc: spi_ecc@1fa12000 {
+		compatible = "econet,ecnt-spi_ecc";
+		reg = <0x1fa12000 0x150>;	//NFI ECC
+	};
+
+	frame_engine: frame_engine@1fb50000 {
+		compatible = "econet,ecnt-frame_engine";
+		reg = <0x1fb50000 0x2600>,	//FE + PPE
+		      <0x1fb54000 0x4000>,	//QDMA
+		      <0x1fb58000 0x8000>;	//SWITCH
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
+			           <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
+			           <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
+			           <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
+			           <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
+			           <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
+			           <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
+			           <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
+			           <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
+			           <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
+	};
+	
+	spi_nor_flash: snor {
+		compatible = "econet,ecnt-snor";
+		spi-controller = <&spi_ctrl>;
+	};
+
+	nand_flash: nand@1fa10000 {
+		compatible = "econet,ecnt-nand";
+		spi-controller = <&spi_ctrl>;
+		spi2nfi = <&spi_spi2nfi>;
+		spi-ecc = <&spi_ecc>;
+	};
+
+	hsdma: dma-controller@1fa01800 {
+		compatible = "econet,en7523-hsdma";
+		reg = <0x1fa01800 0x300>;
+		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		dma-channels = <2>;
+		dma-requests = <2>;
+	};
+
+	cpu_top@1efb0000 {
+		compatible = "econet,ecnt-cpu_top";
+		reg = <0x1efbc800 0x10>;			//CTRL
+	};
+	
+	xpon_mac: xpon@1fb64000 {
+		compatible = "econet,ecnt-xpon";
+		reg = <0x1fb64000 0x3e8>,
+			<0x1fb66000 0x23c>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
+				       <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;// DYINGGASP INT 18+16
+	};
+
+	xhci_hcd: xhci@1fab0000 {
+		compatible = "econet,ecnt-xhci";
+		reg = <0x1fab0000 0x3e00>,      //MAC base address
+			<0x1fab3e00 0x100>;     //IPPC base address
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pon_phy: pon_phy@1faf0000 {
+		compatible = "econet,ecnt-pon_phy";
+		reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
+		      <0x1fa2ff24 0x4>,			// PON_PHY_FPGA_RG_TX_OFF
+			  <0x1faf3000 0xfff>,			// PON_PHY_ASIC_RG range2
+			  <0x1faf4000 0xfff>;			// PON_PHY_ASIC_RG range3
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
+	};
+
+	pcm@bfbd0000 {
+		compatible = "econet,ecnt-pcm";
+		reg = <0x1fbd0000 0x4fff>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	i2s@1fbe2200 {
+		compatible = "econet,ecnt-i2s";
+		reg = <0x1fbe2200 0xfc>,
+			  <0x1fbe2e00 0x114>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;		
+	};
+	
+	pcie_phy: pcie_phy@1fa93700 {
+		compatible = "econet,en7523-pcie_phy";
+		reg = <0x1fa93700 0x568>,		//PC0 RG range		
+			<0x1fa95700 0x568>;		//PC1 RG range
+	};
+	pon_hsgmii: pon_hsgmii@1fa65000 {
+		compatible = "econet,ecnt-pon_hsgmii";
+		reg = <0x1fa65100 0x4a0>,		//PCS mode1 range
+			<0x1fa65a00 0x1ac>,		//PCS mode2 range
+			<0x1fa65e00 0x64>,		//AN range
+			<0x1fa66000 0xdc>;		//rate adaption range
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;	// pon_hsgmii INT 50+16
+	};
+	sgmii_p0: sgmii_p0@1fa72000 {
+		compatible = "econet,ecnt-sgmii";
+		reg = <0x1fa72100 0x4a0>,		//PCS mode1 range
+			<0x1fa72a00 0x160>,		//PCS mode2 range
+			<0x1fa72000 0x64>,		//AN range
+			<0x1fa72600 0xdc>,		//rate adaption range
+			<0x1fa72c00 0x3b0>;		//phya
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;	// pc0_hsgmii INT 135+16
+		int_name = "sgmii_pcie0";
+		int_id = <0>;
+	};
+	sgmii_p1: sgmii_p1@1fa77000 {
+		compatible = "econet,ecnt-sgmii";
+		reg = <0x1fa77100 0x4a0>,		//PCS mode1 range
+			<0x1fa77a00 0x160>,		//PCS mode2 range
+			<0x1fa77000 0x64>,		//AN range
+			<0x1fa77600 0xdc>,		//rate adaption range
+			<0x1fa77c00 0x3b0>;		//phya
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;	// pc1_hsgmii INT 136+16
+		int_name = "sgmii_pcie1";
+		int_id = <1>;
+	};
+	sgmii_u0: sgmii_u0@1fa81000 {
+		compatible = "econet,ecnt-sgmii";
+		reg = <0x1fa81100 0x4a0>,		//PCS mode1 range
+			<0x1fa81a00 0x160>,		//PCS mode2 range
+			<0x1fa81000 0x64>,		//AN range
+			<0x1fa81600 0xdc>,		//rate adaption range
+			<0x1fa81c00 0x3b0>;		//phya
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;	// usb_hsgmii INT 137+16
+		int_name = "sgmii_usb0";
+		int_id = <2>;
+	};
+	
+	usb_phy@1fad0000 {
+		compatible = "econet,ecnt-usb_phy";
+		reg = <0x1fad0000 0x1fff>;		
+	};
+
+	thermal_phy: thermal_phy@1efbd000 {
+		compatible = "econet,ecnt-thermal_phy";		
+		reg = <0x1efbd000 0x0fff>; //ptp_thermal_ctrl
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;	// ptp_therm INT 7+16
+		int_name = "ptp_therm";
+	};
+
+
+};

EN7523

Public informations about the different hardware blocks are hard to come by. Many blocks are related to Mediatek hardware. In some cases specifications or drivers for it exists.

EN7529CT is a highly integrated single-chip solution for xPON application. It integrates four Ethernet GPHYs, one DDR3 controller, one USB3.0 host, one USB2.0 host, two PCIe Gen2 ports, and also a PCM controller with ISI/ZSI compatible interface for VoIP application, so that fully meets future smart home gateway requirements. EN7529CT features a 1.0GHz ARM CA53 dual-core CPU and a powerful Xmart Packet Accelerator (XPA), which can support unmatched network features with extremely high packet processing capability.

With XPA, EN7529CT performs an advanced QoS, security and flexible protocol management.

EN7529CT also integrate three proprietary RISC-V cores to accelerate WiFi and security applications. By leading power-saving technology, EN7529CT makes system board design simple and easy, so as to provide unique solution with low system cost and ultra-low power consumption in themarket.

FEATURES

Highly integrated WANinterfaces

  • Compliant with ITU-T G.984/G.988 and IEEE802.3ah standards
  • Onesingle chip solution designed for EPON/GPONapplication.
  • Support ActiveEthernet
  • GPONsupport 32-TCONTs, 256 GEM port, with flexible GEM port to T-CONTs mapping mechanism, and status report/traffic monitor DBAmode
  • GPONsupport AES-128 decryption andencryption
  • EPONsupport 8 LLIDs, triple-churning decryption algorithm defined byCTC
  • Support PON rouge ONU detection, dying-gasp, Type-C optical protectionswitching
  • Providing MIB counters and sniffer function for quickly field debugpurpose

Un-matched and Xmart packet processingengine

  • Xmartpacket accelerator can support wire-speed packet processing and forwarding capability without CPU’s involvement
  • Support up to 32K flows, including L2 bridge, IPv4 NAT/Routing, IPv4 NAPT,IPv6 3/5-tuple routing, 6RD and DS-LITE, NPTv6, VxLAN,NVGRE
  • Powerful traffic classification engine parsing L2 to L4 headerinformation
  • Flexible VLAN translation functions defined in TR-156 and CTCSpec.
  • Support L2 and L3 multicast streams and multicast VLANtranslation
  • Configurable packet buffer location with efficient page-based link-list buffer

management

  • Effective QoS scheme including per-flow TrTCM traffic shaping, SP/WRR/SP+WRR for traffic scheduling, tail-drop and RED for congestionhandling
  • Support up to 16K jumboframe Highly integrated LAN interfaces
  • x4GEPHY
  • x3HSGMIIcombo with PCIE/USBSerDes.

Powerful SoC platform

  • 1.0GHzARMCA53dual-core CPU, 256K L2cache
  • Integrate three proprietary RISC-V cores for WiFi and securityacceleration
  • Support up to 1GB DDR3-1866SDRAM
  • Support SPI NOR/NANDflash
  • TwoPCIeGen2interfaces for dual-band WiFiapplication
  • OneUSB3.0 interface and one USB 2.0interface
  • Provide one PCM or two ZSI/ISIinterfaces
  • Built-in crypto engine for securityapplication
  • TwoUARTs
  • OneI2Cmaster and one I2Cslave

Block Diagram

SerDes Configuration

SerDes Name Mode
PONSerDes PON/HSGMII/5GBASE-R
PCIe Gen2 SerDes PCIe Gen2/HSGMII
USB3 SerDes USB3/HSGMII

Hardware Blocks

EFUSE

TBD

GDMA (removed staging driver)

Generic DMA The driver for ralink DMA is similar. Source code

Related Specifications Chapter 2.11, page 154

GPIO/Pinctrl (WIP)

GPIO controller Driver based on an7581-pinctrl.c has been written and should work.

pinctrl-airoha.c

airoha,en7523-gpio.yaml

I2C (present in kernel tree)

I2C The same driver as for the MT7621 should work.

Source code

Related Specifications

Chapter 2.7, page 49

Switch (present in kernel tree)

Internal switch. The switch is MT7530-based and the same code for the AN7581 should work. The switch also provide the MDIO-bus.

Source code

Related Specifications

Specifications for MT7531

UART (patches posted)

Serial port, the EN7523 CD has 2 ports. The UART seems to be the same as in other SoCs from EcoNet/Airoha.

Patches

Use ns16550 compatible string for UART1 and airoha,en7523-uart for UART2.

USB2/USB3

TBD

Related Specifications

Chapter 2.2, Page 6

System Architecture

CPU Configuration

  • Architecture: ARM Cortex-A53 dual-core
  • Frequency: 1GHz (default 80MHz clock frequency)
  • Cache: Shared L2 cache
  • Power Management: PSCI (Power State Coordination Interface) support

Memory Configuration

  • DDR Memory: 0x80000000 - 0xC0000000 (1GB)
  • Reserved Memory:
    • ATF Reserved Memory: 0x80000000 - 0x80040000 (256KB)
    • NPU Binary: 0x84000000 - 0x84100000 (1MB)

Interrupt Controller

  • Type: ARM GIC-v3 (Generic Interrupt Controller)
  • Base Address: 0x09000000
  • ITS Support: 0x09020000 (MSI interrupt support)

Peripherals

System Controller (SCU)

Compatible: econet,ecnt-scu Base Address: 0x1fb00000 (NP SCU), 0x1fa20000 (CHIP SCU) Description: System Control Unit responsible for clock control, reset management and system configuration Interrupt: GIC_SPI 47

Note: The SCU driver uses memory region overlapping with pinctrl driver. A dirty hack was implemented to make both drivers coexist.

The Linux mainline use compatible = "airoha,en7523-scu";.

airoha,en7523-scu.yaml

Pin Controller (PINMUX)

Compatible: airoha,en7523-pinctrl Base Addresses:

  • IOMUX Control Registers: 0x1fa20210
  • IO TX Driving Control Registers: 0x1fa2001C
  • IO Pull up/down Control Registers: 0x1fa20044
  • LED Mapping Register: 0x1fa20278

Pin Groups:

  • uart2grp: UART2 function
  • siporclckgrp: SIPO RCLK function
  • mdiogrp: MDIO function
  • pongrp: PON function

Note: Memory regions overlap with SCU driver. Synchronization is maintained through is_pinctrl_reg() function.

GPIO Controller

Compatible: airoha,en7523-gpio

GPIO Bank A (gpio0@1fbf0200)

GPIO Range: 0-31 Base Address: 0x1fbf0200 series Interrupt: GIC_SPI 26 Bank Name: gpio_a (u-boot specific)

Registers:

  • Data Register: 0x1fbf0204
  • Control Register: 0x1fbf0200
  • Control1 Register: 0x1fbf0220
  • Open Drain Register: 0x1fbf0214
  • Interrupt Status Register: 0x1fbf0208
  • Level 0/1 Registers: 0x1fbf0210, 0x1fbf028C
  • Edge 0/1 Registers: 0x1fbf020C, 0x1fbf0280

GPIO Bank B (gpio1@1fbf0270)

GPIO Range: 32-63 Base Address: 0x1fbf0270 series Interrupt: GIC_SPI 26 Bank Name: gpio_b (u-boot specific)

Registers:

  • Data Register: 0x1fbf0270
  • Control Registers: 0x1fbf0260, 0x1fbf0264
  • Open Drain Register: 0x1fbf0278
  • Interrupt Status Register: 0x1fbf027C
  • Level 0/1 Registers: 0x1fbf0290, 0x1fbf0294
  • Edge 0/1 Registers: 0x1fbf0284, 0x1fbf0288

UART Serial Ports

Compatible: airoha,en7523-uart

UART1 (Console)

Base Address: 0x1fbf0000 Interrupt: GIC_SPI 18 Clock Frequency: 1843200 Hz Configuration: 115200n8 (default console) Status: Enabled Properties:

  • reg-io-width: 4
  • reg-shift: 2

The OpenWrt use compatible = "ns16550";.

UART2

Base Address: 0x1fbf0300 Interrupt: GIC_SPI 32 Clock Frequency: 7372800 Hz Status: Disabled (requires pinctrl configuration) Pinctrl: Uses pinctrl_uart2 group

Network Processing Unit (NPU)

Compatible: econet,ecnt-npu Base Addresses:

  • NPU 384K SRAM: 0x1e800000
  • NPU Registers: 0x1e900000 Memory Region: Dedicated reserved memory area Interrupts: Multiple interrupt lines (GIC_SPI 118-125)
  • TR Done: GIC_SPI 118-120
  • HADAP IRQ0: GIC_SPI 121-123
  • MBOX2HOST IRQ: GIC_SPI 125

airoha_npu.c

Frame Engine (Network Engine)

Frame Engine is a network processing engine that handles packet processing, offloading, and management of network traffic.

Compatible: econet,ecnt-frame_engine Base Addresses:

  • FE + PPE: 0x1fb50000
  • QDMA: 0x1fb54000
  • SWITCH: 0x1fb58000

Interrupts:

  • QDMA LAN INT1-4: GIC_SPI 37, 55-57
  • QDMA WAN INT1-4: GIC_SPI 38, 58-60
  • FE ERROR INTR: GIC_SPI 49
  • PDMA INTR: GIC_SPI 64

In the updated products such as AN7581, use eth + switch instead of frame_engine. Maybe we can use the solution from AN7581.

And the switch may be MT7530.

airoha_eth.c

The en7562's frame engine is based on the en7512 but have some features from the en7581. So we use the an7581 driver is not working.

GDMA Controller

Compatible: econet,ecnt-gdma Base Address: 0x1fb30000 Description: General-purpose DMA controller Register Size: 0x2b0

High-Speed DMA (HSDMA)

Compatible: econet,ecnt-hsdma Base Address: 0x1fa01800 Interrupt: GIC_SPI 63 Channels: 2 DMA channels Requests: 2 DMA requests Properties:

  • #dma-cells: 1

SPI Flash Controller

Compatible: econet,en75xx-spi Base Address: 0x1fa10000 Interrupt: GIC_SPI 51 Register Size: 0x140

spi-airoha-snfi.c

Child Devices:

  • SPI NAND: Compatible spi-nand
    • Chip Select: 0
    • TX/RX Bus Width: 2
    • Max Frequency: 50MHz

Related Controllers:

  • SPI2NFI: econet,ecnt-spi2nfi @ 0x1fa11000
  • SPI ECC: econet,ecnt-spi_ecc @ 0x1fa12000

Crypto Engine

Compatible: econet,ecnt-crypto_k Base Address: 0x1fb70000 Interrupt: GIC_SPI 44 Register Size: 0x804 Description: Hardware cryptographic acceleration engine

True Random Number Generator (TRNG)

Compatible: airoha,airoha-trng Base Address: 0x1faa1000 Interrupt: GIC_SPI 35 Register Size: 0xc04

airoha-trng.c

PCIe Controller

Compatible: ecnt,pcie-ecnt Base Addresses:

  • PCIe Controller: 0x1fa91000, 0x1fa92000
  • PCIe Top: 0x1fa90000
  • Switch Lane: 0x1a100000
  • RC0/RC1 PHY Base: 0x1a148000, 0x1a14a000

Configuration: Dual-port PCIe, 1 lane per port Interrupts:

  • Port 0: GIC_SPI 39
  • Port 1: GIC_SPI 40 Bus Range: 0x00-0xff Ranges: 0x82000000 0 0x20000000 0x20000000 0 0x10000000

The PCIe compatible string is "mediatek,mt7622-pcie".

PCIe Port 0 (pcie@0,0)

PCI Slot: 0x0000 Lanes: 1 Status: Enabled

PCIe Port 1 (pcie@1,0)

PCI Slot: 0x0800 Lanes: 1 Status: Enabled

USB Controller (xHCI)

Compatible: econet,ecnt-xhci Base Addresses:

  • MAC Base: 0x1fab0000
  • IPPC Base: 0x1fab3e00 Interrupt: GIC_SPI 33 Description: USB 3.0 host controller

PON (Passive Optical Network)

PON MAC (xpon_mac)

Compatible: econet,ecnt-xpon Base Addresses:

  • XPON MAC: 0x1fb64000
  • EPON MAC: 0x1fb66000 Interrupts:
  • XPON MAC INT: GIC_SPI 42
  • DYING GASP INT: GIC_SPI 34

PON PHY

Compatible: econet,ecnt-pon_phy Base Addresses:

  • PON_PHY_ASIC_RG: 0x1faf0000
  • PON_PHY_FPGA_RG_TX_OFF: 0x1fa2ff24
  • PON_PHY_ASIC_RG range2: 0x1faf3000
  • PON_PHY_ASIC_RG range3: 0x1faf4000 Interrupt: GIC_SPI 43 (XPON_PHY_INTR)

PON HSGMII

Compatible: econet,ecnt-pon_hsgmii Base Addresses:

  • PCS Mode1: 0x1fa65100
  • PCS Mode2: 0x1fa65a00
  • AN Range: 0x1fa65e00
  • Rate Adaption: 0x1fa66000 Interrupt: GIC_SPI 66

I2C Controllers

I2C Master (i2c0)

Compatible: econet,ecnt-i2c Base Address: 0x1fbf8000 Register Size: 0x65

The compatible string is compatible = "mediatek,mt7621-i2c";.

I2C Slave

Compatible: econet,ecnt-i2c_slave Base Address: 0x1fbe3300 Device Addresses: 0x60, 0x62 Interrupt: GIC_SPI 28 SRAM: 0x1fbe3000 (512 bytes)

Audio Controllers

PCM Audio

Compatible: econet,ecnt-pcm Base Address: 0x1fbd0000 Interrupt: GIC_SPI 27 Register Size: 0x4fff Description: VoIP voice processing

I2S Audio

Compatible: econet,ecnt-i2s Base Addresses:

  • I2S Controller: 0x1fbe2200
  • I2S Extended: 0x1fbe2e00 Interrupt: GIC_SPI 48

PWM Controller

Compatible: airoha,en7523-pwm Base Address: 0x1fbf0200 series Status: Disabled (requires pinctrl configuration) Properties: #pwm-cells: 3

Registers:

  • Flash Mode Config: 0x1fbf0234
  • Flash Period Set 0-3: 0x1fbf023C-0x1fbf0248
  • Flash Map Config 0-1: 0x1fbf024C-0x1fbf0250
  • Cycle Config Value 0-1: 0x1fbf0298-0x1fbf029C
  • SIPO Registers: 0x1fbf0230, 0x1fbf0254-0x1fbf025C
  • SIPO Clock: 0x1fbf0228, 0x1fbf022C

Watchdog Timer

Compatible: airoha,en75xx-wdt Timeout: 30 seconds Properties: #interrupt-cells: 1

airoha_wdt.c

Timer Controller

Compatible: econet,ecnt-timer Base Address: 0x1fbf0100 Register Size: 0x40 Interrupts: GIC_SPI 20-22, 25

The compatible string is compatible = "arm,armv8-timer";.

Thermal Management

Compatible: econet,ecnt-thermal_phy Base Address: 0x1efbd000 (ptp_thermal_ctrl) Interrupt: GIC_SPI 23 (ptp_therm) Register Size: 0x0fff

airoha_thermal.c

WED (Wireless Ethernet Dispatch)

WED Controller

Compatible: en751221,wed Base Addresses: 0x1fa02000, 0x1fa03000 Interrupts: GIC_SPI 67, 68 WED Number: 2 PCI Slot Map: 0, 1

WED2 Controller

Compatible: en751221,wed2 Base Addresses: 0x1fa02000, 0x1fa03000 Interrupts: GIC_SPI 67, 68 WED Number: 2 PCI Slot Map: 0, 1

WED Test

Compatible: en751221,wed_test Base Addresses: 0x1fa02b00, 0x1fa03b00 WED Number: 2

WDMA Controller

Compatible: en751221,wdma Base Addresses: 0x1fa06000, 0x1fa06400 Interrupts: GIC_SPI 69-74

SGMII Interfaces

SGMII PCIe0 (sgmii_p0)

Compatible: econet,ecnt-sgmii Base Addresses:

  • PCS Mode1: 0x1fa72100
  • PCS Mode2: 0x1fa72a00
  • AN Range: 0x1fa72000
  • Rate Adaption: 0x1fa72600
  • PHYA: 0x1fa72c00 Interrupt: GIC_SPI 151 (pc0_hsgmii) Interface: sgmii_pcie0 (ID: 0)

SGMII PCIe1 (sgmii_p1)

Compatible: econet,ecnt-sgmii Base Addresses:

  • PCS Mode1: 0x1fa77100
  • PCS Mode2: 0x1fa77a00
  • AN Range: 0x1fa77000
  • Rate Adaption: 0x1fa77600
  • PHYA: 0x1fa77c00 Interrupt: GIC_SPI 152 (pc1_hsgmii) Interface: sgmii_pcie1 (ID: 1)

SGMII USB (sgmii_u0)

Compatible: econet,ecnt-sgmii Base Addresses:

  • PCS Mode1: 0x1fa81100
  • PCS Mode2: 0x1fa81a00
  • AN Range: 0x1fa81000
  • Rate Adaption: 0x1fa81600
  • PHYA: 0x1fa81c00 Interrupt: GIC_SPI 153 (usb_hsgmii) Interface: sgmii_usb0 (ID: 2)

PHY Interfaces

PCIe PHY

Compatible: econet,ecnt-pcie_phy Base Addresses:

  • PC0 RG Range: 0x1fa93700
  • PC1 RG Range: 0x1fa95700

phy-airoha-pcie.c

USB PHY

Compatible: econet,ecnt-usb_phy Base Address: 0x1fad0000 Register Size: 0x1fff

XSI (High-Speed Serial Interface)

Compatible: econet,ecnt-xsi Base Addresses:

  • HSGMII AE: 0x1fa60000
  • HSGMII PCIe0: 0x1fa70000
  • HSGMII PCIe1: 0x1fa71000
  • HSGMII USB: 0x1fa80000

System Support

RBUS Core

Compatible: econet,ecnt-rbus Base Address: 0x1fa00000 Register Size: 0x1000 Description: Bus core controller

SRAM Controller

Compatible: econet,ecnt-sram Base Addresses:

  • GDMP SRAM: 0x1fa40000
  • L2C SRAM (CPU internal): 0x08000000
  • L2C SRAM (external via pbus): 0x1EFC0000
  • L2C SRAM (external via npu_rbus): 0x1E880000
  • I2C_SLAVE SRAM: 0x1fbe3000

GDUMP

Compatible: econet,ecnt-gdump Base Address: 0x1fbf9000 Register Size: 0x84 Description: Debug dump controller

CPU Top

Compatible: econet,ecnt-cpu_top Base Address: 0x1efbc800 Register Size: 0x10 Description: CPU top control

Address Map

Address Size Name Description
0x09000000 0x20000 GIC ARM GIC-v3 Interrupt Controller
0x09080000 0x80000 GIC CPU GIC CPU Interface
0x1e800000 0x60000 NPU SRAM NPU 384KB SRAM
0x1e900000 0x313000 NPU Registers NPU Register Area
0x1fa00000 0x1000 RBUS Bus Core
0x1fa01800 0x300 HSDMA High-Speed DMA
0x1fa02000 0xb00 WED Wireless Ethernet Dispatch
0x1fa06000 0x400 WDMA Wireless DMA
0x1fa10000 0x140 SPI Controller SPI Flash Controller
0x1fa11000 0x160 SPI2NFI SPI to NFI
0x1fa12000 0x150 SPI ECC SPI ECC Controller
0x1fa20000 0x360 CHIP SCU Chip System Control Unit
0x1fa40000 0x8000 GDMP SRAM GDMP SRAM
0x1fa60000 0x300 XSI High-Speed Serial Interface
0x1fa65000 - PON HSGMII PON High-Speed GMII
0x1fa72000 - SGMII PCIe0 SGMII PCIe Port 0
0x1fa77000 - SGMII PCIe1 SGMII PCIe Port 1
0x1fa81000 - SGMII USB SGMII USB
0x1fa91000 0x1000 PCIe PCIe Controller
0x1fa93700 0x568 PCIe PHY PCIe Physical Layer
0x1faa1000 0xc04 TRNG True Random Number Generator
0x1fab0000 0x3e00 xHCI USB 3.0 Host Controller
0x1fad0000 0x1fff USB PHY USB Physical Layer
0x1faf0000 0x800 PON PHY PON Physical Layer
0x1fb00000 0x960 NP SCU Network Processor SCU
0x1fb30000 0x2b0 GDMA General-purpose DMA
0x1fb50000 0x2600 Frame Engine Network Frame Processing Engine
0x1fb54000 0x4000 QDMA Queue DMA
0x1fb58000 0x8000 Switch Ethernet Switch
0x1fb64000 0x3e8 XPON MAC PON MAC Layer
0x1fb70000 0x804 Crypto Engine Hardware Cryptographic Engine
0x1fbd0000 0x4fff PCM Audio PCM
0x1fbe2200 0xfc I2S Audio I2S
0x1fbe3300 0x10 I2C Slave I2C Slave Controller
0x1fbf0000 0x30 UART1 Serial Port 1
0x1fbf0100 0x40 Timer APB Timer
0x1fbf0200 0x7C GPIO GPIO Controller
0x1fbf0300 0x30 UART2 Serial Port 2
0x1fbf8000 0x65 I2C I2C Master Controller
0x1fbf9000 0x84 GDUMP Debug Dump
0x1efbc800 0x10 CPU Top CPU Top Control
0x1efbd000 0x0fff Thermal PHY Thermal Management

Interrupt Map

Based on GIC-v3 interrupt controller, all interrupts are handled through SPI (Shared Peripheral Interrupt):

Interrupt Name Description
GIC_SPI 18 UART1 Serial Port 1 Interrupt
GIC_SPI 20-22,25 Timer APB Timer Interrupts
GIC_SPI 23 Thermal Thermal Sensor Interrupt
GIC_SPI 26 GPIO GPIO Controller Interrupt
GIC_SPI 27 PCM Audio PCM Interrupt
GIC_SPI 28 I2C Slave I2C Slave Device Interrupt
GIC_SPI 32 UART2 Serial Port 2 Interrupt
GIC_SPI 33 xHCI USB 3.0 Interrupt
GIC_SPI 34 DYING GASP Power Loss Detection Interrupt
GIC_SPI 35 TRNG Random Number Generator Interrupt
GIC_SPI 37 QDMA LAN QDMA LAN Interrupt 1
GIC_SPI 38 QDMA WAN QDMA WAN Interrupt 1
GIC_SPI 39-40 PCIe PCIe Port 0/1 Interrupts
GIC_SPI 42 XPON MAC PON MAC Interrupt
GIC_SPI 43 PON PHY PON Physical Layer Interrupt
GIC_SPI 44 Crypto Engine Hardware Cryptographic Interrupt
GIC_SPI 47 SCU System Control Unit Interrupt
GIC_SPI 48 I2S Audio I2S Interrupt
GIC_SPI 49 Frame Engine Error Network Frame Engine Error Interrupt
GIC_SPI 51 SPI Controller SPI Flash Controller Interrupt
GIC_SPI 55-60 QDMA Extended QDMA LAN/WAN Extended Interrupts
GIC_SPI 63 HSDMA High-Speed DMA Interrupt
GIC_SPI 64 PDMA PDMA Interrupt
GIC_SPI 66 PON HSGMII PON High-Speed GMII Interrupt
GIC_SPI 67-68 WED Wireless Ethernet Dispatch Interrupts
GIC_SPI 69-74 WDMA Wireless DMA Interrupts
GIC_SPI 118-125 NPU Network Processing Unit Interrupts
GIC_SPI 151-153 SGMII SGMII Interface Interrupts

Airoha EN7523 Pinctrl Driver

GPIO and Pin Configuration

The EN7523 SoC features 39 physical pins that can be configured for various functions. Each pin can be configured with different electrical characteristics:

  • Drive strength: 2mA (default), 4mA, 6mA, or 8mA
  • Bias control: Disable bias, Enable pull-up, or Enable pull-down

GPIO Pin Functions

GPIO Pin Physical Pin Primary Function Alternate Functions
GPIO0-GPIO5 12-17 General purpose I/O Reserved on EN7523
GPIO6 18 General purpose I/O PCIE_RESET1_GPIO_MODE
GPIO7 19 General purpose I/O -
GPIO8 20 General purpose I/O I2C1 (SCL), SGMII_MDIO, PCM_SPI1_CS3
GPIO9 21 General purpose I/O I2C1 (SDA), SGMII_MDIO, TOD, SPI0_CS1
GPIO10 22 General purpose I/O PCM_SPI1_CS1
GPIO11 23 General purpose I/O PCM_SPI1_CS4
GPIO12 24 General purpose I/O PCM1, PCM_SPI1
GPIO13 25 General purpose I/O SIPO, SIPO_RCLK, NPU_UART
GPIO14 26 General purpose I/O I2C0_SLAVE, PCM_SPI1_RESET, SPI0_QUAD
GPIO15 27 General purpose I/O I2C0_SLAVE, PCM_SPI1_INT, SPI0_QUAD
GPIO16 28 General purpose I/O LAN3_LED1, PCM2, I2S, PCM_SPI1
GPIO17 29 General purpose I/O LAN2_LED1, PCM2, I2S, PCM_SPI1
GPIO18 30 General purpose I/O LAN1_LED1, PCM2, I2S, PCM_SPI1
GPIO19 31 General purpose I/O LAN0_LED1, PCM2, I2S, PCM_SPI1
GPIO20 32 General purpose I/O UART2 (TX), SGMII_MDIO, PCM_SPI1_CS3
GPIO21 33 General purpose I/O UART2 (RX), SGMII_MDIO, TOD, SPI0_CS1
GPIO22 34 General purpose I/O -
GPIO23 35 General purpose I/O -
GPIO24 36 General purpose I/O PCM1, PCM_SPI1
GPIO25 37 General purpose I/O PCM1, PCM_SPI1
GPIO26 38 General purpose I/O PCM1, PCM_SPI1
GPIO27 39 General purpose I/O PCM1, PCM_SPI1, PCM_SPI1_CS2_156
- 40 PAD_PCIE_RESET0 GPIO28
- 41 PAD_PCIE_RESET1 GPIO29, PCM_SPI1_CS2_128

Function Groups

Communication Interfaces

  • UART2: GPIO20 (TX), GPIO21 (RX)
  • I2C1: GPIO8 (SCL), GPIO9 (SDA)
  • I2C0 Slave: GPIO14, GPIO15
  • MDIO: GPIO8, GPIO9
  • SPI Quad: GPIO14, GPIO15
  • SPI CS1: GPIO21

Audio Interfaces

  • PCM1: GPIO24, GPIO25, GPIO26, GPIO27
  • PCM2: GPIO16, GPIO17, GPIO18, GPIO19
  • I2S: GPIO16, GPIO17, GPIO18, GPIO19
  • PCM_SPI1: Various configurations with CS1-CS4 options

Network Interfaces

  • PON (Passive Optical Network): Defined in pon0_grp
  • LAN LED Control:
    • LAN0: GPIO37 (LED0), GPIO19 (LED1)
    • LAN1: GPIO36 (LED0), GPIO18 (LED1)
    • LAN2: GPIO35 (LED0), GPIO17 (LED1)
    • LAN3: GPIO34 (LED0), GPIO16 (LED1)

Debug Interfaces

  • JTAG UDI: Defined in jtag_udi_grp
  • JTAG DFD: Defined in jtag_dfd_grp
  • NPU UART: GPIO13, GPIO38

Miscellaneous

  • SIPO (Serial In, Parallel Out): GPIO13, GPIO38
  • SIPO RCLK: GPIO13, GPIO30, GPIO38
  • TOD (Time of Day): GPIO21
  • PCIe Reset as GPIO: GPIO28 (PCIE_RESET0), GPIO29 (PCIE_RESET1)

LED Mapping

The EN7523 supports flexible LED mapping for LAN ports:

  • Each LAN port (LAN0-LAN3) has two LEDs (LED0 and LED1)
  • Each LED can be mapped to any of five LAN functions (LAN0-LAN4)
  • Example mappings:
    • lan0_led0_to_lan2_led0: Maps LAN0's LED0 to LAN2's LED0 function
    • lan3_led1_to_lan4_led1: Maps LAN3's LED1 to LAN4's LED1 function

Device Tree Configuration Example

pinctrl: pinctrl@1fa20210 {
    compatible = "airoha,en7523-pinctrl";
    reg = <0x1fa20210 0x20>,  /* IOMUX Control Registers */
          <0x1fa20044 0x20>,  /* IO Pull up/down Control Registers */
          <0x1fa2001C 0x20>,  /* IO TX Driving Control Registers */
          <0x1fa20278 0x10>;  /* LED Mapping Register */
          
    status = "okay";
    
    pinctrl_uart2: uart2 {
        function = "uart2";
        groups = "uart2_grp";
        drive-strength = <4>;
    };
    
    pinctrl_mdio: mdio {
        function = "mdio";
        groups = "mdio_grp";
        bias-pull-up;
    };
    
    pinctrl_sipo_rclk: sipo_rclk {
        function = "sipo_rclk";
        groups = "sipo_rclk_grp";
    };
    
    pinctrl_pon: pon {
        function = "pon0";
        groups = "pon0_grp";
    };
};

uart2: serial@1fbf0300 {
    compatible = "airoha,en7523-uart";
    reg = <0x1fbf0300 0x30>;
    interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart2>;
    status = "okay";
};

Pin Configuration Options

The driver supports the following configuration options:

Drive Strength

drive-strength = <2>;  // 2mA
drive-strength = <4>;  // 4mA
drive-strength = <6>;  // 6mA
drive-strength = <8>;  // 8mA

Bias Control

bias-disable;         // Disable pull-up and pull-down
bias-pull-up;         // Enable pull-up
bias-pull-down;       // Enable pull-down

Function Selection

Specify the desired function with the function property in a pin controller node:

function = "uart2";   // Select UART2 function
function = "mdio";    // Select MDIO function
function = "i2c1";    // Select I2C1 function

Implementation Notes

  • GPIO0-GPIO5 are reserved on the EN7523 SoC
  • PAD_PCIE_RESET0 and PAD_PCIE_RESET1 can be configured as GPIO28 and GPIO29
  • The driver handles all register programming required for function selection, pull-up/down control, and drive strength configuration
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