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52 lines
2.1 KiB
Diff
52 lines
2.1 KiB
Diff
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33580
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From 969c946025186d15b5b66006bd393a3782ce47ce Mon Sep 17 00:00:00 2001
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From: Danylo Piliaiev <dpiliaiev@igalia.com>
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Date: Mon, 17 Feb 2025 14:52:34 +0100
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Subject: [PATCH] tu/a6xx: Emit VSC addresses for each bin to restore after
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preemption
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KGSL unconditionally supports preemption so we cannot ignore it.
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On a6xx, we have to emit VSC addresses per-bin or make the amble include
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these registers, because CP_SET_BIN_DATA5_OFFSET will use the
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register instead of the pseudo register and its value won't survive
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across preemptions. The blob seems to take the second approach and
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emits the preamble lazily. We chose the per-bin approach but blob's
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should be a better one.
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Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12627
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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
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---
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src/freedreno/vulkan/tu_cmd_buffer.cc | 7 ++++++-
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1 file changed, 6 insertions(+), 1 deletion(-)
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diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
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index 7f3bc5dbc30aa..ef120c9d44fdb 100644
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--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
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+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
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@@ -1093,6 +1093,10 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
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tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START) |
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A6XX_CP_SET_MARKER_0_USES_GMEM);
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+ if (CHIP == A6XX && cmd->device->physical_device->has_preemption) {
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+ tu_emit_vsc<CHIP>(cmd, &cmd->cs);
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+ }
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+
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tu6_emit_bin_size<CHIP>(
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cs, tiling->tile0.width, tiling->tile0.height,
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{
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@@ -2183,7 +2187,8 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
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* these registers, because CP_SET_BIN_DATA5_OFFSET will use the
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* register instead of the pseudo register and its value won't survive
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* across preemptions. The blob seems to take the second approach and
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- * emits the preamble lazily.
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+ * emits the preamble lazily. We chose the per-bin approach but blob's
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+ * should be a better one.
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*/
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tu_emit_vsc<CHIP>(cmd, cs);
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--
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GitLab
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