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2159 lines
81 KiB
C
2159 lines
81 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* aw882xx_pid_2013_reg.h
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*
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* Copyright (c) 2020 AWINIC Technology CO., LTD
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*
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* Author: Nick Li <liweilei@awinic.com.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __AW882XX_PID_2013_REG_H__
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#define __AW882XX_PID_2013_REG_H__
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#define AW_PID_2013_MONITOR_FILE "aw882xx_pid_2013_monitor.bin"
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/* registers list */
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#define AW_PID_2013_ID_REG (0x00)
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#define AW_PID_2013_SYSST_REG (0x01)
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#define AW_PID_2013_SYSINT_REG (0x02)
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#define AW_PID_2013_SYSINTM_REG (0x03)
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#define AW_PID_2013_SYSCTRL_REG (0x04)
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#define AW_PID_2013_SYSCTRL2_REG (0x05)
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#define AW_PID_2013_I2SCTRL1_REG (0x06)
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#define AW_PID_2013_I2SCTRL2_REG (0x07)
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#define AW_PID_2013_DACCFG1_REG (0x08)
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#define AW_PID_2013_DACCFG2_REG (0x09)
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#define AW_PID_2013_DACCFG3_REG (0x0A)
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#define AW_PID_2013_DACCFG4_REG (0x0B)
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#define AW_PID_2013_DACCFG5_REG (0x0C)
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#define AW_PID_2013_DACCFG6_REG (0x0D)
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#define AW_PID_2013_DACCFG7_REG (0x0E)
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#define AW_PID_2013_PWMCTRL_REG (0x10)
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#define AW_PID_2013_I2SCFG1_REG (0x11)
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#define AW_PID_2013_DBGCTRL_REG (0x12)
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#define AW_PID_2013_DACST_REG (0x20)
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#define AW_PID_2013_VBAT_REG (0x21)
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#define AW_PID_2013_TEMP_REG (0x22)
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#define AW_PID_2013_PVDD_REG (0x23)
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#define AW_PID_2013_ISNDAT_REG (0x24)
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#define AW_PID_2013_VSNDAT_REG (0x25)
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#define AW_PID_2013_I2SINT_REG (0x26)
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#define AW_PID_2013_I2SCAPCNT_REG (0x27)
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#define AW_PID_2013_ANASTA1_REG (0x28)
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#define AW_PID_2013_ANASTA2_REG (0x29)
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#define AW_PID_2013_ANASTA3_REG (0x2A)
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#define AW_PID_2013_TESTDET_REG (0x2B)
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#define AW_PID_2013_TESTIN_REG (0x38)
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#define AW_PID_2013_TESTOUT_REG (0x39)
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#define AW_PID_2013_VSNTM1_REG (0x50)
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#define AW_PID_2013_VSNTM2_REG (0x51)
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#define AW_PID_2013_ISNCTRL1_REG (0x52)
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#define AW_PID_2013_PLLCTRL1_REG (0x53)
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#define AW_PID_2013_PLLCTRL2_REG (0x54)
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#define AW_PID_2013_PLLCTRL3_REG (0x55)
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#define AW_PID_2013_CDACTRL1_REG (0x56)
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#define AW_PID_2013_CDACTRL2_REG (0x57)
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#define AW_PID_2013_SADCCTRL1_REG (0x58)
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#define AW_PID_2013_BSTCTRL1_REG (0x60)
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#define AW_PID_2013_BSTCTRL2_REG (0x61)
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#define AW_PID_2013_BSTCTRL3_REG (0x62)
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#define AW_PID_2013_BSTCTRL4_REG (0x63)
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#define AW_PID_2013_BSTCTRL5_REG (0x64)
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#define AW_PID_2013_BSTCTRL6_REG (0x65)
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#define AW_PID_2013_DSMCFG1_REG (0x66)
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#define AW_PID_2013_DSMCFG2_REG (0x67)
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#define AW_PID_2013_DSMCFG3_REG (0x68)
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#define AW_PID_2013_DSMCFG4_REG (0x69)
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#define AW_PID_2013_DSMCFG5_REG (0x6A)
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#define AW_PID_2013_DSMCFG6_REG (0x6B)
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#define AW_PID_2013_DSMCFG7_REG (0x6C)
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#define AW_PID_2013_DSMCFG8_REG (0x6D)
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#define AW_PID_2013_TESTCTRL1_REG (0x70)
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#define AW_PID_2013_TESTCTRL2_REG (0x71)
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#define AW_PID_2013_EFCTRL1_REG (0x72)
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#define AW_PID_2013_EFCTRL2_REG (0x73)
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#define AW_PID_2013_EFWH_REG (0x74)
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#define AW_PID_2013_EFWM2_REG (0x75)
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#define AW_PID_2013_EFWM1_REG (0x76)
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#define AW_PID_2013_EFWL_REG (0x77)
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#define AW_PID_2013_EFRH_REG (0x78)
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#define AW_PID_2013_EFRM2_REG (0x79)
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#define AW_PID_2013_EFRM1_REG (0x7A)
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#define AW_PID_2013_EFRL_REG (0x7B)
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#define AW_PID_2013_TM_REG (0x7C)
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/********************************************
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* Register Access
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*******************************************/
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#define AW_PID_2013_REG_MAX (0x7D)
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#define AW_PID_2013_REG_NONE_ACCESS (0)
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#define AW_PID_2013_REG_RD_ACCESS (1 << 0)
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#define AW_PID_2013_REG_WR_ACCESS (1 << 1)
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const unsigned char aw_pid_2013_reg_access[AW_PID_2013_REG_MAX] = {
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[AW_PID_2013_ID_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_SYSST_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_SYSINT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_SYSINTM_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_SYSCTRL_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_SYSCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_I2SCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_I2SCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG3_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG4_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG5_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG6_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACCFG7_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_PWMCTRL_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_I2SCFG1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DBGCTRL_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DACST_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_VBAT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_TEMP_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_PVDD_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_ISNDAT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_VSNDAT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_I2SINT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_I2SCAPCNT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_ANASTA1_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_ANASTA2_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_ANASTA3_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_TESTDET_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_TESTIN_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_TESTOUT_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_VSNTM1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_VSNTM2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_ISNCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_PLLCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_PLLCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_PLLCTRL3_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_CDACTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_CDACTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_SADCCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL3_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL4_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL5_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_BSTCTRL6_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG3_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG4_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG5_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG6_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG7_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_DSMCFG8_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_TESTCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_TESTCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFCTRL1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFCTRL2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFWH_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFWM2_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFWM1_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFWL_REG] = (AW_PID_2013_REG_RD_ACCESS | AW_PID_2013_REG_WR_ACCESS),
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[AW_PID_2013_EFRH_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_EFRM2_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_EFRM1_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_EFRL_REG] = (AW_PID_2013_REG_RD_ACCESS),
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[AW_PID_2013_TM_REG] = (AW_PID_2013_REG_NONE_ACCESS),
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};
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/* detail information of registers begin */
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/* ID (0x00) detail */
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/* IDCODE bit 15:0 (ID 0x00) */
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#define AW_PID_2013_IDCODE_START_BIT (0)
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#define AW_PID_2013_IDCODE_BITS_LEN (16)
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#define AW_PID_2013_IDCODE_MASK \
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(~(((1<<AW_PID_2013_IDCODE_BITS_LEN)-1) << AW_PID_2013_IDCODE_START_BIT))
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#define AW_PID_2013_IDCODE_DEFAULT_VALUE (0x2013)
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#define AW_PID_2013_IDCODE_DEFAULT \
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(AW_PID_2013_IDCODE_DEFAULT_VALUE << AW_PID_2013_IDCODE_START_BIT)
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/* default value of ID (0x00) */
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/* #define AW_PID_2013_ID_DEFAULT (0x2013) */
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/* SYSST (0x01) detail */
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/* OVP2S bit 15 (SYSST 0x01) */
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#define AW_PID_2013_OVP2S_START_BIT (15)
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#define AW_PID_2013_OVP2S_BITS_LEN (1)
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#define AW_PID_2013_OVP2S_MASK \
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(~(((1<<AW_PID_2013_OVP2S_BITS_LEN)-1) << AW_PID_2013_OVP2S_START_BIT))
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#define AW_PID_2013_OVP2S_NORMAL (0)
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#define AW_PID_2013_OVP2S_NORMAL_VALUE \
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(AW_PID_2013_OVP2S_NORMAL << AW_PID_2013_OVP2S_START_BIT)
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#define AW_PID_2013_OVP2S_OVP (1)
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#define AW_PID_2013_OVP2S_OVP_VALUE \
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(AW_PID_2013_OVP2S_OVP << AW_PID_2013_OVP2S_START_BIT)
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#define AW_PID_2013_OVP2S_DEFAULT_VALUE (0)
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#define AW_PID_2013_OVP2S_DEFAULT \
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(AW_PID_2013_OVP2S_DEFAULT_VALUE << AW_PID_2013_OVP2S_START_BIT)
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/* UVLS bit 14 (SYSST 0x01) */
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#define AW_PID_2013_UVLS_START_BIT (14)
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#define AW_PID_2013_UVLS_BITS_LEN (1)
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#define AW_PID_2013_UVLS_MASK \
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(~(((1<<AW_PID_2013_UVLS_BITS_LEN)-1) << AW_PID_2013_UVLS_START_BIT))
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#define AW_PID_2013_UVLS_NORMAL (0)
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#define AW_PID_2013_UVLS_NORMAL_VALUE \
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(AW_PID_2013_UVLS_NORMAL << AW_PID_2013_UVLS_START_BIT)
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#define AW_PID_2013_UVLS_UVLO (1)
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#define AW_PID_2013_UVLS_UVLO_VALUE \
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(AW_PID_2013_UVLS_UVLO << AW_PID_2013_UVLS_START_BIT)
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#define AW_PID_2013_UVLS_DEFAULT_VALUE (0)
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#define AW_PID_2013_UVLS_DEFAULT \
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(AW_PID_2013_UVLS_DEFAULT_VALUE << AW_PID_2013_UVLS_START_BIT)
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/* ADPS bit 13 (SYSST 0x01) */
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#define AW_PID_2013_ADPS_START_BIT (13)
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#define AW_PID_2013_ADPS_BITS_LEN (1)
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#define AW_PID_2013_ADPS_MASK \
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(~(((1<<AW_PID_2013_ADPS_BITS_LEN)-1) << AW_PID_2013_ADPS_START_BIT))
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#define AW_PID_2013_ADPS_TRANSPARENT (0)
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#define AW_PID_2013_ADPS_TRANSPARENT_VALUE \
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(AW_PID_2013_ADPS_TRANSPARENT << AW_PID_2013_ADPS_START_BIT)
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#define AW_PID_2013_ADPS_BOOST (1)
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#define AW_PID_2013_ADPS_BOOST_VALUE \
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(AW_PID_2013_ADPS_BOOST << AW_PID_2013_ADPS_START_BIT)
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#define AW_PID_2013_ADPS_DEFAULT_VALUE (0)
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#define AW_PID_2013_ADPS_DEFAULT \
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(AW_PID_2013_ADPS_DEFAULT_VALUE << AW_PID_2013_ADPS_START_BIT)
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/* BSTOCS bit 11 (SYSST 0x01) */
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#define AW_PID_2013_BSTOCS_START_BIT (11)
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#define AW_PID_2013_BSTOCS_BITS_LEN (1)
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#define AW_PID_2013_BSTOCS_MASK \
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(~(((1<<AW_PID_2013_BSTOCS_BITS_LEN)-1) << AW_PID_2013_BSTOCS_START_BIT))
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#define AW_PID_2013_BSTOCS_NORMAL (0)
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#define AW_PID_2013_BSTOCS_NORMAL_VALUE \
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(AW_PID_2013_BSTOCS_NORMAL << AW_PID_2013_BSTOCS_START_BIT)
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#define AW_PID_2013_BSTOCS_OVER_CURRENT (1)
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#define AW_PID_2013_BSTOCS_OVER_CURRENT_VALUE \
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(AW_PID_2013_BSTOCS_OVER_CURRENT << AW_PID_2013_BSTOCS_START_BIT)
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#define AW_PID_2013_BSTOCS_DEFAULT_VALUE (0)
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#define AW_PID_2013_BSTOCS_DEFAULT \
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(AW_PID_2013_BSTOCS_DEFAULT_VALUE << AW_PID_2013_BSTOCS_START_BIT)
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/* OVPS bit 10 (SYSST 0x01) */
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#define AW_PID_2013_OVPS_START_BIT (10)
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#define AW_PID_2013_OVPS_BITS_LEN (1)
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#define AW_PID_2013_OVPS_MASK \
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(~(((1<<AW_PID_2013_OVPS_BITS_LEN)-1) << AW_PID_2013_OVPS_START_BIT))
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#define AW_PID_2013_OVPS_NORMAL (0)
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#define AW_PID_2013_OVPS_NORMAL_VALUE \
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(AW_PID_2013_OVPS_NORMAL << AW_PID_2013_OVPS_START_BIT)
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#define AW_PID_2013_OVPS_OVP (1)
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#define AW_PID_2013_OVPS_OVP_VALUE \
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(AW_PID_2013_OVPS_OVP << AW_PID_2013_OVPS_START_BIT)
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#define AW_PID_2013_OVPS_DEFAULT_VALUE (0)
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#define AW_PID_2013_OVPS_DEFAULT \
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(AW_PID_2013_OVPS_DEFAULT_VALUE << AW_PID_2013_OVPS_START_BIT)
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/* BSTS bit 9 (SYSST 0x01) */
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#define AW_PID_2013_BSTS_START_BIT (9)
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#define AW_PID_2013_BSTS_BITS_LEN (1)
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#define AW_PID_2013_BSTS_MASK \
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(~(((1<<AW_PID_2013_BSTS_BITS_LEN)-1) << AW_PID_2013_BSTS_START_BIT))
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#define AW_PID_2013_BSTS_NOT_FINISHED (0)
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#define AW_PID_2013_BSTS_NOT_FINISHED_VALUE \
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(AW_PID_2013_BSTS_NOT_FINISHED << AW_PID_2013_BSTS_START_BIT)
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#define AW_PID_2013_BSTS_FINISHED (1)
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#define AW_PID_2013_BSTS_FINISHED_VALUE \
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(AW_PID_2013_BSTS_FINISHED << AW_PID_2013_BSTS_START_BIT)
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#define AW_PID_2013_BSTS_DEFAULT_VALUE (0)
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#define AW_PID_2013_BSTS_DEFAULT \
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(AW_PID_2013_BSTS_DEFAULT_VALUE << AW_PID_2013_BSTS_START_BIT)
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/* SWS bit 8 (SYSST 0x01) */
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#define AW_PID_2013_SWS_START_BIT (8)
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#define AW_PID_2013_SWS_BITS_LEN (1)
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#define AW_PID_2013_SWS_MASK \
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(~(((1<<AW_PID_2013_SWS_BITS_LEN)-1) << AW_PID_2013_SWS_START_BIT))
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#define AW_PID_2013_SWS_NOT_SWITCHING (0)
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#define AW_PID_2013_SWS_NOT_SWITCHING_VALUE \
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(AW_PID_2013_SWS_NOT_SWITCHING << AW_PID_2013_SWS_START_BIT)
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#define AW_PID_2013_SWS_SWITCHING (1)
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#define AW_PID_2013_SWS_SWITCHING_VALUE \
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(AW_PID_2013_SWS_SWITCHING << AW_PID_2013_SWS_START_BIT)
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#define AW_PID_2013_SWS_DEFAULT_VALUE (0)
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#define AW_PID_2013_SWS_DEFAULT \
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(AW_PID_2013_SWS_DEFAULT_VALUE << AW_PID_2013_SWS_START_BIT)
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/* NOCLKS bit 5 (SYSST 0x01) */
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#define AW_PID_2013_NOCLKS_START_BIT (5)
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#define AW_PID_2013_NOCLKS_BITS_LEN (1)
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#define AW_PID_2013_NOCLKS_MASK \
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(~(((1<<AW_PID_2013_NOCLKS_BITS_LEN)-1) << AW_PID_2013_NOCLKS_START_BIT))
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#define AW_PID_2013_NOCLKS_CLOCK_OK (0)
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#define AW_PID_2013_NOCLKS_CLOCK_OK_VALUE \
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(AW_PID_2013_NOCLKS_CLOCK_OK << AW_PID_2013_NOCLKS_START_BIT)
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#define AW_PID_2013_NOCLKS_NO_CLOCK (1)
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#define AW_PID_2013_NOCLKS_NO_CLOCK_VALUE \
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(AW_PID_2013_NOCLKS_NO_CLOCK << AW_PID_2013_NOCLKS_START_BIT)
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#define AW_PID_2013_NOCLKS_DEFAULT_VALUE (0)
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#define AW_PID_2013_NOCLKS_DEFAULT \
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(AW_PID_2013_NOCLKS_DEFAULT_VALUE << AW_PID_2013_NOCLKS_START_BIT)
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/* CLKS bit 4 (SYSST 0x01) */
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#define AW_PID_2013_CLKS_START_BIT (4)
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#define AW_PID_2013_CLKS_BITS_LEN (1)
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#define AW_PID_2013_CLKS_MASK \
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(~(((1<<AW_PID_2013_CLKS_BITS_LEN)-1) << AW_PID_2013_CLKS_START_BIT))
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#define AW_PID_2013_CLKS_NOT_STABLE (0)
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#define AW_PID_2013_CLKS_NOT_STABLE_VALUE \
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(AW_PID_2013_CLKS_NOT_STABLE << AW_PID_2013_CLKS_START_BIT)
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#define AW_PID_2013_CLKS_STABLE (1)
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#define AW_PID_2013_CLKS_STABLE_VALUE \
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(AW_PID_2013_CLKS_STABLE << AW_PID_2013_CLKS_START_BIT)
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#define AW_PID_2013_CLKS_DEFAULT_VALUE (0)
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#define AW_PID_2013_CLKS_DEFAULT \
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(AW_PID_2013_CLKS_DEFAULT_VALUE << AW_PID_2013_CLKS_START_BIT)
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/* OCDS bit 3 (SYSST 0x01) */
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#define AW_PID_2013_OCDS_START_BIT (3)
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#define AW_PID_2013_OCDS_BITS_LEN (1)
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#define AW_PID_2013_OCDS_MASK \
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(~(((1<<AW_PID_2013_OCDS_BITS_LEN)-1) << AW_PID_2013_OCDS_START_BIT))
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#define AW_PID_2013_OCDS_NORAML (0)
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#define AW_PID_2013_OCDS_NORAML_VALUE \
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(AW_PID_2013_OCDS_NORAML << AW_PID_2013_OCDS_START_BIT)
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#define AW_PID_2013_OCDS_OC (1)
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#define AW_PID_2013_OCDS_OC_VALUE \
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(AW_PID_2013_OCDS_OC << AW_PID_2013_OCDS_START_BIT)
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#define AW_PID_2013_OCDS_DEFAULT_VALUE (0)
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#define AW_PID_2013_OCDS_DEFAULT \
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(AW_PID_2013_OCDS_DEFAULT_VALUE << AW_PID_2013_OCDS_START_BIT)
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/* UVL_DVDDS bit 2 (SYSST 0x01) */
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#define AW_PID_2013_UVL_DVDDS_START_BIT (2)
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#define AW_PID_2013_UVL_DVDDS_BITS_LEN (1)
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#define AW_PID_2013_UVL_DVDDS_MASK \
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(~(((1<<AW_PID_2013_UVL_DVDDS_BITS_LEN)-1) << AW_PID_2013_UVL_DVDDS_START_BIT))
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#define AW_PID_2013_UVL_DVDDS_NORMAL (0)
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#define AW_PID_2013_UVL_DVDDS_NORMAL_VALUE \
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(AW_PID_2013_UVL_DVDDS_NORMAL << AW_PID_2013_UVL_DVDDS_START_BIT)
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#define AW_PID_2013_UVL_DVDDS_UVLO (1)
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#define AW_PID_2013_UVL_DVDDS_UVLO_VALUE \
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(AW_PID_2013_UVL_DVDDS_UVLO << AW_PID_2013_UVL_DVDDS_START_BIT)
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#define AW_PID_2013_UVL_DVDDS_DEFAULT_VALUE (0)
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#define AW_PID_2013_UVL_DVDDS_DEFAULT \
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(AW_PID_2013_UVL_DVDDS_DEFAULT_VALUE << AW_PID_2013_UVL_DVDDS_START_BIT)
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/* OTHS bit 1 (SYSST 0x01) */
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#define AW_PID_2013_OTHS_START_BIT (1)
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#define AW_PID_2013_OTHS_BITS_LEN (1)
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#define AW_PID_2013_OTHS_MASK \
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(~(((1<<AW_PID_2013_OTHS_BITS_LEN)-1) << AW_PID_2013_OTHS_START_BIT))
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#define AW_PID_2013_OTHS_NORMAL (0)
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#define AW_PID_2013_OTHS_NORMAL_VALUE \
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(AW_PID_2013_OTHS_NORMAL << AW_PID_2013_OTHS_START_BIT)
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#define AW_PID_2013_OTHS_OT (1)
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#define AW_PID_2013_OTHS_OT_VALUE \
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(AW_PID_2013_OTHS_OT << AW_PID_2013_OTHS_START_BIT)
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#define AW_PID_2013_OTHS_DEFAULT_VALUE (0)
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#define AW_PID_2013_OTHS_DEFAULT \
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(AW_PID_2013_OTHS_DEFAULT_VALUE << AW_PID_2013_OTHS_START_BIT)
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/* PLLS bit 0 (SYSST 0x01) */
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#define AW_PID_2013_PLLS_START_BIT (0)
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#define AW_PID_2013_PLLS_BITS_LEN (1)
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#define AW_PID_2013_PLLS_MASK \
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(~(((1<<AW_PID_2013_PLLS_BITS_LEN)-1) << AW_PID_2013_PLLS_START_BIT))
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#define AW_PID_2013_PLLS_UNLOCKED (0)
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#define AW_PID_2013_PLLS_UNLOCKED_VALUE \
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(AW_PID_2013_PLLS_UNLOCKED << AW_PID_2013_PLLS_START_BIT)
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#define AW_PID_2013_PLLS_LOCKED (1)
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#define AW_PID_2013_PLLS_LOCKED_VALUE \
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(AW_PID_2013_PLLS_LOCKED << AW_PID_2013_PLLS_START_BIT)
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|
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#define AW_PID_2013_PLLS_DEFAULT_VALUE (0)
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#define AW_PID_2013_PLLS_DEFAULT \
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(AW_PID_2013_PLLS_DEFAULT_VALUE << AW_PID_2013_PLLS_START_BIT)
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#define AW_PID_2013_SYSST_CHECK_MASK \
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(~(AW_PID_2013_UVLS_UVLO_VALUE | \
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AW_PID_2013_BSTOCS_OVER_CURRENT_VALUE | \
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AW_PID_2013_BSTS_FINISHED_VALUE | \
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AW_PID_2013_SWS_SWITCHING_VALUE | \
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AW_PID_2013_NOCLKS_NO_CLOCK_VALUE | \
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AW_PID_2013_CLKS_STABLE_VALUE | \
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AW_PID_2013_OCDS_OC_VALUE | \
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AW_PID_2013_OTHS_OT_VALUE | \
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AW_PID_2013_PLLS_LOCKED_VALUE))
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#define AW_PID_2013_SYSST_CHECK \
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(AW_PID_2013_BSTS_FINISHED_VALUE | \
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AW_PID_2013_SWS_SWITCHING_VALUE | \
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AW_PID_2013_CLKS_STABLE_VALUE | \
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AW_PID_2013_PLLS_LOCKED_VALUE)
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|
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#define AW_PID_2013_IIS_CHECK \
|
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(AW_PID_2013_CLKS_STABLE_VALUE |\
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AW_PID_2013_PLLS_LOCKED_VALUE)
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|
|
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/* default value of SYSST (0x01) */
|
|
/* #define AW_PID_2013_SYSST_DEFAULT (0x0000) */
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|
|
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/* SYSINT (0x02) detail */
|
|
/* OVP2I bit 15 (SYSINT 0x02) */
|
|
#define AW_PID_2013_OVP2I_START_BIT (15)
|
|
#define AW_PID_2013_OVP2I_BITS_LEN (1)
|
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#define AW_PID_2013_OVP2I_MASK \
|
|
(~(((1<<AW_PID_2013_OVP2I_BITS_LEN)-1) << AW_PID_2013_OVP2I_START_BIT))
|
|
|
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#define AW_PID_2013_OVP2I_DEFAULT_VALUE (0)
|
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#define AW_PID_2013_OVP2I_DEFAULT \
|
|
(AW_PID_2013_OVP2I_DEFAULT_VALUE << AW_PID_2013_OVP2I_START_BIT)
|
|
|
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/* UVLI bit 14 (SYSINT 0x02) */
|
|
#define AW_PID_2013_UVLI_START_BIT (14)
|
|
#define AW_PID_2013_UVLI_BITS_LEN (1)
|
|
#define AW_PID_2013_UVLI_MASK \
|
|
(~(((1<<AW_PID_2013_UVLI_BITS_LEN)-1) << AW_PID_2013_UVLI_START_BIT))
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|
|
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#define AW_PID_2013_UVLI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_UVLI_DEFAULT \
|
|
(AW_PID_2013_UVLI_DEFAULT_VALUE << AW_PID_2013_UVLI_START_BIT)
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|
|
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/* ADPI bit 13 (SYSINT 0x02) */
|
|
#define AW_PID_2013_ADPI_START_BIT (13)
|
|
#define AW_PID_2013_ADPI_BITS_LEN (1)
|
|
#define AW_PID_2013_ADPI_MASK \
|
|
(~(((1<<AW_PID_2013_ADPI_BITS_LEN)-1) << AW_PID_2013_ADPI_START_BIT))
|
|
|
|
#define AW_PID_2013_ADPI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_ADPI_DEFAULT \
|
|
(AW_PID_2013_ADPI_DEFAULT_VALUE << AW_PID_2013_ADPI_START_BIT)
|
|
|
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/* BSTOCI bit 11 (SYSINT 0x02) */
|
|
#define AW_PID_2013_BSTOCI_START_BIT (11)
|
|
#define AW_PID_2013_BSTOCI_BITS_LEN (1)
|
|
#define AW_PID_2013_BSTOCI_MASK \
|
|
(~(((1<<AW_PID_2013_BSTOCI_BITS_LEN)-1) << AW_PID_2013_BSTOCI_START_BIT))
|
|
|
|
#define AW_PID_2013_BSTOCI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_BSTOCI_DEFAULT \
|
|
(AW_PID_2013_BSTOCI_DEFAULT_VALUE << AW_PID_2013_BSTOCI_START_BIT)
|
|
|
|
/* OVPI bit 10 (SYSINT 0x02) */
|
|
#define AW_PID_2013_OVPI_START_BIT (10)
|
|
#define AW_PID_2013_OVPI_BITS_LEN (1)
|
|
#define AW_PID_2013_OVPI_MASK \
|
|
(~(((1<<AW_PID_2013_OVPI_BITS_LEN)-1) << AW_PID_2013_OVPI_START_BIT))
|
|
|
|
#define AW_PID_2013_OVPI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_OVPI_DEFAULT \
|
|
(AW_PID_2013_OVPI_DEFAULT_VALUE << AW_PID_2013_OVPI_START_BIT)
|
|
|
|
/* BSTI bit 9 (SYSINT 0x02) */
|
|
#define AW_PID_2013_BSTI_START_BIT (9)
|
|
#define AW_PID_2013_BSTI_BITS_LEN (1)
|
|
#define AW_PID_2013_BSTI_MASK \
|
|
(~(((1<<AW_PID_2013_BSTI_BITS_LEN)-1) << AW_PID_2013_BSTI_START_BIT))
|
|
|
|
#define AW_PID_2013_BSTI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_BSTI_DEFAULT \
|
|
(AW_PID_2013_BSTI_DEFAULT_VALUE << AW_PID_2013_BSTI_START_BIT)
|
|
|
|
/* SWI bit 8 (SYSINT 0x02) */
|
|
#define AW_PID_2013_SWI_START_BIT (8)
|
|
#define AW_PID_2013_SWI_BITS_LEN (1)
|
|
#define AW_PID_2013_SWI_MASK \
|
|
(~(((1<<AW_PID_2013_SWI_BITS_LEN)-1) << AW_PID_2013_SWI_START_BIT))
|
|
|
|
#define AW_PID_2013_SWI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_SWI_DEFAULT \
|
|
(AW_PID_2013_SWI_DEFAULT_VALUE << AW_PID_2013_SWI_START_BIT)
|
|
|
|
/* NOCLKI bit 5 (SYSINT 0x02) */
|
|
#define AW_PID_2013_NOCLKI_START_BIT (5)
|
|
#define AW_PID_2013_NOCLKI_BITS_LEN (1)
|
|
#define AW_PID_2013_NOCLKI_MASK \
|
|
(~(((1<<AW_PID_2013_NOCLKI_BITS_LEN)-1) << AW_PID_2013_NOCLKI_START_BIT))
|
|
|
|
#define AW_PID_2013_NOCLKI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_NOCLKI_DEFAULT \
|
|
(AW_PID_2013_NOCLKI_DEFAULT_VALUE << AW_PID_2013_NOCLKI_START_BIT)
|
|
|
|
/* CLKI bit 4 (SYSINT 0x02) */
|
|
#define AW_PID_2013_CLKI_START_BIT (4)
|
|
#define AW_PID_2013_CLKI_BITS_LEN (1)
|
|
#define AW_PID_2013_CLKI_MASK \
|
|
(~(((1<<AW_PID_2013_CLKI_BITS_LEN)-1) << AW_PID_2013_CLKI_START_BIT))
|
|
|
|
#define AW_PID_2013_CLKI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_CLKI_DEFAULT \
|
|
(AW_PID_2013_CLKI_DEFAULT_VALUE << AW_PID_2013_CLKI_START_BIT)
|
|
|
|
/* OCDI bit 3 (SYSINT 0x02) */
|
|
#define AW_PID_2013_OCDI_START_BIT (3)
|
|
#define AW_PID_2013_OCDI_BITS_LEN (1)
|
|
#define AW_PID_2013_OCDI_MASK \
|
|
(~(((1<<AW_PID_2013_OCDI_BITS_LEN)-1) << AW_PID_2013_OCDI_START_BIT))
|
|
|
|
#define AW_PID_2013_OCDI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_OCDI_DEFAULT \
|
|
(AW_PID_2013_OCDI_DEFAULT_VALUE << AW_PID_2013_OCDI_START_BIT)
|
|
|
|
/* UVL_DVDDI bit 2 (SYSINT 0x02) */
|
|
#define AW_PID_2013_UVL_DVDDI_START_BIT (2)
|
|
#define AW_PID_2013_UVL_DVDDI_BITS_LEN (1)
|
|
#define AW_PID_2013_UVL_DVDDI_MASK \
|
|
(~(((1<<AW_PID_2013_UVL_DVDDI_BITS_LEN)-1) << AW_PID_2013_UVL_DVDDI_START_BIT))
|
|
|
|
#define AW_PID_2013_UVL_DVDDI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_UVL_DVDDI_DEFAULT \
|
|
(AW_PID_2013_UVL_DVDDI_DEFAULT_VALUE << AW_PID_2013_UVL_DVDDI_START_BIT)
|
|
|
|
/* OTHI bit 1 (SYSINT 0x02) */
|
|
#define AW_PID_2013_OTHI_START_BIT (1)
|
|
#define AW_PID_2013_OTHI_BITS_LEN (1)
|
|
#define AW_PID_2013_OTHI_MASK \
|
|
(~(((1<<AW_PID_2013_OTHI_BITS_LEN)-1) << AW_PID_2013_OTHI_START_BIT))
|
|
|
|
#define AW_PID_2013_OTHI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_OTHI_DEFAULT \
|
|
(AW_PID_2013_OTHI_DEFAULT_VALUE << AW_PID_2013_OTHI_START_BIT)
|
|
|
|
/* PLLI bit 0 (SYSINT 0x02) */
|
|
#define AW_PID_2013_PLLI_START_BIT (0)
|
|
#define AW_PID_2013_PLLI_BITS_LEN (1)
|
|
#define AW_PID_2013_PLLI_MASK \
|
|
(~(((1<<AW_PID_2013_PLLI_BITS_LEN)-1) << AW_PID_2013_PLLI_START_BIT))
|
|
|
|
#define AW_PID_2013_PLLI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_PLLI_DEFAULT \
|
|
(AW_PID_2013_PLLI_DEFAULT_VALUE << AW_PID_2013_PLLI_START_BIT)
|
|
|
|
/* default value of SYSINT (0x02) */
|
|
/* #define AW_PID_2013_SYSINT_DEFAULT (0x0000) */
|
|
|
|
/* SYSINTM (0x03) detail */
|
|
/* OVP2M bit 15 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_OVP2M_START_BIT (15)
|
|
#define AW_PID_2013_OVP2M_BITS_LEN (1)
|
|
#define AW_PID_2013_OVP2M_MASK \
|
|
(~(((1<<AW_PID_2013_OVP2M_BITS_LEN)-1) << AW_PID_2013_OVP2M_START_BIT))
|
|
|
|
#define AW_PID_2013_OVP2M_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_OVP2M_DEFAULT \
|
|
(AW_PID_2013_OVP2M_DEFAULT_VALUE << AW_PID_2013_OVP2M_START_BIT)
|
|
|
|
/* UVLM bit 14 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_UVLM_START_BIT (14)
|
|
#define AW_PID_2013_UVLM_BITS_LEN (1)
|
|
#define AW_PID_2013_UVLM_MASK \
|
|
(~(((1<<AW_PID_2013_UVLM_BITS_LEN)-1) << AW_PID_2013_UVLM_START_BIT))
|
|
|
|
#define AW_PID_2013_UVLM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_UVLM_DEFAULT \
|
|
(AW_PID_2013_UVLM_DEFAULT_VALUE << AW_PID_2013_UVLM_START_BIT)
|
|
|
|
/* ADPM bit 13 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_ADPM_START_BIT (13)
|
|
#define AW_PID_2013_ADPM_BITS_LEN (1)
|
|
#define AW_PID_2013_ADPM_MASK \
|
|
(~(((1<<AW_PID_2013_ADPM_BITS_LEN)-1) << AW_PID_2013_ADPM_START_BIT))
|
|
|
|
#define AW_PID_2013_ADPM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_ADPM_DEFAULT \
|
|
(AW_PID_2013_ADPM_DEFAULT_VALUE << AW_PID_2013_ADPM_START_BIT)
|
|
|
|
/* DSPM bit 12 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_DSPM_START_BIT (12)
|
|
#define AW_PID_2013_DSPM_BITS_LEN (1)
|
|
#define AW_PID_2013_DSPM_MASK \
|
|
(~(((1<<AW_PID_2013_DSPM_BITS_LEN)-1) << AW_PID_2013_DSPM_START_BIT))
|
|
|
|
#define AW_PID_2013_DSPM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_DSPM_DEFAULT \
|
|
(AW_PID_2013_DSPM_DEFAULT_VALUE << AW_PID_2013_DSPM_START_BIT)
|
|
|
|
/* BSTOCM bit 11 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_BSTOCM_START_BIT (11)
|
|
#define AW_PID_2013_BSTOCM_BITS_LEN (1)
|
|
#define AW_PID_2013_BSTOCM_MASK \
|
|
(~(((1<<AW_PID_2013_BSTOCM_BITS_LEN)-1) << AW_PID_2013_BSTOCM_START_BIT))
|
|
|
|
#define AW_PID_2013_BSTOCM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_BSTOCM_DEFAULT \
|
|
(AW_PID_2013_BSTOCM_DEFAULT_VALUE << AW_PID_2013_BSTOCM_START_BIT)
|
|
|
|
/* OVPM bit 10 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_OVPM_START_BIT (10)
|
|
#define AW_PID_2013_OVPM_BITS_LEN (1)
|
|
#define AW_PID_2013_OVPM_MASK \
|
|
(~(((1<<AW_PID_2013_OVPM_BITS_LEN)-1) << AW_PID_2013_OVPM_START_BIT))
|
|
|
|
#define AW_PID_2013_OVPM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_OVPM_DEFAULT \
|
|
(AW_PID_2013_OVPM_DEFAULT_VALUE << AW_PID_2013_OVPM_START_BIT)
|
|
|
|
/* BSTM bit 9 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_BSTM_START_BIT (9)
|
|
#define AW_PID_2013_BSTM_BITS_LEN (1)
|
|
#define AW_PID_2013_BSTM_MASK \
|
|
(~(((1<<AW_PID_2013_BSTM_BITS_LEN)-1) << AW_PID_2013_BSTM_START_BIT))
|
|
|
|
#define AW_PID_2013_BSTM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_BSTM_DEFAULT \
|
|
(AW_PID_2013_BSTM_DEFAULT_VALUE << AW_PID_2013_BSTM_START_BIT)
|
|
|
|
/* SWM bit 8 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_SWM_START_BIT (8)
|
|
#define AW_PID_2013_SWM_BITS_LEN (1)
|
|
#define AW_PID_2013_SWM_MASK \
|
|
(~(((1<<AW_PID_2013_SWM_BITS_LEN)-1) << AW_PID_2013_SWM_START_BIT))
|
|
|
|
#define AW_PID_2013_SWM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_SWM_DEFAULT \
|
|
(AW_PID_2013_SWM_DEFAULT_VALUE << AW_PID_2013_SWM_START_BIT)
|
|
|
|
/* CLIPM bit 7 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_CLIPM_START_BIT (7)
|
|
#define AW_PID_2013_CLIPM_BITS_LEN (1)
|
|
#define AW_PID_2013_CLIPM_MASK \
|
|
(~(((1<<AW_PID_2013_CLIPM_BITS_LEN)-1) << AW_PID_2013_CLIPM_START_BIT))
|
|
|
|
#define AW_PID_2013_CLIPM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_CLIPM_DEFAULT \
|
|
(AW_PID_2013_CLIPM_DEFAULT_VALUE << AW_PID_2013_CLIPM_START_BIT)
|
|
|
|
/* WDM bit 6 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_WDM_START_BIT (6)
|
|
#define AW_PID_2013_WDM_BITS_LEN (1)
|
|
#define AW_PID_2013_WDM_MASK \
|
|
(~(((1<<AW_PID_2013_WDM_BITS_LEN)-1) << AW_PID_2013_WDM_START_BIT))
|
|
|
|
#define AW_PID_2013_WDM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_WDM_DEFAULT \
|
|
(AW_PID_2013_WDM_DEFAULT_VALUE << AW_PID_2013_WDM_START_BIT)
|
|
|
|
/* NOCLKM bit 5 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_NOCLKM_START_BIT (5)
|
|
#define AW_PID_2013_NOCLKM_BITS_LEN (1)
|
|
#define AW_PID_2013_NOCLKM_MASK \
|
|
(~(((1<<AW_PID_2013_NOCLKM_BITS_LEN)-1) << AW_PID_2013_NOCLKM_START_BIT))
|
|
|
|
#define AW_PID_2013_NOCLKM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_NOCLKM_DEFAULT \
|
|
(AW_PID_2013_NOCLKM_DEFAULT_VALUE << AW_PID_2013_NOCLKM_START_BIT)
|
|
|
|
/* CLKM bit 4 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_CLKM_START_BIT (4)
|
|
#define AW_PID_2013_CLKM_BITS_LEN (1)
|
|
#define AW_PID_2013_CLKM_MASK \
|
|
(~(((1<<AW_PID_2013_CLKM_BITS_LEN)-1) << AW_PID_2013_CLKM_START_BIT))
|
|
|
|
#define AW_PID_2013_CLKM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_CLKM_DEFAULT \
|
|
(AW_PID_2013_CLKM_DEFAULT_VALUE << AW_PID_2013_CLKM_START_BIT)
|
|
|
|
/* OCDM bit 3 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_OCDM_START_BIT (3)
|
|
#define AW_PID_2013_OCDM_BITS_LEN (1)
|
|
#define AW_PID_2013_OCDM_MASK \
|
|
(~(((1<<AW_PID_2013_OCDM_BITS_LEN)-1) << AW_PID_2013_OCDM_START_BIT))
|
|
|
|
#define AW_PID_2013_OCDM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_OCDM_DEFAULT \
|
|
(AW_PID_2013_OCDM_DEFAULT_VALUE << AW_PID_2013_OCDM_START_BIT)
|
|
|
|
/* UVL_DVDDM bit 2 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_UVL_DVDDM_START_BIT (2)
|
|
#define AW_PID_2013_UVL_DVDDM_BITS_LEN (1)
|
|
#define AW_PID_2013_UVL_DVDDM_MASK \
|
|
(~(((1<<AW_PID_2013_UVL_DVDDM_BITS_LEN)-1) << AW_PID_2013_UVL_DVDDM_START_BIT))
|
|
|
|
#define AW_PID_2013_UVL_DVDDM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_UVL_DVDDM_DEFAULT \
|
|
(AW_PID_2013_UVL_DVDDM_DEFAULT_VALUE << AW_PID_2013_UVL_DVDDM_START_BIT)
|
|
|
|
/* OTHM bit 1 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_OTHM_START_BIT (1)
|
|
#define AW_PID_2013_OTHM_BITS_LEN (1)
|
|
#define AW_PID_2013_OTHM_MASK \
|
|
(~(((1<<AW_PID_2013_OTHM_BITS_LEN)-1) << AW_PID_2013_OTHM_START_BIT))
|
|
|
|
#define AW_PID_2013_OTHM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_OTHM_DEFAULT \
|
|
(AW_PID_2013_OTHM_DEFAULT_VALUE << AW_PID_2013_OTHM_START_BIT)
|
|
|
|
/* PLLM bit 0 (SYSINTM 0x03) */
|
|
#define AW_PID_2013_PLLM_START_BIT (0)
|
|
#define AW_PID_2013_PLLM_BITS_LEN (1)
|
|
#define AW_PID_2013_PLLM_MASK \
|
|
(~(((1<<AW_PID_2013_PLLM_BITS_LEN)-1) << AW_PID_2013_PLLM_START_BIT))
|
|
|
|
#define AW_PID_2013_PLLM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_PLLM_DEFAULT \
|
|
(AW_PID_2013_PLLM_DEFAULT_VALUE << AW_PID_2013_PLLM_START_BIT)
|
|
|
|
/* default value of SYSINTM (0x03) */
|
|
#define AW_PID_2013_SYSINTM_DEFAULT (0xFFFF)
|
|
|
|
/* SYSCTRL (0x04) detail */
|
|
/* DRVSTREN bit 15 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_DRVSTREN_START_BIT (15)
|
|
#define AW_PID_2013_DRVSTREN_BITS_LEN (1)
|
|
#define AW_PID_2013_DRVSTREN_MASK \
|
|
(~(((1<<AW_PID_2013_DRVSTREN_BITS_LEN)-1) << AW_PID_2013_DRVSTREN_START_BIT))
|
|
|
|
#define AW_PID_2013_DRVSTREN_4MA (0)
|
|
#define AW_PID_2013_DRVSTREN_4MA_VALUE \
|
|
(AW_PID_2013_DRVSTREN_4MA << AW_PID_2013_DRVSTREN_START_BIT)
|
|
|
|
#define AW_PID_2013_DRVSTREN_12MA (1)
|
|
#define AW_PID_2013_DRVSTREN_12MA_VALUE \
|
|
(AW_PID_2013_DRVSTREN_12MA << AW_PID_2013_DRVSTREN_START_BIT)
|
|
|
|
#define AW_PID_2013_DRVSTREN_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_DRVSTREN_DEFAULT \
|
|
(AW_PID_2013_DRVSTREN_DEFAULT_VALUE << AW_PID_2013_DRVSTREN_START_BIT)
|
|
|
|
/* SET_GAIN bit 14:12 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_SET_GAIN_START_BIT (12)
|
|
#define AW_PID_2013_SET_GAIN_BITS_LEN (3)
|
|
#define AW_PID_2013_SET_GAIN_MASK \
|
|
(~(((1<<AW_PID_2013_SET_GAIN_BITS_LEN)-1) << AW_PID_2013_SET_GAIN_START_BIT))
|
|
|
|
#define AW_PID_2013_SET_GAIN_4P5_AV (0)
|
|
#define AW_PID_2013_SET_GAIN_4P5_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_4P5_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_5P0_AV (1)
|
|
#define AW_PID_2013_SET_GAIN_5P0_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_5P0_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_6P0_AV (2)
|
|
#define AW_PID_2013_SET_GAIN_6P0_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_6P0_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_6P7_AV (3)
|
|
#define AW_PID_2013_SET_GAIN_6P7_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_6P7_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_10_AV (4)
|
|
#define AW_PID_2013_SET_GAIN_10_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_10_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_12_AV (5)
|
|
#define AW_PID_2013_SET_GAIN_12_AV_VALUE \
|
|
(AW_PID_2013_SET_GAIN_12_AV << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2013_SET_GAIN_DEFAULT_VALUE (0x5)
|
|
#define AW_PID_2013_SET_GAIN_DEFAULT \
|
|
(AW_PID_2013_SET_GAIN_DEFAULT_VALUE << AW_PID_2013_SET_GAIN_START_BIT)
|
|
|
|
/* RMSE bit 11 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_RMSE_START_BIT (11)
|
|
#define AW_PID_2013_RMSE_BITS_LEN (1)
|
|
#define AW_PID_2013_RMSE_MASK \
|
|
(~(((1<<AW_PID_2013_RMSE_BITS_LEN)-1) << AW_PID_2013_RMSE_START_BIT))
|
|
|
|
#define AW_PID_2013_RMSE_PEAK_AGC (0)
|
|
#define AW_PID_2013_RMSE_PEAK_AGC_VALUE \
|
|
(AW_PID_2013_RMSE_PEAK_AGC << AW_PID_2013_RMSE_START_BIT)
|
|
|
|
#define AW_PID_2013_RMSE_RMS_AGC (1)
|
|
#define AW_PID_2013_RMSE_RMS_AGC_VALUE \
|
|
(AW_PID_2013_RMSE_RMS_AGC << AW_PID_2013_RMSE_START_BIT)
|
|
|
|
#define AW_PID_2013_RMSE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_RMSE_DEFAULT \
|
|
(AW_PID_2013_RMSE_DEFAULT_VALUE << AW_PID_2013_RMSE_START_BIT)
|
|
|
|
/* HAGCE bit 10 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_HAGCE_START_BIT (10)
|
|
#define AW_PID_2013_HAGCE_BITS_LEN (1)
|
|
#define AW_PID_2013_HAGCE_MASK \
|
|
(~(((1<<AW_PID_2013_HAGCE_BITS_LEN)-1) << AW_PID_2013_HAGCE_START_BIT))
|
|
|
|
#define AW_PID_2013_HAGCE_DISABLE (0)
|
|
#define AW_PID_2013_HAGCE_DISABLE_VALUE \
|
|
(AW_PID_2013_HAGCE_DISABLE << AW_PID_2013_HAGCE_START_BIT)
|
|
|
|
#define AW_PID_2013_HAGCE_ENABLE (1)
|
|
#define AW_PID_2013_HAGCE_ENABLE_VALUE \
|
|
(AW_PID_2013_HAGCE_ENABLE << AW_PID_2013_HAGCE_START_BIT)
|
|
|
|
#define AW_PID_2013_HAGCE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_HAGCE_DEFAULT \
|
|
(AW_PID_2013_HAGCE_DEFAULT_VALUE << AW_PID_2013_HAGCE_START_BIT)
|
|
|
|
/* HDCCE bit 9 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_HDCCE_START_BIT (9)
|
|
#define AW_PID_2013_HDCCE_BITS_LEN (1)
|
|
#define AW_PID_2013_HDCCE_MASK \
|
|
(~(((1<<AW_PID_2013_HDCCE_BITS_LEN)-1) << AW_PID_2013_HDCCE_START_BIT))
|
|
|
|
#define AW_PID_2013_HDCCE_DISABLE (0)
|
|
#define AW_PID_2013_HDCCE_DISABLE_VALUE \
|
|
(AW_PID_2013_HDCCE_DISABLE << AW_PID_2013_HDCCE_START_BIT)
|
|
|
|
#define AW_PID_2013_HDCCE_ENABLE (1)
|
|
#define AW_PID_2013_HDCCE_ENABLE_VALUE \
|
|
(AW_PID_2013_HDCCE_ENABLE << AW_PID_2013_HDCCE_START_BIT)
|
|
|
|
#define AW_PID_2013_HDCCE_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_HDCCE_DEFAULT \
|
|
(AW_PID_2013_HDCCE_DEFAULT_VALUE << AW_PID_2013_HDCCE_START_BIT)
|
|
|
|
/* HMUTE bit 8 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_HMUTE_START_BIT (8)
|
|
#define AW_PID_2013_HMUTE_BITS_LEN (1)
|
|
#define AW_PID_2013_HMUTE_MASK \
|
|
(~(((1<<AW_PID_2013_HMUTE_BITS_LEN)-1) << AW_PID_2013_HMUTE_START_BIT))
|
|
|
|
#define AW_PID_2013_HMUTE_DISABLE (0)
|
|
#define AW_PID_2013_HMUTE_DISABLE_VALUE \
|
|
(AW_PID_2013_HMUTE_DISABLE << AW_PID_2013_HMUTE_START_BIT)
|
|
|
|
#define AW_PID_2013_HMUTE_ENABLE (1)
|
|
#define AW_PID_2013_HMUTE_ENABLE_VALUE \
|
|
(AW_PID_2013_HMUTE_ENABLE << AW_PID_2013_HMUTE_START_BIT)
|
|
|
|
#define AW_PID_2013_HMUTE_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_HMUTE_DEFAULT \
|
|
(AW_PID_2013_HMUTE_DEFAULT_VALUE << AW_PID_2013_HMUTE_START_BIT)
|
|
|
|
/* EN_TRAN bit 7 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_EN_TRAN_START_BIT (7)
|
|
#define AW_PID_2013_EN_TRAN_BITS_LEN (1)
|
|
#define AW_PID_2013_EN_TRAN_MASK \
|
|
(~(((1<<AW_PID_2013_EN_TRAN_BITS_LEN)-1) << AW_PID_2013_EN_TRAN_START_BIT))
|
|
|
|
#define AW_PID_2013_EN_TRAN_SPK (0)
|
|
#define AW_PID_2013_EN_TRAN_SPK_VALUE \
|
|
(AW_PID_2013_EN_TRAN_SPK << AW_PID_2013_EN_TRAN_START_BIT)
|
|
|
|
#define AW_PID_2013_EN_TRAN_RCV (1)
|
|
#define AW_PID_2013_EN_TRAN_RCV_VALUE \
|
|
(AW_PID_2013_EN_TRAN_RCV << AW_PID_2013_EN_TRAN_START_BIT)
|
|
|
|
#define AW_PID_2013_EN_TRAN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_EN_TRAN_DEFAULT \
|
|
(AW_PID_2013_EN_TRAN_DEFAULT_VALUE << AW_PID_2013_EN_TRAN_START_BIT)
|
|
|
|
/* I2SEN bit 6 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_I2SEN_START_BIT (6)
|
|
#define AW_PID_2013_I2SEN_BITS_LEN (1)
|
|
#define AW_PID_2013_I2SEN_MASK \
|
|
(~(((1<<AW_PID_2013_I2SEN_BITS_LEN)-1) << AW_PID_2013_I2SEN_START_BIT))
|
|
|
|
#define AW_PID_2013_I2SEN_DISABLE (0)
|
|
#define AW_PID_2013_I2SEN_DISABLE_VALUE \
|
|
(AW_PID_2013_I2SEN_DISABLE << AW_PID_2013_I2SEN_START_BIT)
|
|
|
|
#define AW_PID_2013_I2SEN_ENABLE (1)
|
|
#define AW_PID_2013_I2SEN_ENABLE_VALUE \
|
|
(AW_PID_2013_I2SEN_ENABLE << AW_PID_2013_I2SEN_START_BIT)
|
|
|
|
#define AW_PID_2013_I2SEN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_I2SEN_DEFAULT \
|
|
(AW_PID_2013_I2SEN_DEFAULT_VALUE << AW_PID_2013_I2SEN_START_BIT)
|
|
|
|
/* WSINV bit 5 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_WSINV_START_BIT (5)
|
|
#define AW_PID_2013_WSINV_BITS_LEN (1)
|
|
#define AW_PID_2013_WSINV_MASK \
|
|
(~(((1<<AW_PID_2013_WSINV_BITS_LEN)-1) << AW_PID_2013_WSINV_START_BIT))
|
|
|
|
#define AW_PID_2013_WSINV_NOT_SWITCH (0)
|
|
#define AW_PID_2013_WSINV_NOT_SWITCH_VALUE \
|
|
(AW_PID_2013_WSINV_NOT_SWITCH << AW_PID_2013_WSINV_START_BIT)
|
|
|
|
#define AW_PID_2013_WSINV_SWITCH (1)
|
|
#define AW_PID_2013_WSINV_SWITCH_VALUE \
|
|
(AW_PID_2013_WSINV_SWITCH << AW_PID_2013_WSINV_START_BIT)
|
|
|
|
#define AW_PID_2013_WSINV_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_WSINV_DEFAULT \
|
|
(AW_PID_2013_WSINV_DEFAULT_VALUE << AW_PID_2013_WSINV_START_BIT)
|
|
|
|
/* BCKINV bit 4 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_BCKINV_START_BIT (4)
|
|
#define AW_PID_2013_BCKINV_BITS_LEN (1)
|
|
#define AW_PID_2013_BCKINV_MASK \
|
|
(~(((1<<AW_PID_2013_BCKINV_BITS_LEN)-1) << AW_PID_2013_BCKINV_START_BIT))
|
|
|
|
#define AW_PID_2013_BCKINV_NOT_INVERT (0)
|
|
#define AW_PID_2013_BCKINV_NOT_INVERT_VALUE \
|
|
(AW_PID_2013_BCKINV_NOT_INVERT << AW_PID_2013_BCKINV_START_BIT)
|
|
|
|
#define AW_PID_2013_BCKINV_INVERTED (1)
|
|
#define AW_PID_2013_BCKINV_INVERTED_VALUE \
|
|
(AW_PID_2013_BCKINV_INVERTED << AW_PID_2013_BCKINV_START_BIT)
|
|
|
|
#define AW_PID_2013_BCKINV_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_BCKINV_DEFAULT \
|
|
(AW_PID_2013_BCKINV_DEFAULT_VALUE << AW_PID_2013_BCKINV_START_BIT)
|
|
|
|
/* IPLL bit 3 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_IPLL_START_BIT (3)
|
|
#define AW_PID_2013_IPLL_BITS_LEN (1)
|
|
#define AW_PID_2013_IPLL_MASK \
|
|
(~(((1<<AW_PID_2013_IPLL_BITS_LEN)-1) << AW_PID_2013_IPLL_START_BIT))
|
|
|
|
#define AW_PID_2013_IPLL_BCK (0)
|
|
#define AW_PID_2013_IPLL_BCK_VALUE \
|
|
(AW_PID_2013_IPLL_BCK << AW_PID_2013_IPLL_START_BIT)
|
|
|
|
#define AW_PID_2013_IPLL_WCK (1)
|
|
#define AW_PID_2013_IPLL_WCK_VALUE \
|
|
(AW_PID_2013_IPLL_WCK << AW_PID_2013_IPLL_START_BIT)
|
|
|
|
#define AW_PID_2013_IPLL_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_IPLL_DEFAULT \
|
|
(AW_PID_2013_IPLL_DEFAULT_VALUE << AW_PID_2013_IPLL_START_BIT)
|
|
|
|
/* AMPPD bit 1 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_AMPPD_START_BIT (1)
|
|
#define AW_PID_2013_AMPPD_BITS_LEN (1)
|
|
#define AW_PID_2013_AMPPD_MASK \
|
|
(~(((1<<AW_PID_2013_AMPPD_BITS_LEN)-1) << AW_PID_2013_AMPPD_START_BIT))
|
|
|
|
#define AW_PID_2013_AMPPD_WORKING (0)
|
|
#define AW_PID_2013_AMPPD_WORKING_VALUE \
|
|
(AW_PID_2013_AMPPD_WORKING << AW_PID_2013_AMPPD_START_BIT)
|
|
|
|
#define AW_PID_2013_AMPPD_POWER_DOWN (1)
|
|
#define AW_PID_2013_AMPPD_POWER_DOWN_VALUE \
|
|
(AW_PID_2013_AMPPD_POWER_DOWN << AW_PID_2013_AMPPD_START_BIT)
|
|
|
|
#define AW_PID_2013_AMPPD_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_AMPPD_DEFAULT \
|
|
(AW_PID_2013_AMPPD_DEFAULT_VALUE << AW_PID_2013_AMPPD_START_BIT)
|
|
|
|
/* PWDN bit 0 (SYSCTRL 0x04) */
|
|
#define AW_PID_2013_PWDN_START_BIT (0)
|
|
#define AW_PID_2013_PWDN_BITS_LEN (1)
|
|
#define AW_PID_2013_PWDN_MASK \
|
|
(~(((1<<AW_PID_2013_PWDN_BITS_LEN)-1) << AW_PID_2013_PWDN_START_BIT))
|
|
|
|
#define AW_PID_2013_PWDN_WORKING (0)
|
|
#define AW_PID_2013_PWDN_WORKING_VALUE \
|
|
(AW_PID_2013_PWDN_WORKING << AW_PID_2013_PWDN_START_BIT)
|
|
|
|
#define AW_PID_2013_PWDN_POWER_DOWN (1)
|
|
#define AW_PID_2013_PWDN_POWER_DOWN_VALUE \
|
|
(AW_PID_2013_PWDN_POWER_DOWN << AW_PID_2013_PWDN_START_BIT)
|
|
|
|
#define AW_PID_2013_PWDN_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_PWDN_DEFAULT \
|
|
(AW_PID_2013_PWDN_DEFAULT_VALUE << AW_PID_2013_PWDN_START_BIT)
|
|
|
|
/* default value of SYSCTRL (0x04) */
|
|
/* #define AW_PID_2013_SYSCTRL_DEFAULT (0xD303) */
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/* SYSCTRL2 (0x05) detail */
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/* IV2CH bit 15 (SYSCTRL2 0x05) */
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#define AW_PID_2013_IV2CH_START_BIT (15)
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#define AW_PID_2013_IV2CH_BITS_LEN (1)
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#define AW_PID_2013_IV2CH_MASK \
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(~(((1<<AW_PID_2013_IV2CH_BITS_LEN)-1) << AW_PID_2013_IV2CH_START_BIT))
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#define AW_PID_2013_IV2CH_LEGACY (0)
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#define AW_PID_2013_IV2CH_LEGACY_VALUE \
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(AW_PID_2013_IV2CH_LEGACY << AW_PID_2013_IV2CH_START_BIT)
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#define AW_PID_2013_IV2CH_SPECIAL (1)
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#define AW_PID_2013_IV2CH_SPECIAL_VALUE \
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(AW_PID_2013_IV2CH_SPECIAL << AW_PID_2013_IV2CH_START_BIT)
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#define AW_PID_2013_IV2CH_DEFAULT_VALUE (0)
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#define AW_PID_2013_IV2CH_DEFAULT \
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(AW_PID_2013_IV2CH_DEFAULT_VALUE << AW_PID_2013_IV2CH_START_BIT)
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/* I2SDOSEL bit 14 (SYSCTRL2 0x05) */
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#define AW_PID_2013_I2SDOSEL_START_BIT (14)
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#define AW_PID_2013_I2SDOSEL_BITS_LEN (1)
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#define AW_PID_2013_I2SDOSEL_MASK \
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(~(((1<<AW_PID_2013_I2SDOSEL_BITS_LEN)-1) << AW_PID_2013_I2SDOSEL_START_BIT))
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#define AW_PID_2013_I2SDOSEL_ZEROS (0)
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#define AW_PID_2013_I2SDOSEL_ZEROS_VALUE \
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(AW_PID_2013_I2SDOSEL_ZEROS << AW_PID_2013_I2SDOSEL_START_BIT)
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#define AW_PID_2013_I2SDOSEL_TXDATA (1)
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#define AW_PID_2013_I2SDOSEL_TXDATA_VALUE \
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(AW_PID_2013_I2SDOSEL_TXDATA << AW_PID_2013_I2SDOSEL_START_BIT)
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#define AW_PID_2013_I2SDOSEL_DEFAULT_VALUE (1)
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#define AW_PID_2013_I2SDOSEL_DEFAULT \
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(AW_PID_2013_I2SDOSEL_DEFAULT_VALUE << AW_PID_2013_I2SDOSEL_START_BIT)
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/* DOHZ bit 13 (SYSCTRL2 0x05) */
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#define AW_PID_2013_DOHZ_START_BIT (13)
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#define AW_PID_2013_DOHZ_BITS_LEN (1)
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#define AW_PID_2013_DOHZ_MASK \
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(~(((1<<AW_PID_2013_DOHZ_BITS_LEN)-1) << AW_PID_2013_DOHZ_START_BIT))
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#define AW_PID_2013_DOHZ_ALL (0)
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#define AW_PID_2013_DOHZ_ALL_VALUE \
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(AW_PID_2013_DOHZ_ALL << AW_PID_2013_DOHZ_START_BIT)
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#define AW_PID_2013_DOHZ_HIZ (1)
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#define AW_PID_2013_DOHZ_HIZ_VALUE \
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(AW_PID_2013_DOHZ_HIZ << AW_PID_2013_DOHZ_START_BIT)
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#define AW_PID_2013_DOHZ_DEFAULT_VALUE (1)
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#define AW_PID_2013_DOHZ_DEFAULT \
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(AW_PID_2013_DOHZ_DEFAULT_VALUE << AW_PID_2013_DOHZ_START_BIT)
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/* I2SCHS bit 12 (SYSCTRL2 0x05) */
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#define AW_PID_2013_I2SCHS_START_BIT (12)
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#define AW_PID_2013_I2SCHS_BITS_LEN (1)
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#define AW_PID_2013_I2SCHS_MASK \
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(~(((1<<AW_PID_2013_I2SCHS_BITS_LEN)-1) << AW_PID_2013_I2SCHS_START_BIT))
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#define AW_PID_2013_I2SCHS_LEFT (0)
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#define AW_PID_2013_I2SCHS_LEFT_VALUE \
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(AW_PID_2013_I2SCHS_LEFT << AW_PID_2013_I2SCHS_START_BIT)
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#define AW_PID_2013_I2SCHS_RIGHT (1)
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#define AW_PID_2013_I2SCHS_RIGHT_VALUE \
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(AW_PID_2013_I2SCHS_RIGHT << AW_PID_2013_I2SCHS_START_BIT)
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#define AW_PID_2013_I2SCHS_DEFAULT_VALUE (0)
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#define AW_PID_2013_I2SCHS_DEFAULT \
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(AW_PID_2013_I2SCHS_DEFAULT_VALUE << AW_PID_2013_I2SCHS_START_BIT)
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/* INTMODE bit 11 (SYSCTRL2 0x05) */
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#define AW_PID_2013_INTMODE_START_BIT (11)
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#define AW_PID_2013_INTMODE_BITS_LEN (1)
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#define AW_PID_2013_INTMODE_MASK \
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(~(((1<<AW_PID_2013_INTMODE_BITS_LEN)-1) << AW_PID_2013_INTMODE_START_BIT))
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#define AW_PID_2013_INTMODE_OPENMINUS_DRAIN (0)
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#define AW_PID_2013_INTMODE_OPENMINUS_DRAIN_VALUE \
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(AW_PID_2013_INTMODE_OPENMINUS_DRAIN << AW_PID_2013_INTMODE_START_BIT)
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#define AW_PID_2013_INTMODE_PUSHPULL (1)
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#define AW_PID_2013_INTMODE_PUSHPULL_VALUE \
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(AW_PID_2013_INTMODE_PUSHPULL << AW_PID_2013_INTMODE_START_BIT)
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#define AW_PID_2013_INTMODE_DEFAULT_VALUE (0)
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#define AW_PID_2013_INTMODE_DEFAULT \
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(AW_PID_2013_INTMODE_DEFAULT_VALUE << AW_PID_2013_INTMODE_START_BIT)
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/* INTN bit 10 (SYSCTRL2 0x05) */
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#define AW_PID_2013_INTN_START_BIT (10)
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#define AW_PID_2013_INTN_BITS_LEN (1)
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#define AW_PID_2013_INTN_MASK \
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(~(((1<<AW_PID_2013_INTN_BITS_LEN)-1) << AW_PID_2013_INTN_START_BIT))
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#define AW_PID_2013_INTN_SYSINT (0)
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#define AW_PID_2013_INTN_SYSINT_VALUE \
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(AW_PID_2013_INTN_SYSINT << AW_PID_2013_INTN_START_BIT)
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#define AW_PID_2013_INTN_SYSST (1)
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#define AW_PID_2013_INTN_SYSST_VALUE \
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(AW_PID_2013_INTN_SYSST << AW_PID_2013_INTN_START_BIT)
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#define AW_PID_2013_INTN_DEFAULT_VALUE (0)
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#define AW_PID_2013_INTN_DEFAULT \
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(AW_PID_2013_INTN_DEFAULT_VALUE << AW_PID_2013_INTN_START_BIT)
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/* VOL bit 9:0 (SYSCTRL2 0x05) */
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#define AW_PID_2013_VOL_START_BIT (0)
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#define AW_PID_2013_VOL_BITS_LEN (10)
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#define AW_PID_2013_VOL_MASK \
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(~(((1<<AW_PID_2013_VOL_BITS_LEN)-1) << AW_PID_2013_VOL_START_BIT))
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#define AW_PID_2013_MUTE_VOL (90 * 8)
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#define AW_PID_2013_VOL_STEP_DB (6 * 8)
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#define AW_PID_2013_VOL_DEFAULT_VALUE (0)
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#define AW_PID_2013_VOL_DEFAULT \
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(AW_PID_2013_VOL_DEFAULT_VALUE << AW_PID_2013_VOL_START_BIT)
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/* default value of SYSCTRL2 (0x05) */
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/* #define AW_PID_2013_SYSCTRL2_DEFAULT (0x6000) */
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/* I2SCTRL1 (0x06) detail */
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/* I2SRXEN bit 15 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2SRXEN_START_BIT (15)
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#define AW_PID_2013_I2SRXEN_BITS_LEN (1)
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#define AW_PID_2013_I2SRXEN_MASK \
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(~(((1<<AW_PID_2013_I2SRXEN_BITS_LEN)-1) << AW_PID_2013_I2SRXEN_START_BIT))
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#define AW_PID_2013_I2SRXEN_DISABLE (0)
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#define AW_PID_2013_I2SRXEN_DISABLE_VALUE \
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(AW_PID_2013_I2SRXEN_DISABLE << AW_PID_2013_I2SRXEN_START_BIT)
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#define AW_PID_2013_I2SRXEN_ENABLE (1)
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#define AW_PID_2013_I2SRXEN_ENABLE_VALUE \
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(AW_PID_2013_I2SRXEN_ENABLE << AW_PID_2013_I2SRXEN_START_BIT)
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#define AW_PID_2013_I2SRXEN_DEFAULT_VALUE (1)
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#define AW_PID_2013_I2SRXEN_DEFAULT \
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(AW_PID_2013_I2SRXEN_DEFAULT_VALUE << AW_PID_2013_I2SRXEN_START_BIT)
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/* I2STXEN bit 14 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2STXEN_START_BIT (14)
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#define AW_PID_2013_I2STXEN_BITS_LEN (1)
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#define AW_PID_2013_I2STXEN_MASK \
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(~(((1<<AW_PID_2013_I2STXEN_BITS_LEN)-1) << AW_PID_2013_I2STXEN_START_BIT))
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#define AW_PID_2013_I2STXEN_DISABLE (0)
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#define AW_PID_2013_I2STXEN_DISABLE_VALUE \
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(AW_PID_2013_I2STXEN_DISABLE << AW_PID_2013_I2STXEN_START_BIT)
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#define AW_PID_2013_I2STXEN_ENABLE (1)
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#define AW_PID_2013_I2STXEN_ENABLE_VALUE \
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(AW_PID_2013_I2STXEN_ENABLE << AW_PID_2013_I2STXEN_START_BIT)
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#define AW_PID_2013_I2STXEN_DEFAULT_VALUE (0)
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#define AW_PID_2013_I2STXEN_DEFAULT \
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(AW_PID_2013_I2STXEN_DEFAULT_VALUE << AW_PID_2013_I2STXEN_START_BIT)
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/* CFSEL bit 13:12 (I2SCTRL1 0x06) */
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#define AW_PID_2013_CFSEL_START_BIT (12)
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#define AW_PID_2013_CFSEL_BITS_LEN (2)
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#define AW_PID_2013_CFSEL_MASK \
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(~(((1<<AW_PID_2013_CFSEL_BITS_LEN)-1) << AW_PID_2013_CFSEL_START_BIT))
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#define AW_PID_2013_CFSEL_HAGC (0)
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#define AW_PID_2013_CFSEL_HAGC_VALUE \
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(AW_PID_2013_CFSEL_HAGC << AW_PID_2013_CFSEL_START_BIT)
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#define AW_PID_2013_CFSEL_IV (1)
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#define AW_PID_2013_CFSEL_IV_VALUE \
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(AW_PID_2013_CFSEL_IV << AW_PID_2013_CFSEL_START_BIT)
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#define AW_PID_2013_CFSEL_IVT_IPVT (2)
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#define AW_PID_2013_CFSEL_IVT_IPVT_VALUE \
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(AW_PID_2013_CFSEL_IVT_IPVT << AW_PID_2013_CFSEL_START_BIT)
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#define AW_PID_2013_CFSEL_RESERVED (3)
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#define AW_PID_2013_CFSEL_RESERVED_VALUE \
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(AW_PID_2013_CFSEL_RESERVED << AW_PID_2013_CFSEL_START_BIT)
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#define AW_PID_2013_CFSEL_DEFAULT_VALUE (0)
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#define AW_PID_2013_CFSEL_DEFAULT \
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(AW_PID_2013_CFSEL_DEFAULT_VALUE << AW_PID_2013_CFSEL_START_BIT)
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/* CHSEL bit 11:10 (I2SCTRL1 0x06) */
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#define AW_PID_2013_CHSEL_START_BIT (10)
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#define AW_PID_2013_CHSEL_BITS_LEN (2)
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#define AW_PID_2013_CHSEL_MASK \
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(~(((1<<AW_PID_2013_CHSEL_BITS_LEN)-1) << AW_PID_2013_CHSEL_START_BIT))
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#define AW_PID_2013_CHSEL_RESERVED (0)
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#define AW_PID_2013_CHSEL_RESERVED_VALUE \
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(AW_PID_2013_CHSEL_RESERVED << AW_PID_2013_CHSEL_START_BIT)
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#define AW_PID_2013_CHSEL_LEFT (1)
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#define AW_PID_2013_CHSEL_LEFT_VALUE \
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(AW_PID_2013_CHSEL_LEFT << AW_PID_2013_CHSEL_START_BIT)
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#define AW_PID_2013_CHSEL_RIGHT (2)
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#define AW_PID_2013_CHSEL_RIGHT_VALUE \
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(AW_PID_2013_CHSEL_RIGHT << AW_PID_2013_CHSEL_START_BIT)
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#define AW_PID_2013_CHSEL_MONO (3)
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#define AW_PID_2013_CHSEL_MONO_VALUE \
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(AW_PID_2013_CHSEL_MONO << AW_PID_2013_CHSEL_START_BIT)
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#define AW_PID_2013_CHSEL_DEFAULT_VALUE (1)
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#define AW_PID_2013_CHSEL_DEFAULT \
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(AW_PID_2013_CHSEL_DEFAULT_VALUE << AW_PID_2013_CHSEL_START_BIT)
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/* I2SMD bit 9:8 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2SMD_START_BIT (8)
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#define AW_PID_2013_I2SMD_BITS_LEN (2)
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#define AW_PID_2013_I2SMD_MASK \
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(~(((1<<AW_PID_2013_I2SMD_BITS_LEN)-1) << AW_PID_2013_I2SMD_START_BIT))
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#define AW_PID_2013_I2SMD_PHILIP_STANDARD (0)
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#define AW_PID_2013_I2SMD_PHILIP_STANDARD_VALUE \
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(AW_PID_2013_I2SMD_PHILIP_STANDARD << AW_PID_2013_I2SMD_START_BIT)
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#define AW_PID_2013_I2SMD_MSB_JUSTIFIED (1)
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#define AW_PID_2013_I2SMD_MSB_JUSTIFIED_VALUE \
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(AW_PID_2013_I2SMD_MSB_JUSTIFIED << AW_PID_2013_I2SMD_START_BIT)
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#define AW_PID_2013_I2SMD_LSB_JUSTIFIED (2)
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#define AW_PID_2013_I2SMD_LSB_JUSTIFIED_VALUE \
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(AW_PID_2013_I2SMD_LSB_JUSTIFIED << AW_PID_2013_I2SMD_START_BIT)
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#define AW_PID_2013_I2SMD_RESERVED (3)
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#define AW_PID_2013_I2SMD_RESERVED_VALUE \
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(AW_PID_2013_I2SMD_RESERVED << AW_PID_2013_I2SMD_START_BIT)
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#define AW_PID_2013_I2SMD_DEFAULT_VALUE (0)
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#define AW_PID_2013_I2SMD_DEFAULT \
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(AW_PID_2013_I2SMD_DEFAULT_VALUE << AW_PID_2013_I2SMD_START_BIT)
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/* I2SFS bit 7:6 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2SFS_START_BIT (6)
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#define AW_PID_2013_I2SFS_BITS_LEN (2)
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#define AW_PID_2013_I2SFS_MASK \
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(~(((1<<AW_PID_2013_I2SFS_BITS_LEN)-1) << AW_PID_2013_I2SFS_START_BIT))
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#define AW_PID_2013_I2SFS_16_BITS (0)
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#define AW_PID_2013_I2SFS_16_BITS_VALUE \
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(AW_PID_2013_I2SFS_16_BITS << AW_PID_2013_I2SFS_START_BIT)
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#define AW_PID_2013_I2SFS_20_BITS (1)
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#define AW_PID_2013_I2SFS_20_BITS_VALUE \
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(AW_PID_2013_I2SFS_20_BITS << AW_PID_2013_I2SFS_START_BIT)
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#define AW_PID_2013_I2SFS_24_BITS (2)
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#define AW_PID_2013_I2SFS_24_BITS_VALUE \
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(AW_PID_2013_I2SFS_24_BITS << AW_PID_2013_I2SFS_START_BIT)
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#define AW_PID_2013_I2SFS_32_BITS (3)
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#define AW_PID_2013_I2SFS_32_BITS_VALUE \
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(AW_PID_2013_I2SFS_32_BITS << AW_PID_2013_I2SFS_START_BIT)
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#define AW_PID_2013_I2SFS_DEFAULT_VALUE (3)
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#define AW_PID_2013_I2SFS_DEFAULT \
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(AW_PID_2013_I2SFS_DEFAULT_VALUE << AW_PID_2013_I2SFS_START_BIT)
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/* I2SBCK bit 5:4 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2SBCK_START_BIT (4)
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#define AW_PID_2013_I2SBCK_BITS_LEN (2)
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#define AW_PID_2013_I2SBCK_MASK \
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(~(((1<<AW_PID_2013_I2SBCK_BITS_LEN)-1) << AW_PID_2013_I2SBCK_START_BIT))
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#define AW_PID_2013_I2SBCK_32FS (0)
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#define AW_PID_2013_I2SBCK_32FS_VALUE \
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(AW_PID_2013_I2SBCK_32FS << AW_PID_2013_I2SBCK_START_BIT)
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#define AW_PID_2013_I2SBCK_48FS (1)
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#define AW_PID_2013_I2SBCK_48FS_VALUE \
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(AW_PID_2013_I2SBCK_48FS << AW_PID_2013_I2SBCK_START_BIT)
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#define AW_PID_2013_I2SBCK_64FS (2)
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#define AW_PID_2013_I2SBCK_64FS_VALUE \
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(AW_PID_2013_I2SBCK_64FS << AW_PID_2013_I2SBCK_START_BIT)
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#define AW_PID_2013_I2SBCK_RESERVED (3)
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#define AW_PID_2013_I2SBCK_RESERVED_VALUE \
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(AW_PID_2013_I2SBCK_RESERVED << AW_PID_2013_I2SBCK_START_BIT)
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#define AW_PID_2013_I2SBCK_DEFAULT_VALUE (2)
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#define AW_PID_2013_I2SBCK_DEFAULT \
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(AW_PID_2013_I2SBCK_DEFAULT_VALUE << AW_PID_2013_I2SBCK_START_BIT)
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/* I2SSR bit 3:0 (I2SCTRL1 0x06) */
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#define AW_PID_2013_I2SSR_START_BIT (0)
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#define AW_PID_2013_I2SSR_BITS_LEN (4)
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#define AW_PID_2013_I2SSR_MASK \
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(~(((1<<AW_PID_2013_I2SSR_BITS_LEN)-1) << AW_PID_2013_I2SSR_START_BIT))
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#define AW_PID_2013_I2SSR_8_KHZ (0)
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#define AW_PID_2013_I2SSR_8_KHZ_VALUE \
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(AW_PID_2013_I2SSR_8_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_11_KHZ (1)
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#define AW_PID_2013_I2SSR_11_KHZ_VALUE \
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(AW_PID_2013_I2SSR_11_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_12_KHZ (2)
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#define AW_PID_2013_I2SSR_12_KHZ_VALUE \
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(AW_PID_2013_I2SSR_12_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_16_KHZ (3)
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#define AW_PID_2013_I2SSR_16_KHZ_VALUE \
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(AW_PID_2013_I2SSR_16_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_22_KHZ (4)
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#define AW_PID_2013_I2SSR_22_KHZ_VALUE \
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(AW_PID_2013_I2SSR_22_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_24_KHZ (5)
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#define AW_PID_2013_I2SSR_24_KHZ_VALUE \
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(AW_PID_2013_I2SSR_24_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_32_KHZ (6)
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#define AW_PID_2013_I2SSR_32_KHZ_VALUE \
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(AW_PID_2013_I2SSR_32_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_44_KHZ (7)
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#define AW_PID_2013_I2SSR_44_KHZ_VALUE \
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(AW_PID_2013_I2SSR_44_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_48_KHZ (8)
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#define AW_PID_2013_I2SSR_48_KHZ_VALUE \
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(AW_PID_2013_I2SSR_48_KHZ << AW_PID_2013_I2SSR_START_BIT)
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#define AW_PID_2013_I2SSR_96_KHZ (9)
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#define AW_PID_2013_I2SSR_96_KHZ_VALUE \
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(AW_PID_2013_I2SSR_96_KHZ << AW_PID_2013_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2013_I2SSR_192_KHZ (10)
|
|
#define AW_PID_2013_I2SSR_192_KHZ_VALUE \
|
|
(AW_PID_2013_I2SSR_192_KHZ << AW_PID_2013_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2013_I2SSR_DEFAULT_VALUE (8)
|
|
#define AW_PID_2013_I2SSR_DEFAULT \
|
|
(AW_PID_2013_I2SSR_DEFAULT_VALUE << AW_PID_2013_I2SSR_START_BIT)
|
|
|
|
/* default value of I2SCTRL1 (0x06) */
|
|
/* #define AW_PID_2013_I2SCTRL1_DEFAULT (0x84E8) */
|
|
|
|
/* I2SCTRL2 (0x07) detail */
|
|
/* FSYNC_TYPE bit 15 (I2SCTRL2 0x07) */
|
|
#define AW_PID_2013_FSYNC_TYPE_START_BIT (15)
|
|
#define AW_PID_2013_FSYNC_TYPE_BITS_LEN (1)
|
|
#define AW_PID_2013_FSYNC_TYPE_MASK \
|
|
(~(((1<<AW_PID_2013_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2013_FSYNC_TYPE_START_BIT))
|
|
|
|
#define AW_PID_2013_FSYNC_TYPE_ONEMINUS_SLOT (0)
|
|
#define AW_PID_2013_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \
|
|
(AW_PID_2013_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2013_FSYNC_TYPE_START_BIT)
|
|
|
|
#define AW_PID_2013_FSYNC_TYPE_ONEMINUS_BCK (1)
|
|
#define AW_PID_2013_FSYNC_TYPE_ONEMINUS_BCK_VALUE \
|
|
(AW_PID_2013_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2013_FSYNC_TYPE_START_BIT)
|
|
|
|
#define AW_PID_2013_FSYNC_TYPE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_FSYNC_TYPE_DEFAULT \
|
|
(AW_PID_2013_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2013_FSYNC_TYPE_START_BIT)
|
|
|
|
/* SLOT_NUM bit 14:12 (I2SCTRL2 0x07) */
|
|
#define AW_PID_2013_SLOT_NUM_START_BIT (12)
|
|
#define AW_PID_2013_SLOT_NUM_BITS_LEN (3)
|
|
#define AW_PID_2013_SLOT_NUM_MASK \
|
|
(~(((1<<AW_PID_2013_SLOT_NUM_BITS_LEN)-1) << AW_PID_2013_SLOT_NUM_START_BIT))
|
|
|
|
#define AW_PID_2013_SLOT_NUM_I2S_MODE (0)
|
|
#define AW_PID_2013_SLOT_NUM_I2S_MODE_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_I2S_MODE << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM1S (1)
|
|
#define AW_PID_2013_SLOT_NUM_TDM1S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM1S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM2S (2)
|
|
#define AW_PID_2013_SLOT_NUM_TDM2S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM2S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM4S (3)
|
|
#define AW_PID_2013_SLOT_NUM_TDM4S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM4S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM6S (4)
|
|
#define AW_PID_2013_SLOT_NUM_TDM6S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM6S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM8S (5)
|
|
#define AW_PID_2013_SLOT_NUM_TDM8S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM8S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
#define AW_PID_2013_SLOT_NUM_TDM16S (6)
|
|
#define AW_PID_2013_SLOT_NUM_TDM16S_VALUE \
|
|
(AW_PID_2013_SLOT_NUM_TDM16S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
/*
|
|
*#define AW_PID_2013_SLOT_NUM_TDM16S (7)
|
|
*#define AW_PID_2013_SLOT_NUM_TDM16S_VALUE \
|
|
* (AW_PID_2013_SLOT_NUM_TDM16S << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
*/
|
|
|
|
#define AW_PID_2013_SLOT_NUM_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_SLOT_NUM_DEFAULT \
|
|
(AW_PID_2013_SLOT_NUM_DEFAULT_VALUE << AW_PID_2013_SLOT_NUM_START_BIT)
|
|
|
|
/* I2S_TX_SLOTVLD bit 11:8 (I2SCTRL2 0x07) */
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_START_BIT (8)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_BITS_LEN (4)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_MASK \
|
|
(~(((1<<AW_PID_2013_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT))
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_0 (0)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_0_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_1 (1)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_1_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_2 (2)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_2_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_3 (3)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_3_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_4 (4)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_4_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_4 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_5 (5)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_5_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_5 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_6 (6)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_6_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_6 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_15 (15)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_SLOT_15_VALUE \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_I2S_TX_SLOTVLD_DEFAULT \
|
|
(AW_PID_2013_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2013_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
/* I2S_RXR_SLOTVLD bit 7:4 (I2SCTRL2 0x07) */
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT (4)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_BITS_LEN (4)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_MASK \
|
|
(~(((1<<AW_PID_2013_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT))
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_0 (0)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_0_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_1 (1)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_1_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_2 (2)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_2_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_3 (3)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_3_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_4 (4)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_4_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_4 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_5 (5)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_5_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_5 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_6 (6)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_6_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_6 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_15 (15)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_15_VALUE \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_DEFAULT_VALUE (1)
|
|
#define AW_PID_2013_I2S_RXR_SLOTVLD_DEFAULT \
|
|
(AW_PID_2013_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2013_I2S_RXR_SLOTVLD_START_BIT)
|
|
|
|
/* I2S_RXL_SLOTVLD bit 3:0 (I2SCTRL2 0x07) */
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT (0)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_BITS_LEN (4)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_MASK \
|
|
(~(((1<<AW_PID_2013_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT))
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_0 (0)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_0_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_1 (1)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_1_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_2 (2)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_2_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_3 (3)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_3_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_4 (4)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_4_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_4 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_5 (5)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_5_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_5 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_6 (6)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_6_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_6 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_15 (15)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_15_VALUE \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_I2S_RXL_SLOTVLD_DEFAULT \
|
|
(AW_PID_2013_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2013_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
/* default value of I2SCTRL2 (0x07) */
|
|
/* #define AW_PID_2013_I2SCTRL2_DEFAULT (0x0010) */
|
|
|
|
/* DACCFG1 (0x08) detail */
|
|
/* RVTH bit 15:8 (DACCFG1 0x08) */
|
|
#define AW_PID_2013_RVTH_START_BIT (8)
|
|
#define AW_PID_2013_RVTH_BITS_LEN (8)
|
|
#define AW_PID_2013_RVTH_MASK \
|
|
(~(((1<<AW_PID_2013_RVTH_BITS_LEN)-1) << AW_PID_2013_RVTH_START_BIT))
|
|
|
|
#define AW_PID_2013_RVTH_DEFAULT_VALUE (0x39)
|
|
#define AW_PID_2013_RVTH_DEFAULT \
|
|
(AW_PID_2013_RVTH_DEFAULT_VALUE << AW_PID_2013_RVTH_START_BIT)
|
|
|
|
/* AVTH bit 7:0 (DACCFG1 0x08) */
|
|
#define AW_PID_2013_AVTH_START_BIT (0)
|
|
#define AW_PID_2013_AVTH_BITS_LEN (8)
|
|
#define AW_PID_2013_AVTH_MASK \
|
|
(~(((1<<AW_PID_2013_AVTH_BITS_LEN)-1) << AW_PID_2013_AVTH_START_BIT))
|
|
|
|
#define AW_PID_2013_AVTH_DEFAULT_VALUE (0x40)
|
|
#define AW_PID_2013_AVTH_DEFAULT \
|
|
(AW_PID_2013_AVTH_DEFAULT_VALUE << AW_PID_2013_AVTH_START_BIT)
|
|
|
|
/* default value of DACCFG1 (0x08) */
|
|
/* #define AW_PID_2013_DACCFG1_DEFAULT (0x3940) */
|
|
|
|
/* DACCFG2 (0x09) detail */
|
|
/* ATTH bit 15:0 (DACCFG2 0x09) */
|
|
#define AW_PID_2013_ATTH_START_BIT (0)
|
|
#define AW_PID_2013_ATTH_BITS_LEN (16)
|
|
#define AW_PID_2013_ATTH_MASK \
|
|
(~(((1<<AW_PID_2013_ATTH_BITS_LEN)-1) << AW_PID_2013_ATTH_START_BIT))
|
|
|
|
#define AW_PID_2013_ATTH_RESERVED (0)
|
|
#define AW_PID_2013_ATTH_RESERVED_VALUE \
|
|
(AW_PID_2013_ATTH_RESERVED << AW_PID_2013_ATTH_START_BIT)
|
|
|
|
#define AW_PID_2013_ATTH_DEFAULT_VALUE (0x0030)
|
|
#define AW_PID_2013_ATTH_DEFAULT \
|
|
(AW_PID_2013_ATTH_DEFAULT_VALUE << AW_PID_2013_ATTH_START_BIT)
|
|
|
|
/* default value of DACCFG2 (0x09) */
|
|
/* #define AW_PID_2013_DACCFG2_DEFAULT (0x0030) */
|
|
|
|
/* DACCFG3 (0x0A) detail */
|
|
/* RTTH bit 15:0 (DACCFG3 0x0A) */
|
|
#define AW_PID_2013_RTTH_START_BIT (0)
|
|
#define AW_PID_2013_RTTH_BITS_LEN (16)
|
|
#define AW_PID_2013_RTTH_MASK \
|
|
(~(((1<<AW_PID_2013_RTTH_BITS_LEN)-1) << AW_PID_2013_RTTH_START_BIT))
|
|
|
|
#define AW_PID_2013_RTTH_RESERVED (0)
|
|
#define AW_PID_2013_RTTH_RESERVED_VALUE \
|
|
(AW_PID_2013_RTTH_RESERVED << AW_PID_2013_RTTH_START_BIT)
|
|
|
|
#define AW_PID_2013_RTTH_DEFAULT_VALUE (0x01E0)
|
|
#define AW_PID_2013_RTTH_DEFAULT \
|
|
(AW_PID_2013_RTTH_DEFAULT_VALUE << AW_PID_2013_RTTH_START_BIT)
|
|
|
|
/* default value of DACCFG3 (0x0A) */
|
|
/* #define AW_PID_2013_DACCFG3_DEFAULT (0x01E0) */
|
|
|
|
/* DACCFG4 (0x0B) detail */
|
|
/* IIC_GEN_ADDR bit 15:9 (DACCFG4 0x0B) */
|
|
#define AW_PID_2013_IIC_GEN_ADDR_START_BIT (9)
|
|
#define AW_PID_2013_IIC_GEN_ADDR_BITS_LEN (7)
|
|
#define AW_PID_2013_IIC_GEN_ADDR_MASK \
|
|
(~(((1<<AW_PID_2013_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2013_IIC_GEN_ADDR_START_BIT))
|
|
|
|
#define AW_PID_2013_IIC_GEN_ADDR_DEFAULT_VALUE (0x0E)
|
|
#define AW_PID_2013_IIC_GEN_ADDR_DEFAULT \
|
|
(AW_PID_2013_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2013_IIC_GEN_ADDR_START_BIT)
|
|
|
|
/* IIC_GEN_EN bit 8 (DACCFG4 0x0B) */
|
|
#define AW_PID_2013_IIC_GEN_EN_START_BIT (8)
|
|
#define AW_PID_2013_IIC_GEN_EN_BITS_LEN (1)
|
|
#define AW_PID_2013_IIC_GEN_EN_MASK \
|
|
(~(((1<<AW_PID_2013_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2013_IIC_GEN_EN_START_BIT))
|
|
|
|
#define AW_PID_2013_IIC_GEN_EN_DISABLE (0)
|
|
#define AW_PID_2013_IIC_GEN_EN_DISABLE_VALUE \
|
|
(AW_PID_2013_IIC_GEN_EN_DISABLE << AW_PID_2013_IIC_GEN_EN_START_BIT)
|
|
|
|
#define AW_PID_2013_IIC_GEN_EN_ENABLE (1)
|
|
#define AW_PID_2013_IIC_GEN_EN_ENABLE_VALUE \
|
|
(AW_PID_2013_IIC_GEN_EN_ENABLE << AW_PID_2013_IIC_GEN_EN_START_BIT)
|
|
|
|
#define AW_PID_2013_IIC_GEN_EN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_IIC_GEN_EN_DEFAULT \
|
|
(AW_PID_2013_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2013_IIC_GEN_EN_START_BIT)
|
|
|
|
/* HOLDTH bit 7:0 (DACCFG4 0x0B) */
|
|
#define AW_PID_2013_HOLDTH_START_BIT (0)
|
|
#define AW_PID_2013_HOLDTH_BITS_LEN (8)
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#define AW_PID_2013_HOLDTH_MASK \
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(~(((1<<AW_PID_2013_HOLDTH_BITS_LEN)-1) << AW_PID_2013_HOLDTH_START_BIT))
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#define AW_PID_2013_HOLDTH_RESERVED (0)
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#define AW_PID_2013_HOLDTH_RESERVED_VALUE \
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(AW_PID_2013_HOLDTH_RESERVED << AW_PID_2013_HOLDTH_START_BIT)
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#define AW_PID_2013_HOLDTH_DEFAULT_VALUE (0x64)
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#define AW_PID_2013_HOLDTH_DEFAULT \
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(AW_PID_2013_HOLDTH_DEFAULT_VALUE << AW_PID_2013_HOLDTH_START_BIT)
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/* default value of DACCFG4 (0x0B) */
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/* #define AW_PID_2013_DACCFG4_DEFAULT (0x1C64) */
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/* DACST (0x20) detail */
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/* SET_GAIN_ST bit 10:8 (DACST 0x20) */
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#define AW_PID_2013_SET_GAIN_ST_START_BIT (8)
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#define AW_PID_2013_SET_GAIN_ST_BITS_LEN (3)
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#define AW_PID_2013_SET_GAIN_ST_MASK \
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(~(((1<<AW_PID_2013_SET_GAIN_ST_BITS_LEN)-1) << AW_PID_2013_SET_GAIN_ST_START_BIT))
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#define AW_PID_2013_SET_GAIN_ST_4P5_AV (0)
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#define AW_PID_2013_SET_GAIN_ST_4P5_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_4P5_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_5P0_AV (1)
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#define AW_PID_2013_SET_GAIN_ST_5P0_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_5P0_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_6P0_AV (2)
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#define AW_PID_2013_SET_GAIN_ST_6P0_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_6P0_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_6P7_AV (3)
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#define AW_PID_2013_SET_GAIN_ST_6P7_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_6P7_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_10_AV (4)
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#define AW_PID_2013_SET_GAIN_ST_10_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_10_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_12_AV (5)
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#define AW_PID_2013_SET_GAIN_ST_12_AV_VALUE \
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(AW_PID_2013_SET_GAIN_ST_12_AV << AW_PID_2013_SET_GAIN_ST_START_BIT)
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#define AW_PID_2013_SET_GAIN_ST_DEFAULT_VALUE (5)
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#define AW_PID_2013_SET_GAIN_ST_DEFAULT \
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(AW_PID_2013_SET_GAIN_ST_DEFAULT_VALUE << AW_PID_2013_SET_GAIN_ST_START_BIT)
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/* BSTVOUT_ST bit 3:0 (DACST 0x20) */
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#define AW_PID_2013_BSTVOUT_ST_START_BIT (0)
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#define AW_PID_2013_BSTVOUT_ST_BITS_LEN (4)
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#define AW_PID_2013_BSTVOUT_ST_MASK \
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(~(((1<<AW_PID_2013_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2013_BSTVOUT_ST_START_BIT))
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#define AW_PID_2013_BSTVOUT_ST_3P25V (0)
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#define AW_PID_2013_BSTVOUT_ST_3P25V_VALUE \
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(AW_PID_2013_BSTVOUT_ST_3P25V << AW_PID_2013_BSTVOUT_ST_START_BIT)
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#define AW_PID_2013_BSTVOUT_ST_3P50V (1)
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#define AW_PID_2013_BSTVOUT_ST_3P50V_VALUE \
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(AW_PID_2013_BSTVOUT_ST_3P50V << AW_PID_2013_BSTVOUT_ST_START_BIT)
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#define AW_PID_2013_BSTVOUT_ST_3P75V (2)
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#define AW_PID_2013_BSTVOUT_ST_3P75V_VALUE \
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(AW_PID_2013_BSTVOUT_ST_3P75V << AW_PID_2013_BSTVOUT_ST_START_BIT)
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#define AW_PID_2013_BSTVOUT_ST_7P00V (15)
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#define AW_PID_2013_BSTVOUT_ST_7P00V_VALUE \
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(AW_PID_2013_BSTVOUT_ST_7P00V << AW_PID_2013_BSTVOUT_ST_START_BIT)
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#define AW_PID_2013_BSTVOUT_ST_DEFAULT_VALUE (0)
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#define AW_PID_2013_BSTVOUT_ST_DEFAULT \
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(AW_PID_2013_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2013_BSTVOUT_ST_START_BIT)
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/* default value of DACST (0x20) */
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/* #define AW_PID_2013_DACST_DEFAULT (0x0500) */
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/* VBAT (0x21) detail */
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/* VBAT_DET bit 9:0 (VBAT 0x21) */
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#define AW_PID_2013_VBAT_DET_START_BIT (0)
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#define AW_PID_2013_VBAT_DET_BITS_LEN (10)
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#define AW_PID_2013_VBAT_DET_MASK \
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(~(((1<<AW_PID_2013_VBAT_DET_BITS_LEN)-1) << AW_PID_2013_VBAT_DET_START_BIT))
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#define AW_PID_2013_VBAT_DET_DEFAULT_VALUE (0x263)
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#define AW_PID_2013_VBAT_DET_DEFAULT \
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(AW_PID_2013_VBAT_DET_DEFAULT_VALUE << AW_PID_2013_VBAT_DET_START_BIT)
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/* default value of VBAT (0x21) */
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/* #define AW_PID_2013_VBAT_DEFAULT (0x0263) */
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/* TEMP (0x22) detail */
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/* TEMP_DET bit 9:0 (TEMP 0x22) */
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#define AW_PID_2013_TEMP_DET_START_BIT (0)
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#define AW_PID_2013_TEMP_DET_BITS_LEN (10)
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#define AW_PID_2013_TEMP_DET_MASK \
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(~(((1<<AW_PID_2013_TEMP_DET_BITS_LEN)-1) << AW_PID_2013_TEMP_DET_START_BIT))
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#define AW_PID_2013_TEMP_DET_MINUS_40_DEGREE (0x3D8)
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#define AW_PID_2013_TEMP_DET_MINUS_40_DEGREE_VALUE \
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(AW_PID_2013_TEMP_DET_MINUS_40_DEGREE << AW_PID_2013_TEMP_DET_START_BIT)
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#define AW_PID_2013_TEMP_DET_0_DEGREE (0x00)
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#define AW_PID_2013_TEMP_DET_0_DEGREE_VALUE \
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(AW_PID_2013_TEMP_DET_0_DEGREE << AW_PID_2013_TEMP_DET_START_BIT)
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#define AW_PID_2013_TEMP_DET_1_DEGREE (0x01)
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#define AW_PID_2013_TEMP_DET_1_DEGREE_VALUE \
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(AW_PID_2013_TEMP_DET_1_DEGREE << AW_PID_2013_TEMP_DET_START_BIT)
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#define AW_PID_2013_TEMP_DET_25_DEGREE (0x19)
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#define AW_PID_2013_TEMP_DET_25_DEGREE_VALUE \
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(AW_PID_2013_TEMP_DET_25_DEGREE << AW_PID_2013_TEMP_DET_START_BIT)
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#define AW_PID_2013_TEMP_DET_55_DEGREE (0x37)
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#define AW_PID_2013_TEMP_DET_55_DEGREE_VALUE \
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(AW_PID_2013_TEMP_DET_55_DEGREE << AW_PID_2013_TEMP_DET_START_BIT)
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#define AW_PID_2013_TEMP_DET_DEFAULT_VALUE (0x019)
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#define AW_PID_2013_TEMP_DET_DEFAULT \
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(AW_PID_2013_TEMP_DET_DEFAULT_VALUE << AW_PID_2013_TEMP_DET_START_BIT)
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/* default value of TEMP (0x22) */
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/* #define AW_PID_2013_TEMP_DEFAULT (0x0019) */
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|
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/* PVDD (0x23) detail */
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/* PVDD_DET bit 9:0 (PVDD 0x23) */
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#define AW_PID_2013_PVDD_DET_START_BIT (0)
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#define AW_PID_2013_PVDD_DET_BITS_LEN (10)
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#define AW_PID_2013_PVDD_DET_MASK \
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(~(((1<<AW_PID_2013_PVDD_DET_BITS_LEN)-1) << AW_PID_2013_PVDD_DET_START_BIT))
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#define AW_PID_2013_PVDD_DET_DEFAULT_VALUE (0x263)
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#define AW_PID_2013_PVDD_DET_DEFAULT \
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(AW_PID_2013_PVDD_DET_DEFAULT_VALUE << AW_PID_2013_PVDD_DET_START_BIT)
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/* default value of PVDD (0x23) */
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/* #define AW_PID_2013_PVDD_DEFAULT (0x0263) */
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|
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/* CCO_MUX bit 2 (PLLCTRL3 0x55) */
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#define AW_PID_2013_CCO_MUX_START_BIT (2)
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#define AW_PID_2013_CCO_MUX_BITS_LEN (1)
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#define AW_PID_2013_CCO_MUX_MASK \
|
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(~(((1<<AW_PID_2013_CCO_MUX_BITS_LEN)-1) << AW_PID_2013_CCO_MUX_START_BIT))
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#define AW_PID_2013_CCO_MUX_DIVIDED (0)
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#define AW_PID_2013_CCO_MUX_DIVIDED_VALUE \
|
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(AW_PID_2013_CCO_MUX_DIVIDED << AW_PID_2013_CCO_MUX_START_BIT)
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#define AW_PID_2013_CCO_MUX_BYPASS (1)
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#define AW_PID_2013_CCO_MUX_BYPASS_VALUE \
|
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(AW_PID_2013_CCO_MUX_BYPASS << AW_PID_2013_CCO_MUX_START_BIT)
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|
|
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/* BSTCTRL1 (0x60) detail */
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|
/* BURST_OVPCTR bit 15 (BSTCTRL1 0x60) */
|
|
#define AW_PID_2013_BURST_OVPCTR_START_BIT (15)
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|
#define AW_PID_2013_BURST_OVPCTR_BITS_LEN (1)
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|
#define AW_PID_2013_BURST_OVPCTR_MASK \
|
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(~(((1<<AW_PID_2013_BURST_OVPCTR_BITS_LEN)-1) << AW_PID_2013_BURST_OVPCTR_START_BIT))
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#define AW_PID_2013_BURST_OVPCTR_DISABLE (0)
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#define AW_PID_2013_BURST_OVPCTR_DISABLE_VALUE \
|
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(AW_PID_2013_BURST_OVPCTR_DISABLE << AW_PID_2013_BURST_OVPCTR_START_BIT)
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|
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#define AW_PID_2013_BURST_OVPCTR_ENABLE (1)
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#define AW_PID_2013_BURST_OVPCTR_ENABLE_VALUE \
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(AW_PID_2013_BURST_OVPCTR_ENABLE << AW_PID_2013_BURST_OVPCTR_START_BIT)
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#define AW_PID_2013_BURST_OVPCTR_DEFAULT_VALUE (1)
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#define AW_PID_2013_BURST_OVPCTR_DEFAULT \
|
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(AW_PID_2013_BURST_OVPCTR_DEFAULT_VALUE << AW_PID_2013_BURST_OVPCTR_START_BIT)
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|
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/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */
|
|
#define AW_PID_2013_BST_RTH_START_BIT (8)
|
|
#define AW_PID_2013_BST_RTH_BITS_LEN (6)
|
|
#define AW_PID_2013_BST_RTH_MASK \
|
|
(~(((1<<AW_PID_2013_BST_RTH_BITS_LEN)-1) << AW_PID_2013_BST_RTH_START_BIT))
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|
|
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#define AW_PID_2013_BST_RTH_DEFAULT_VALUE (4)
|
|
#define AW_PID_2013_BST_RTH_DEFAULT \
|
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(AW_PID_2013_BST_RTH_DEFAULT_VALUE << AW_PID_2013_BST_RTH_START_BIT)
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|
|
|
/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */
|
|
#define AW_PID_2013_BST_ATH_START_BIT (0)
|
|
#define AW_PID_2013_BST_ATH_BITS_LEN (6)
|
|
#define AW_PID_2013_BST_ATH_MASK \
|
|
(~(((1<<AW_PID_2013_BST_ATH_BITS_LEN)-1) << AW_PID_2013_BST_ATH_START_BIT))
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|
|
|
#define AW_PID_2013_BST_ATH_DEFAULT_VALUE (2)
|
|
#define AW_PID_2013_BST_ATH_DEFAULT \
|
|
(AW_PID_2013_BST_ATH_DEFAULT_VALUE << AW_PID_2013_BST_ATH_START_BIT)
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|
|
|
/* default value of BSTCTRL1 (0x60) */
|
|
/* #define AW_PID_2013_BSTCTRL1_DEFAULT (0x8402) */
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|
|
|
/* BSTCTRL2 (0x61) detail */
|
|
/* BST_VOUT6_SEL bit 15 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2013_BST_VOUT6_SEL_START_BIT (15)
|
|
#define AW_PID_2013_BST_VOUT6_SEL_BITS_LEN (1)
|
|
#define AW_PID_2013_BST_VOUT6_SEL_MASK \
|
|
(~(((1<<AW_PID_2013_BST_VOUT6_SEL_BITS_LEN)-1) << AW_PID_2013_BST_VOUT6_SEL_START_BIT))
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|
|
|
#define AW_PID_2013_BST_VOUT6_SEL_6P0V (0)
|
|
#define AW_PID_2013_BST_VOUT6_SEL_6P0V_VALUE \
|
|
(AW_PID_2013_BST_VOUT6_SEL_6P0V << AW_PID_2013_BST_VOUT6_SEL_START_BIT)
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|
|
#define AW_PID_2013_BST_VOUT6_SEL_6P1V (1)
|
|
#define AW_PID_2013_BST_VOUT6_SEL_6P1V_VALUE \
|
|
(AW_PID_2013_BST_VOUT6_SEL_6P1V << AW_PID_2013_BST_VOUT6_SEL_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_VOUT6_SEL_DEFAULT_VALUE (0)
|
|
#define AW_PID_2013_BST_VOUT6_SEL_DEFAULT \
|
|
(AW_PID_2013_BST_VOUT6_SEL_DEFAULT_VALUE << AW_PID_2013_BST_VOUT6_SEL_START_BIT)
|
|
|
|
/* BST_IPEAK bit 14:12 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2013_BST_IPEAK_START_BIT (12)
|
|
#define AW_PID_2013_BST_IPEAK_BITS_LEN (3)
|
|
#define AW_PID_2013_BST_IPEAK_MASK \
|
|
(~(((1<<AW_PID_2013_BST_IPEAK_BITS_LEN)-1) << AW_PID_2013_BST_IPEAK_START_BIT))
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|
|
|
#define AW_PID_2013_BST_IPEAK_1P20A (0)
|
|
#define AW_PID_2013_BST_IPEAK_1P20A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_1P20A << AW_PID_2013_BST_IPEAK_START_BIT)
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|
|
|
#define AW_PID_2013_BST_IPEAK_1P40A (1)
|
|
#define AW_PID_2013_BST_IPEAK_1P40A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_1P40A << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_IPEAK_1P60A (2)
|
|
#define AW_PID_2013_BST_IPEAK_1P60A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_1P60A << AW_PID_2013_BST_IPEAK_START_BIT)
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|
|
|
#define AW_PID_2013_BST_IPEAK_1P80A (3)
|
|
#define AW_PID_2013_BST_IPEAK_1P80A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_1P80A << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_IPEAK_2P00A (4)
|
|
#define AW_PID_2013_BST_IPEAK_2P00A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_2P00A << AW_PID_2013_BST_IPEAK_START_BIT)
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|
|
|
#define AW_PID_2013_BST_IPEAK_2P25A (5)
|
|
#define AW_PID_2013_BST_IPEAK_2P25A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_2P25A << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_IPEAK_2P50A (6)
|
|
#define AW_PID_2013_BST_IPEAK_2P50A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_2P50A << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_IPEAK_2P75A (7)
|
|
#define AW_PID_2013_BST_IPEAK_2P75A_VALUE \
|
|
(AW_PID_2013_BST_IPEAK_2P75A << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_IPEAK_DEFAULT_VALUE (6)
|
|
#define AW_PID_2013_BST_IPEAK_DEFAULT \
|
|
(AW_PID_2013_BST_IPEAK_DEFAULT_VALUE << AW_PID_2013_BST_IPEAK_START_BIT)
|
|
|
|
/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2013_BST_TDEG_START_BIT (8)
|
|
#define AW_PID_2013_BST_TDEG_BITS_LEN (4)
|
|
#define AW_PID_2013_BST_TDEG_MASK \
|
|
(~(((1<<AW_PID_2013_BST_TDEG_BITS_LEN)-1) << AW_PID_2013_BST_TDEG_START_BIT))
|
|
|
|
#define AW_PID_2013_BST_TDEG_0P50_MS (0)
|
|
#define AW_PID_2013_BST_TDEG_0P50_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_0P50_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_1P00_MS (1)
|
|
#define AW_PID_2013_BST_TDEG_1P00_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_1P00_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_2P00_MS (2)
|
|
#define AW_PID_2013_BST_TDEG_2P00_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_2P00_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_4P00_MS (3)
|
|
#define AW_PID_2013_BST_TDEG_4P00_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_4P00_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_8P00_MS (4)
|
|
#define AW_PID_2013_BST_TDEG_8P00_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_8P00_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_10P7_MS (5)
|
|
#define AW_PID_2013_BST_TDEG_10P7_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_10P7_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_13P3_MS (6)
|
|
#define AW_PID_2013_BST_TDEG_13P3_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_13P3_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_16P0_MS (7)
|
|
#define AW_PID_2013_BST_TDEG_16P0_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_16P0_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_18P6_MS (8)
|
|
#define AW_PID_2013_BST_TDEG_18P6_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_18P6_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_21P3_MS (9)
|
|
#define AW_PID_2013_BST_TDEG_21P3_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_21P3_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_24P0_MS (10)
|
|
#define AW_PID_2013_BST_TDEG_24P0_MS_VALUE \
|
|
(AW_PID_2013_BST_TDEG_24P0_MS << AW_PID_2013_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2013_BST_TDEG_32P0_MS (11)
|
|
#define AW_PID_2013_BST_TDEG_32P0_MS_VALUE \
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(AW_PID_2013_BST_TDEG_32P0_MS << AW_PID_2013_BST_TDEG_START_BIT)
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#define AW_PID_2013_BST_TDEG_64P0_MS (12)
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#define AW_PID_2013_BST_TDEG_64P0_MS_VALUE \
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(AW_PID_2013_BST_TDEG_64P0_MS << AW_PID_2013_BST_TDEG_START_BIT)
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#define AW_PID_2013_BST_TDEG_128_MS (13)
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#define AW_PID_2013_BST_TDEG_128_MS_VALUE \
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(AW_PID_2013_BST_TDEG_128_MS << AW_PID_2013_BST_TDEG_START_BIT)
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#define AW_PID_2013_BST_TDEG_256_MS (14)
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#define AW_PID_2013_BST_TDEG_256_MS_VALUE \
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(AW_PID_2013_BST_TDEG_256_MS << AW_PID_2013_BST_TDEG_START_BIT)
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#define AW_PID_2013_BST_TDEG_1200_MS (15)
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#define AW_PID_2013_BST_TDEG_1200_MS_VALUE \
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(AW_PID_2013_BST_TDEG_1200_MS << AW_PID_2013_BST_TDEG_START_BIT)
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#define AW_PID_2013_BST_TDEG_DEFAULT_VALUE (11)
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#define AW_PID_2013_BST_TDEG_DEFAULT \
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(AW_PID_2013_BST_TDEG_DEFAULT_VALUE << AW_PID_2013_BST_TDEG_START_BIT)
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/* BURST_FRE bit 7 (BSTCTRL2 0x61) */
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#define AW_PID_2013_BURST_FRE_START_BIT (7)
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#define AW_PID_2013_BURST_FRE_BITS_LEN (1)
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#define AW_PID_2013_BURST_FRE_MASK \
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(~(((1<<AW_PID_2013_BURST_FRE_BITS_LEN)-1) << AW_PID_2013_BURST_FRE_START_BIT))
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#define AW_PID_2013_BURST_FRE_20KHZ (0)
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#define AW_PID_2013_BURST_FRE_20KHZ_VALUE \
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(AW_PID_2013_BURST_FRE_20KHZ << AW_PID_2013_BURST_FRE_START_BIT)
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#define AW_PID_2013_BURST_FRE_30KHZ (1)
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#define AW_PID_2013_BURST_FRE_30KHZ_VALUE \
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(AW_PID_2013_BURST_FRE_30KHZ << AW_PID_2013_BURST_FRE_START_BIT)
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#define AW_PID_2013_BURST_FRE_DEFAULT_VALUE (0)
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#define AW_PID_2013_BURST_FRE_DEFAULT \
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(AW_PID_2013_BURST_FRE_DEFAULT_VALUE << AW_PID_2013_BURST_FRE_START_BIT)
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/* RSQN_DLY_EN bit 6 (BSTCTRL2 0x61) */
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#define AW_PID_2013_RSQN_DLY_EN_START_BIT (6)
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#define AW_PID_2013_RSQN_DLY_EN_BITS_LEN (1)
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#define AW_PID_2013_RSQN_DLY_EN_MASK \
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(~(((1<<AW_PID_2013_RSQN_DLY_EN_BITS_LEN)-1) << AW_PID_2013_RSQN_DLY_EN_START_BIT))
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#define AW_PID_2013_RSQN_DLY_EN_6NS (0)
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#define AW_PID_2013_RSQN_DLY_EN_6NS_VALUE \
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(AW_PID_2013_RSQN_DLY_EN_6NS << AW_PID_2013_RSQN_DLY_EN_START_BIT)
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#define AW_PID_2013_RSQN_DLY_EN_12NS (1)
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#define AW_PID_2013_RSQN_DLY_EN_12NS_VALUE \
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(AW_PID_2013_RSQN_DLY_EN_12NS << AW_PID_2013_RSQN_DLY_EN_START_BIT)
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#define AW_PID_2013_RSQN_DLY_EN_DEFAULT_VALUE (0)
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#define AW_PID_2013_RSQN_DLY_EN_DEFAULT \
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(AW_PID_2013_RSQN_DLY_EN_DEFAULT_VALUE << AW_PID_2013_RSQN_DLY_EN_START_BIT)
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/* BST_MODE bit 5:4 (BSTCTRL2 0x61) */
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#define AW_PID_2013_BST_MODE_START_BIT (4)
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#define AW_PID_2013_BST_MODE_BITS_LEN (2)
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#define AW_PID_2013_BST_MODE_MASK \
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(~(((1<<AW_PID_2013_BST_MODE_BITS_LEN)-1) << AW_PID_2013_BST_MODE_START_BIT))
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#define AW_PID_2013_BST_MODE_TRANSPARENT (0)
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#define AW_PID_2013_BST_MODE_TRANSPARENT_VALUE \
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(AW_PID_2013_BST_MODE_TRANSPARENT << AW_PID_2013_BST_MODE_START_BIT)
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#define AW_PID_2013_BST_MODE_FORCE_BOOST (1)
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#define AW_PID_2013_BST_MODE_FORCE_BOOST_VALUE \
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(AW_PID_2013_BST_MODE_FORCE_BOOST << AW_PID_2013_BST_MODE_START_BIT)
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#define AW_PID_2013_BST_MODE_CLASS_G (2)
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#define AW_PID_2013_BST_MODE_CLASS_G_VALUE \
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(AW_PID_2013_BST_MODE_CLASS_G << AW_PID_2013_BST_MODE_START_BIT)
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#define AW_PID_2013_BST_MODE_CLASS_H (3)
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#define AW_PID_2013_BST_MODE_CLASS_H_VALUE \
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(AW_PID_2013_BST_MODE_CLASS_H << AW_PID_2013_BST_MODE_START_BIT)
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#define AW_PID_2013_BST_MODE_DEFAULT_VALUE (0x3)
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#define AW_PID_2013_BST_MODE_DEFAULT \
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(AW_PID_2013_BST_MODE_DEFAULT_VALUE << AW_PID_2013_BST_MODE_START_BIT)
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/* VOUT_VREFSET bit 3:0 (BSTCTRL2 0x61) */
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#define AW_PID_2013_VOUT_VREFSET_START_BIT (0)
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#define AW_PID_2013_VOUT_VREFSET_BITS_LEN (4)
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#define AW_PID_2013_VOUT_VREFSET_MASK \
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(~(((1<<AW_PID_2013_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2013_VOUT_VREFSET_START_BIT))
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#define AW_PID_2013_VOUT_VREFSET_3P25V (0)
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#define AW_PID_2013_VOUT_VREFSET_3P25V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_3P25V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_3P50V (1)
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#define AW_PID_2013_VOUT_VREFSET_3P50V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_3P50V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_3P75V (2)
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#define AW_PID_2013_VOUT_VREFSET_3P75V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_3P75V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_4P00V (3)
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#define AW_PID_2013_VOUT_VREFSET_4P00V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_4P00V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_4P25V (4)
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#define AW_PID_2013_VOUT_VREFSET_4P25V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_4P25V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_4P50V (5)
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#define AW_PID_2013_VOUT_VREFSET_4P50V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_4P50V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_4P75V (6)
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#define AW_PID_2013_VOUT_VREFSET_4P75V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_4P75V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_5P00V (7)
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#define AW_PID_2013_VOUT_VREFSET_5P00V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_5P00V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_5P25V (8)
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#define AW_PID_2013_VOUT_VREFSET_5P25V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_5P25V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_5P50V (9)
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#define AW_PID_2013_VOUT_VREFSET_5P50V_VALUE \
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(AW_PID_2013_VOUT_VREFSET_5P50V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_5P75V (10)
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#define AW_PID_2013_VOUT_VREFSET_5P75V_VALUE \
|
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(AW_PID_2013_VOUT_VREFSET_5P75V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_6P00V (11)
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#define AW_PID_2013_VOUT_VREFSET_6P00V_VALUE \
|
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(AW_PID_2013_VOUT_VREFSET_6P00V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_6P25V (12)
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|
#define AW_PID_2013_VOUT_VREFSET_6P25V_VALUE \
|
|
(AW_PID_2013_VOUT_VREFSET_6P25V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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#define AW_PID_2013_VOUT_VREFSET_6P50V (13)
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#define AW_PID_2013_VOUT_VREFSET_6P50V_VALUE \
|
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(AW_PID_2013_VOUT_VREFSET_6P50V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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|
|
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#define AW_PID_2013_VOUT_VREFSET_6P75V (14)
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#define AW_PID_2013_VOUT_VREFSET_6P75V_VALUE \
|
|
(AW_PID_2013_VOUT_VREFSET_6P75V << AW_PID_2013_VOUT_VREFSET_START_BIT)
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|
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#define AW_PID_2013_VOUT_VREFSET_7P00V (15)
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|
#define AW_PID_2013_VOUT_VREFSET_7P00V_VALUE \
|
|
(AW_PID_2013_VOUT_VREFSET_7P00V << AW_PID_2013_VOUT_VREFSET_START_BIT)
|
|
|
|
#define AW_PID_2013_VOUT_VREFSET_DEFAULT_VALUE (0xB)
|
|
#define AW_PID_2013_VOUT_VREFSET_DEFAULT \
|
|
(AW_PID_2013_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2013_VOUT_VREFSET_START_BIT)
|
|
|
|
/* default value of BSTCTRL2 (0x61) */
|
|
/* #define AW_PID_2013_BSTCTRL2_DEFAULT (0x6B3B) */
|
|
|
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/* EF_ISN_GESLP bit 9:0 (EFRH 0x78) */
|
|
#define AW_PID_2013_EF_ISN_GESLP_START_BIT (0)
|
|
#define AW_PID_2013_EF_ISN_GESLP_BITS_LEN (10)
|
|
#define AW_PID_2013_EF_ISN_GESLP_MASK \
|
|
(~(((1<<AW_PID_2013_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2013_EF_ISN_GESLP_START_BIT))
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|
|
|
/* EF_VSN_GESLP bit 9:0 (EFRM2 0x79) */
|
|
#define AW_PID_2013_EF_VSN_GESLP_START_BIT (0)
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|
#define AW_PID_2013_EF_VSN_GESLP_BITS_LEN (10)
|
|
#define AW_PID_2013_EF_VSN_GESLP_MASK \
|
|
(~(((1<<AW_PID_2013_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2013_EF_VSN_GESLP_START_BIT))
|
|
|
|
/* detail information of registers end */
|
|
#define AW_PID_2013_EFVER_CHECK (0x0007)
|
|
#define AW_PID_2013_EFVERH_START_BIT (13)
|
|
#define AW_PID_2013_EFVERL_START_BIT (10)
|
|
|
|
#define AW_PID_2013_EFVERH_MASK (~(7 << 13))
|
|
#define AW_PID_2013_EFVERL_MASK (~(7 << 10))
|
|
/********************************************
|
|
* Volume Coefficient
|
|
*******************************************/
|
|
#define AW_PID_2013_VOL_STEP (6 * 8)
|
|
|
|
/********************************************
|
|
* Vcalb
|
|
*******************************************/
|
|
#define AW_PID_2013_EF_ISN_GESLP2_SIGN_MASK (~0x0200)
|
|
#define AW_PID_2013_EF_ISN_GESLP2_NEG (~0xFC00)
|
|
|
|
#define AW_PID_2013_EF_ISN_GESLP_SIGN_MASK (~0x0200)
|
|
#define AW_PID_2013_EF_ISN_GESLP_NEG (~0xFC00)
|
|
|
|
#define AW_PID_2013_CABL_BASE_VALUE (1000)
|
|
#define AW_PID_2013_ICABLK_FACTOR (1)
|
|
#define AW_PID_2013_VCABLK_FACTOR (1)
|
|
|
|
#define AW_PID_2013_VCAL_FACTOR (1<<13)
|
|
|
|
#define AW_PID_2013_MONITOR_VBAT_RANGE (6025)
|
|
#define AW_PID_2013_MONITOR_INT_10BIT (1023)
|
|
#define AW_PID_2013_MONITOR_TEMP_SIGN_MASK (~(1<<9))
|
|
#define AW_PID_2013_MONITOR_TEMP_NEG_MASK (0XFC00)
|
|
|
|
/********************************************
|
|
* Dither
|
|
*******************************************/
|
|
#define AW_PID_2013_DITHER_START_BIT (14)
|
|
#define AW_PID_2013_DITHER_BITS_LEN (1)
|
|
#define AW_PID_2013_DITHER_MASK \
|
|
(~(((1<<AW_PID_2013_DITHER_BITS_LEN)-1) << AW_PID_2013_DITHER_START_BIT))
|
|
|
|
#define AW_PID_2013_DITHER_DISABLE (0)
|
|
#define AW_PID_2013_DITHER_DISABLE_VALUE \
|
|
(AW_PID_2013_DITHER_DISABLE << AW_PID_2013_DITHER_START_BIT)
|
|
|
|
#define AW_PID_2013_DITHER_ENABLE (1)
|
|
#define AW_PID_2013_DITHER_ENABLE_VALUE \
|
|
(AW_PID_2013_DITHER_ENABLE << AW_PID_2013_DITHER_START_BIT)
|
|
|
|
#endif /* #ifndef __AW_PID_2013_REG_H__ */
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