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https://github.com/physwizz/a155-U-u1.git
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84 lines
1.6 KiB
C
84 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRAMC_H__
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#define __DRAMC_H__
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struct mr_info_t {
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unsigned int mr_index;
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unsigned int mr_value;
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};
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struct reg_ctrl_t {
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unsigned int offset;
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unsigned int mask;
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unsigned int shift;
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};
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struct fmeter_dev_t {
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unsigned int version;
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unsigned int crystal_freq;
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unsigned int shu_of;
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struct reg_ctrl_t shu_lv;
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struct reg_ctrl_t pll_id;
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struct reg_ctrl_t pll_md[2];
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struct reg_ctrl_t sdmpcw[2];
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struct reg_ctrl_t prediv[2];
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struct reg_ctrl_t posdiv[2];
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struct reg_ctrl_t ckdiv4[2];
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struct reg_ctrl_t cldiv2[2];
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struct reg_ctrl_t fbksel[2];
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struct reg_ctrl_t dqopen[2];
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struct reg_ctrl_t dqsopen[2];
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struct reg_ctrl_t ckdiv4_ca[2];
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};
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struct mr4_dev_t {
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unsigned int version;
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struct reg_ctrl_t mr4_rg;
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};
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struct dramc_dev_t {
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unsigned int dram_type;
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unsigned int support_ch_cnt;
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unsigned int ch_cnt;
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unsigned int rk_cnt;
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unsigned int mr_cnt;
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unsigned int freq_cnt;
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unsigned int *rk_size;
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unsigned int *freq_step;
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struct mr_info_t *mr_info_ptr;
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void __iomem **dramc_chn_base_ao;
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void __iomem **dramc_chn_base_nao;
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void __iomem **ddrphy_chn_base_ao;
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void __iomem **ddrphy_chn_base_nao;
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void __iomem *sleep_base;
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void *mr4_dev_ptr;
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void *fmeter_dev_ptr;
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};
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enum DRAM_TYPE {
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TYPE_DDR1 = 1,
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TYPE_LPDDR2,
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TYPE_LPDDR3,
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TYPE_PCDDR3,
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TYPE_LPDDR4,
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TYPE_LPDDR4X,
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TYPE_LPDDR4P,
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TYPE_LPDDR5,
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TYPE_LPDDR5X
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};
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#define DPM_IRQ_CHA 0
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#define DPM_IRQ_CHB 1
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int mtk_dramc_get_steps_freq(unsigned int step);
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unsigned int mtk_dramc_get_ddr_type(void);
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unsigned int mtk_dramc_get_data_rate(void);
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unsigned int mtk_dramc_get_mr4(unsigned int ch);
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#endif /* __DRAMC_H__ */
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