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https://github.com/physwizz/a155-U-u1.git
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255 lines
7.1 KiB
C
255 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MediaTek Controls Header
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*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Yunfei Dong <yunfei.dong@mediatek.com>
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*/
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#ifndef __MTK_VCU_CONTROLS_H__
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#define __MTK_VCU_CONTROLS_H__
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/compat.h>
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#define SHARE_BUF_SIZE 80
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#define LOG_INFO_SIZE 1024
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#define VCODEC_CMDQ_CMD_MAX (2048)
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/**
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* struct mem_obj - memory buffer allocated in kernel
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*
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* @iova: iova of buffer
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* @len: buffer length
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* @pa: physical address
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* @va: kernel virtual address
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*/
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struct mem_obj {
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uint64_t iova;
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uint32_t len;
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uint64_t pa;
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uint64_t va;
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};
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/**
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* struct map_obj - memory buffer mmaped in kernel
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*
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* @map_buf: iova of buffer
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* 0: not mapped buf; 1: mapped buf
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* @map_type: the type of mmap
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* 0: reserved; 1: MM_BASE;
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* 2: MM_CACHEABLE_BASE; 3: PA_BASE
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* @reserved: reserved
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*/
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struct map_obj {
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uint32_t map_buf;
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uint32_t map_type;
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uint64_t reserved;
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};
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/**
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* struct gce_cmds - cmds buffer
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*
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* @cmd: gce cmd
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* @addr: cmd operation addr
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* @data: cmd operation data
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* @mask: cmd operation mask
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* @cmd_cnt: cmdq total cmd count
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*/
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struct gce_cmds {
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uint8_t cmd[VCODEC_CMDQ_CMD_MAX];
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uint64_t addr[VCODEC_CMDQ_CMD_MAX];
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uint64_t data[VCODEC_CMDQ_CMD_MAX];
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uint32_t mask[VCODEC_CMDQ_CMD_MAX];
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uint32_t dma_offset[VCODEC_CMDQ_CMD_MAX];
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uint32_t dma_size[VCODEC_CMDQ_CMD_MAX];
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uint32_t cmd_cnt;
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};
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/**
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* struct gce_cmdq_obj - cmdQ buffer allocated in kernel
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*
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* @cmds_user_ptr: user pointer to struct gce_cmds
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* @gce_handle: instance handle
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* @flush_order: cmdQ buffer order
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* @codec_type: decoder(1) or encoder(0)
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*/
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struct gce_cmdq_obj {
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uint64_t cmds_user_ptr;
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uint64_t gce_handle;
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uint32_t flush_order;
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uint32_t codec_type;
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uint32_t core_id;
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uint32_t secure;
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};
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/**
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* struct gce_obj - gce allocated in kernel
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* @gce_handle: instance handle
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* @flush_order: cmdQ buffer order
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* @codec_type: decoder(1) or encoder(0)
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*/
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struct gce_obj {
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uint64_t gce_handle;
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uint32_t flush_order;
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uint32_t codec_type;
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};
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struct disp_iova_obj {
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uint32_t mapped_iova;
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};
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enum gce_cmd_id {
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CMD_READ = 0, /* read register */
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CMD_WRITE, /* write register */
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CMD_POLL_REG,
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/* polling register until get some value (no timeout, blocking wait) */
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CMD_WAIT_EVENT, /* gce wait HW done event & clear */
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CMD_MEM_MV, /* copy memory data from PA to another PA */
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CMD_POLL_ADDR,
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/* polling addr until get some value (with timeout) */
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CMD_SEC_WRITE, /* sec dma write register */
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CMD_MAX
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};
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enum gce_event_id {
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VDEC_EVENT_0, /* pic_start (each spec trigger decode will get) */
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VDEC_EVENT_1, /* decode done, VDEC_TOP(41) bit16=1 */
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VDEC_EVENT_2, /* vdec_pause (WDMA(9)bit0 or bit1=1) */
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VDEC_EVENT_3, /* vdec_dec_error (each spec. decode error will get) */
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VDEC_EVENT_4,
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/* mc_busy_overflow | mdec_timeout
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* (decode to VLD_TOP(20) or VLD_TOP(22) will get)
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*/
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VDEC_EVENT_5,
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/* all_dram_req & all_dram_cnt_0 & bits_proc_nop_1
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* & bits_proc_nop_2, break or pic_finish need wait
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*/
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VDEC_EVENT_6, /* ini_fetch_rdy VLD(58)bit0=1 */
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VDEC_EVENT_7,
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/* process_flag VLD(61)bit15=0 ||
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* VLD(61)bit15=1 && VLD(61)bit0=0
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*/
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VDEC_EVENT_8,
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/* "search_start_code_done HEVC_VLD(37)bit8=0"
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* "search_start_code_doneAVC_VLD(182)bit0=0"
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* "ctx_count_dma_rdyVP9_VLD(170)bit0=1"
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*/
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VDEC_EVENT_9,
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/* "ref_reorder_doneHEVC_VLD(37)bit4=0"
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* "ref_reorder_doneAVC_VLD(139)bit0=1"
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* "& update_probs_rdy& VP9_VLD(51) = 1"
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*/
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VDEC_EVENT_10,
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/* "wp_tble_doneHEVC_VLD(37)bit0=0"
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* "wp_tble_doneAVC_VLD(140)bit0=1"
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* "bool_init_rdyVP9_VLD(68)bit16 = 1"
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*/
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VDEC_EVENT_11,
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/* "count_sram_clr_done &
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* ctx_sram_clr_doneVP9_VLD(106)bit0 =0 &
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* VP9_VLD(166)bit0 = 0"
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*/
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VDEC_EVENT_12, /* reserved */
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VDEC_EVENT_13, /* reserved */
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VDEC_EVENT_14, /* reserved */
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VDEC_EVENT_15, /* Queue Counter OP threshold */
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VDEC_LAT_EVENT_0,
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VDEC_LAT_EVENT_1,
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VDEC_LAT_EVENT_2,
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VDEC_LAT_EVENT_3,
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VDEC_LAT_EVENT_4,
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VDEC_LAT_EVENT_5,
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VDEC_LAT_EVENT_6,
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VDEC_LAT_EVENT_7,
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VDEC_LAT_EVENT_8,
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VDEC_LAT_EVENT_9,
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VDEC_LAT_EVENT_10,
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VDEC_LAT_EVENT_11,
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VDEC_LAT_EVENT_12,
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VDEC_LAT_EVENT_13,
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VDEC_LAT_EVENT_14,
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VDEC_LAT_EVENT_15,
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VDEC_EVENT_COUNT,
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VENC_EOF = VDEC_EVENT_COUNT,
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VENC_CMDQ_PAUSE_DONE,
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VENC_MB_DONE,
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VENC_128BYTE_CNT_DONE,
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VENC_EOF_C1,
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VENC_WP_2ND_DONE,
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VENC_WP_3ND_DONE,
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VENC_SPS_DONE,
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VENC_PPS_DONE
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};
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#define VCU_SET_OBJECT _IOW('v', 0, struct share_obj)
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#define VCU_MVA_ALLOCATION _IOWR('v', 1, struct mem_obj)
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#define VCU_MVA_FREE _IOWR('v', 2, struct mem_obj)
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#define VCU_CACHE_FLUSH_ALL _IOWR('v', 3, struct mem_obj)
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#define VCU_CACHE_FLUSH_BUFF _IOWR('v', 4, struct mem_obj)
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#define VCU_CACHE_INVALIDATE_BUFF _IOWR('v', 5, struct mem_obj)
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#define VCU_PA_ALLOCATION _IOWR('v', 6, struct mem_obj)
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#define VCU_PA_FREE _IOWR('v', 7, struct mem_obj)
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#define VCU_GCE_SET_CMD_FLUSH _IOW('v', 8, struct gce_cmdq_obj)
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#define VCU_GCE_WAIT_CALLBACK _IOW('v', 9, struct gce_obj)
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#define VCU_GET_OBJECT _IOWR('v', 10, struct share_obj)
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#define VCU_GET_LOG_OBJECT _IOW('v', 11, struct log_test_nofuse)
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#define VCU_SET_LOG_OBJECT _IOW('v', 12, struct log_test)
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#define VCU_SET_MMAP_TYPE _IOW('v', 13, struct map_obj)
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#define VCU_GET_DISP_MAPPED_IOVA _IOWR('v', 14, struct disp_iova_obj)
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#define VCU_CLEAR_DISP_MAPPED_IOVA _IOW('v', 15, struct disp_iova_obj)
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#define VCU_GET_DISP_WDMA_Y_ADDR _IOWR('v', 16, struct disp_iova_obj)
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#define VCU_UBE_MVA_ALLOCATION _IOWR('v', 17, struct mem_obj)
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#define VCU_UBE_MVA_FREE _IOWR('v', 18, struct mem_obj)
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#define VCU_SECURE_HANDLE_ALLOCATION _IOWR('v', 19, struct mem_obj)
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#define VCU_SECURE_HANDLE_FREE _IOWR('v', 20, struct mem_obj)
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#define VCU_SECURE_BUFFER_ALLOCATION _IOWR('v', 21, struct mem_obj)
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#define VCU_SECURE_BUFFER_FREE _IOWR('v', 22, struct mem_obj)
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#define COMPAT_VCU_SET_OBJECT _IOW('v', 0, struct share_obj)
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#define COMPAT_VCU_MVA_ALLOCATION _IOWR('v', 1, struct compat_mem_obj)
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#define COMPAT_VCU_MVA_FREE _IOWR('v', 2, struct compat_mem_obj)
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#define COMPAT_VCU_CACHE_FLUSH_ALL _IOWR('v', 3, struct compat_mem_obj)
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#define COMPAT_VCU_CACHE_FLUSH_BUFF _IOWR('v', 4, struct compat_mem_obj)
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#define COMPAT_VCU_CACHE_INVALIDATE_BUFF _IOWR('v', 5, struct compat_mem_obj)
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#define COMPAT_VCU_PA_ALLOCATION _IOWR('v', 6, struct compat_mem_obj)
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#define COMPAT_VCU_PA_FREE _IOWR('v', 7, struct compat_mem_obj)
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#define COMPAT_VCU_SET_MMAP_TYPE _IOW('v', 13, struct map_obj)
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#define COMPAT_VCU_UBE_MVA_ALLOCATION _IOWR('v', 17, struct compat_mem_obj)
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#define COMPAT_VCU_UBE_MVA_FREE _IOWR('v', 18, struct compat_mem_obj)
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#define COMPAT_VCU_SECURE_HANDLE_ALLOCATION _IOWR('v', 19, struct mem_obj)
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#define COMPAT_VCU_SECURE_HANDLE_FREE _IOWR('v', 20, struct mem_obj)
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#define COMPAT_VCU_SECURE_BUFFER_ALLOCATION _IOWR('v', 21, struct mem_obj)
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#define COMPAT_VCU_SECURE_BUFFER_FREE _IOWR('v', 22, struct mem_obj)
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struct compat_mem_obj {
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uint64_t iova;
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uint32_t len;
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compat_u64 pa;
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compat_u64 va;
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};
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/**
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* struct share_obj - DTCM (Data Tightly-Coupled Memory) buffer shared with
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* AP and VCU
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*
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* @id: IPI id
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* @len: share buffer length
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* @share_buf: share buffer data
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*/
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struct share_obj {
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int32_t id;
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uint32_t len;
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unsigned char share_buf[SHARE_BUF_SIZE];
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};
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struct log_test_nofuse {
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char log_info[LOG_INFO_SIZE];
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};
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#endif
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