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https://github.com/physwizz/a155-U-u1.git
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263 lines
8.0 KiB
C
263 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __MT6685_RTC_H__
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#define __MT6685_RTC_H__
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#include <linux/mfd/mt6685/registers.h>
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/*features*/
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#define SUPPORT_EOSC_CALI
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#define SUPPORT_PWR_OFF_ALARM
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/* we map HW YEA 0 (2000) to 1968 not 1970 because 2000 is the leap year */
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#define RTC_MIN_YEAR 1968
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#define RTC_BASE_YEAR 1900
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#define RTC_NUM_YEARS 128
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#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
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#define RTC_TC_SEC 0x12
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#define RTC_TC_MIN 0x14
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#define RTC_TC_HOU 0x16
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#define RTC_TC_DOM 0x18
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#define RTC_TC_DOW 0x1A
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#define RTC_TC_MTH 0x1C
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#define RTC_TC_YEA 0x1E
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/* Min, Hour, Dom... register offset to RTC_TC_SEC */
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#define RTC_OFFSET_SEC 0
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#define RTC_OFFSET_MIN 1
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#define RTC_OFFSET_HOUR 2
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#define RTC_OFFSET_DOM 3
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#define RTC_OFFSET_DOW 4
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#define RTC_OFFSET_MTH 5
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#define RTC_OFFSET_YEAR 6
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#define RTC_OFFSET_COUNT 7
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#define RTC_DSN_ID 0x580
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#define DCXO_ANA_ID 0x200
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#define RTC_BBPU 0x8
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#define RTC_WRTGR_MT6685 0x42
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#define RTC_IRQ_STA 0xa
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#define RTC_IRQ_EN 0xc
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#define RTC_AL_MASK 0x10
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#define RTC_AL_SEC 0x20
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#define RTC_AL_MIN 0x22
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#define RTC_AL_HOU 0x24
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#define RTC_AL_HOU_H 0x25
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#define RTC_AL_DOM 0x26
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#define RTC_AL_DOW 0x28
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#define RTC_AL_DOW_H 0x29
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#define RTC_AL_MTH 0x2a
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#define RTC_AL_MTH_H 0x2b
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#define RTC_AL_YEA 0x2c
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#define RTC_AL_YEA_H 0x2d
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#define RTC_OSC32CON 0x2e
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#define RTC_POWERKEY1 0x30
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#define RTC_POWERKEY2 0x32
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#define RTC_PDN1 0x34
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#define RTC_PDN1_H 0x35
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#define RTC_PDN2 0x36
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#define RTC_SPAR0 0x38
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#define RTC_SPAR1 0x3a
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#define RTC_PROT 0x3c
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#define RTC_WRTGR 0x42
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#define RTC_CON 0x44
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#define RTC_INT_CNT_L 0x48
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#define RTC_TC_SEC_MASK 0x3f
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#define RTC_TC_MIN_MASK 0x3f
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#define RTC_TC_HOU_MASK 0x1f
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#define RTC_TC_DOM_MASK 0x1f
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#define RTC_TC_DOW_MASK 0x7
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#define RTC_TC_MTH_MASK 0xf
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#define RTC_TC_YEA_MASK 0x7f
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#define RTC_AL_SEC_MASK 0x3f
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#define RTC_AL_MIN_MASK 0x3f
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#define RTC_AL_HOU_MASK 0x1f
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#define RTC_AL_DOM_MASK 0x1f
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#define RTC_AL_DOW_MASK 0x7
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#define RTC_AL_MTH_MASK 0xf
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#define RTC_AL_YEA_MASK 0x7f
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#define RTC_PWRON_YEA RTC_PDN2
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#define RTC_PWRON_MTH RTC_PDN2
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#define RTC_PWRON_SEC RTC_SPAR0
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#define RTC_PWRON_MIN RTC_SPAR1
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#define RTC_PWRON_HOU RTC_SPAR1
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#define RTC_PWRON_DOM RTC_SPAR1
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#define RTC_PWRON_SEC_SHIFT 0x0
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#define RTC_PWRON_MIN_SHIFT 0x0
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#define RTC_PWRON_HOU_SHIFT 0x6
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#define RTC_PWRON_DOM_SHIFT 0xb
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#define RTC_PWRON_MTH_SHIFT 0x0
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#define RTC_PWRON_YEA_SHIFT 0x8
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#define RTC_PWRON_SEC_MASK (RTC_AL_SEC_MASK << RTC_PWRON_SEC_SHIFT)
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#define RTC_PWRON_MIN_MASK (RTC_AL_MIN_MASK << RTC_PWRON_MIN_SHIFT)
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#define RTC_PWRON_HOU_MASK (RTC_AL_HOU_MASK << RTC_PWRON_HOU_SHIFT)
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#define RTC_PWRON_DOM_MASK (RTC_AL_DOM_MASK << RTC_PWRON_DOM_SHIFT)
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#define RTC_PWRON_MTH_MASK (RTC_AL_MTH_MASK << RTC_PWRON_MTH_SHIFT)
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#define RTC_PWRON_YEA_MASK (RTC_AL_YEA_MASK << RTC_PWRON_YEA_SHIFT)
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#define RTC_BBPU_KEY 0x4300
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#define RTC_BBPU_CBUSY BIT(6)
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#define RTC_BBPU_RELOAD BIT(5)
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#define RTC_BBPU_AUTO BIT(3)
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#define RTC_BBPU_CLR BIT(1)
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#define RTC_BBPU_PWREN BIT(0)
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#define RTC_BBPU_AL_STA BIT(7)
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#define RTC_BBPU_RESET_AL BIT(3)
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#define RTC_BBPU_RESET_SPAR BIT(2)
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#define RTC_AL_MASK_DOW BIT(4)
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#define RTC_IRQ_EN_LP BIT(3)
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#define RTC_IRQ_EN_ONESHOT BIT(2)
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#define RTC_IRQ_EN_AL BIT(0)
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#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
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#define RTC_IRQ_STA_LP BIT(3)
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#define RTC_IRQ_STA_AL BIT(0)
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#define RTC_PDN1_PWRON_TIME BIT(7)
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#define RTC_PDN2_PWRON_LOGO BIT(15)
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#define RTC_PDN2_PWRON_ALARM BIT(4)
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#define RTC_RG_FG2 0x54
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#define RTC_RG_FG3 0x56
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#define TOP_RTC_EOSC32_CK_PDN MT6685_SCK_TOP_CKPDN_CON0_L
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#define TOP_RTC_EOSC32_CK_PDN_MASK (MT6685_RG_RTC_EOSC32_CK_PDN_MASK \
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<< MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT)
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#define EOSC_CALI_TD RTC_AL_DOW_H
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#define EOSC_CALI_TD_MASK MT6685_RG_EOSC_CALI_TD_MASK
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#define TOP_DIG_WPK MT6685_TOP_DIG_WPK
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#define DIG_WPK_KEY_MASK (MT6685_DIG_WPK_KEY_MASK << MT6685_DIG_WPK_KEY_SHIFT)
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#define TOP_DIG_WPK_H MT6685_TOP_DIG_WPK_H
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#define DIG_WPK_KEY_H_MASK (MT6685_DIG_WPK_KEY_H_MASK << MT6685_DIG_WPK_KEY_H_SHIFT)
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#define RG_RTC_MCLK_PDN_SET MT6685_SCK_TOP_CKPDN_CON0_L_SET
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#define RG_RTC_MCLK_PDN_CLR MT6685_SCK_TOP_CKPDN_CON0_L_CLR
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#define RG_RTC_MCLK_PDN_MASK (MT6685_RG_RTC_MCLK_PDN_MASK << MT6685_RG_RTC_MCLK_PDN_SHIFT)
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/*SCK_TOP rtc interrupt*/
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#define SCK_TOP_INT_CON0 MT6685_SCK_TOP_INT_CON0
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#define EN_RTC_INTERRUPT MT6685_RG_INT_EN_RTC_MASK
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#define SCK_TOP_INT_STATUS0 MT6685_SCK_TOP_INT_STATUS0
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#define TOP2_ELR1 MT6685_TOP2_ELR1
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#define MTK_RTC_POLL_DELAY_US 10
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#define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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#define RTC_POFF_ALM_SET _IOW('p', 0x15, struct rtc_time) /* Set alarm time */
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#define SPARE_REG_WIDTH 1
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enum mtk_rtc_spare_enum {
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SPARE_FG2,
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SPARE_FG3,
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SPARE_SPAR0,
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#ifdef SUPPORT_PWR_OFF_ALARM
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SPARE_KPOC,
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#endif
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SPARE_RG_MAX,
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};
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enum rtc_irq_sta {
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RTC_NONE,
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RTC_ALSTA,
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RTC_TCSTA,
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RTC_LPSTA,
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};
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enum rtc_reg_set {
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RTC_REG,
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RTC_MASK,
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RTC_SHIFT
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};
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enum unlock_version {
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UNLOCK_MT6685_SERIES,
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};
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#ifdef SUPPORT_EOSC_CALI
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#define EOSC_SOL_1 0x5
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#define EOSC_SOL_2 0x7
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enum rtc_eosc_cali_td {
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EOSC_CALI_TD_01_SEC = 0x3,
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EOSC_CALI_TD_02_SEC,
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EOSC_CALI_TD_04_SEC,
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EOSC_CALI_TD_08_SEC,
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EOSC_CALI_TD_16_SEC,
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};
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#endif
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#ifdef SUPPORT_PWR_OFF_ALARM
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struct tag_bootmode {
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u32 size;
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u32 tag;
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u32 bootmode;
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u32 boottype;
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};
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enum boot_mode_t {
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NORMAL_BOOT = 0,
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META_BOOT = 1,
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RECOVERY_BOOT = 2,
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SW_REBOOT = 3,
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FACTORY_BOOT = 4,
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ADVMETA_BOOT = 5,
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ATE_FACTORY_BOOT = 6,
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ALARM_BOOT = 7,
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KERNEL_POWER_OFF_CHARGING_BOOT = 8,
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LOW_POWER_OFF_CHARGING_BOOT = 9,
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DONGLE_BOOT = 10,
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UNKNOWN_BOOT
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};
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#endif
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struct mtk_rtc_data {
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u32 wrtgr;
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u32 unlock_version;
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};
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struct mt6685_rtc {
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struct rtc_device *rtc_dev;
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/* Protect register access from multiple tasks */
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struct mutex lock;
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struct mutex clk_lock;
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struct regmap *regmap;
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struct regmap *regmap_spar;
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int irq;
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u32 addr_base;
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const struct mtk_rtc_data *data;
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#ifdef SUPPORT_EOSC_CALI
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bool cali_is_supported;
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#endif
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#ifdef SUPPORT_PWR_OFF_ALARM
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struct work_struct work;
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struct completion comp;
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#if IS_ENABLED(CONFIG_PM)
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struct notifier_block pm_nb;
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#endif
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#endif
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};
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#endif /* __MT6685_RTC_H__ */
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