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270 lines
6.3 KiB
C
270 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2014-2019 MediaTek Inc.
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*
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* Author: Tianping.Fang <tianping.fang@mediatek.com>
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* Sean Wang <sean.wang@mediatek.com>
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*/
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#ifndef _LINUX_MFD_MT6397_RTC_H_
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#define _LINUX_MFD_MT6397_RTC_H_
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#include <linux/jiffies.h>
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#include <linux/mutex.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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/*features*/
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#define SUPPORT_EOSC_CALI
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#define SUPPORT_PWR_OFF_ALARM
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#define RTC_BBPU 0x0000
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#define RTC_BBPU_PWREN BIT(0)
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#define RTC_BBPU_CLR BIT(1)
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#define RTC_BBPU_RESET_AL BIT(3)
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#define RTC_BBPU_RELOAD BIT(5)
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#define RTC_BBPU_CBUSY BIT(6)
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#define RTC_BBPU_KEY (0x43 << 8)
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#define RTC_WRTGR_MT6358 0x003a
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#define RTC_WRTGR_MT6397 0x003c
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#define RTC_WRTGR_MT6323 RTC_WRTGR_MT6397
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#define RTC_IRQ_STA 0x0002
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#define RTC_IRQ_STA_AL BIT(0)
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#define RTC_IRQ_STA_LP BIT(3)
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#define RTC_IRQ_EN 0x0004
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#define RTC_IRQ_EN_AL BIT(0)
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#define RTC_IRQ_EN_ONESHOT BIT(2)
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#define RTC_IRQ_EN_LP BIT(3)
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#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
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#define RTC_AL_MASK 0x0008
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#define RTC_AL_MASK_DOW BIT(4)
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#define RTC_TC_SEC 0x000a
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/* Min, Hour, Dom... register offset to RTC_TC_SEC */
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#define RTC_OFFSET_SEC 0
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#define RTC_OFFSET_MIN 1
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#define RTC_OFFSET_HOUR 2
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#define RTC_OFFSET_DOM 3
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#define RTC_OFFSET_DOW 4
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#define RTC_OFFSET_MTH 5
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#define RTC_OFFSET_YEAR 6
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#define RTC_OFFSET_COUNT 7
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#define RTC_TC_SEC_MASK 0x003f
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#define RTC_TC_MIN_MASK 0x003f
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#define RTC_TC_HOU_MASK 0x001f
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#define RTC_TC_DOM_MASK 0x001f
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#define RTC_TC_DOW_MASK 0x0007
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#define RTC_TC_MTH_MASK 0x000f
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#define RTC_TC_YEA_MASK 0x007f
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#define RTC_AL_SEC 0x0018
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#define RTC_AL_HOU 0x001c
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#define RTC_AL_DOW 0x0020
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#define RTC_AL_MTH 0x0022
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#define RTC_AL_YEA 0x0024
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#define RTC_AL_SEC_MASK 0x003f
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#define RTC_AL_MIN_MASK 0x003f
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#define RTC_AL_HOU_MASK 0x001f
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#define RTC_AL_DOM_MASK 0x001f
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#define RTC_AL_DOW_MASK 0x0007
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#define RTC_AL_MTH_MASK 0x000f
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#define RTC_AL_YEA_MASK 0x007f
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#define RTC_PDN1 0x002c
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#define RTC_PDN1_PWRON_TIME BIT(7)
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#define RTC_PDN2 0x002e
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#define RTC_PDN2_PWRON_ALARM BIT(4)
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#define RTC_SPAR0 0x0030
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#define RTC_SPAR1 0x0032
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#define RTC_MIN_YEAR 1968
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#define RTC_BASE_YEAR 1900
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#define RTC_NUM_YEARS 128
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#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
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#define RTC_PWRON_YEA RTC_PDN2
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#define RTC_PWRON_YEA_MASK 0x7f00
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#define RTC_PWRON_YEA_SHIFT 8
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#define RTC_PWRON_MTH RTC_PDN2
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#define RTC_PWRON_MTH_MASK 0x000f
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#define RTC_PWRON_MTH_SHIFT 0
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#define RTC_PWRON_SEC RTC_SPAR0
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#define RTC_PWRON_SEC_MASK 0x003f
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#define RTC_PWRON_SEC_SHIFT 0
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#define RTC_PWRON_MIN RTC_SPAR1
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#define RTC_PWRON_MIN_MASK 0x003f
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#define RTC_PWRON_MIN_SHIFT 0
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#define RTC_PWRON_HOU RTC_SPAR1
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#define RTC_PWRON_HOU_MASK 0x07c0
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#define RTC_PWRON_HOU_SHIFT 6
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#define RTC_PWRON_DOM RTC_SPAR1
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#define RTC_PWRON_DOM_MASK 0xf800
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#define RTC_PWRON_DOM_SHIFT 11
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#define SPARE_REG_WIDTH 1
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#define MTK_RTC_POLL_DELAY_US 10
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#define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ))
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#define RTC_POFF_ALM_SET _IOW('p', 0x15, struct rtc_time) /* Set alarm time */
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#define RTC_OSC32CON 0x0026
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#define RTC_POWERKEY1 0x0028
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#define RTC_POWERKEY2 0x002a
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#define RTC_PROT 0x0034
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#define RTC_CON 0x003c
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enum mtk_rtc_spare_enum {
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SPARE_AL_HOU,
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SPARE_AL_MTH,
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SPARE_SPAR0,
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#ifdef SUPPORT_PWR_OFF_ALARM
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SPARE_KPOC,
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#endif
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SPARE_RG_MAX,
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};
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enum rtc_reg_set {
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RTC_REG,
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RTC_MASK,
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RTC_SHIFT
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};
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enum rtc_irq_sta {
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RTC_NONE,
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RTC_ALSTA,
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RTC_TCSTA,
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RTC_LPSTA,
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};
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#ifdef SUPPORT_EOSC_CALI
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#define EOSC_SOL_1 0x5
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#define EOSC_SOL_2 0x7
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enum rtc_eosc_cali_td {
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EOSC_CALI_TD_01_SEC = 0x3,
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EOSC_CALI_TD_02_SEC,
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EOSC_CALI_TD_04_SEC,
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EOSC_CALI_TD_08_SEC,
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EOSC_CALI_TD_16_SEC,
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};
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enum cali_field_enum {
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RTC_EOSC32_CK_PDN,
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EOSC_CALI_TD,
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RTC_K_EOSC_RSV,
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CALI_FILED_MAX
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};
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enum eosc_cali_version {
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EOSC_CALI_NONE,
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EOSC_CALI_MT6357_SERIES,
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EOSC_CALI_MT6358_SERIES,
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EOSC_CALI_MT6359_SERIES,
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EOSC_CALI_MT6359P_SERIES,
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};
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#endif
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#ifdef SUPPORT_PWR_OFF_ALARM
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#define RTC_PWRON_YEA RTC_PDN2
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#define RTC_PWRON_YEA_MASK 0x7f00
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#define RTC_PWRON_YEA_SHIFT 8
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#define RTC_PWRON_MTH RTC_PDN2
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#define RTC_PWRON_MTH_MASK 0x000f
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#define RTC_PWRON_MTH_SHIFT 0
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#define RTC_PWRON_SEC RTC_SPAR0
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#define RTC_PWRON_SEC_MASK 0x003f
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#define RTC_PWRON_SEC_SHIFT 0
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#define RTC_PWRON_MIN RTC_SPAR1
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#define RTC_PWRON_MIN_MASK 0x003f
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#define RTC_PWRON_MIN_SHIFT 0
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#define RTC_PWRON_HOU RTC_SPAR1
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#define RTC_PWRON_HOU_MASK 0x07c0
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#define RTC_PWRON_HOU_SHIFT 6
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#define RTC_PWRON_DOM RTC_SPAR1
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#define RTC_PWRON_DOM_MASK 0xf800
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#define RTC_PWRON_DOM_SHIFT 11
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struct tag_bootmode {
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u32 size;
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u32 tag;
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u32 bootmode;
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u32 boottype;
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};
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enum boot_mode_t {
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NORMAL_BOOT = 0,
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META_BOOT = 1,
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RECOVERY_BOOT = 2,
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SW_REBOOT = 3,
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FACTORY_BOOT = 4,
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ADVMETA_BOOT = 5,
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ATE_FACTORY_BOOT = 6,
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ALARM_BOOT = 7,
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KERNEL_POWER_OFF_CHARGING_BOOT = 8,
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LOW_POWER_OFF_CHARGING_BOOT = 9,
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DONGLE_BOOT = 10,
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UNKNOWN_BOOT
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};
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#endif
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struct mtk_rtc_data {
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u32 wrtgr;
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const struct reg_field *spare_reg_fields;
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#ifdef SUPPORT_EOSC_CALI
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const struct reg_field *cali_reg_fields;
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u32 eosc_cali_version;
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#endif
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};
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struct mt6397_rtc {
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struct rtc_device *rtc_dev;
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/* Protect register access from multiple tasks */
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struct mutex lock;
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struct regmap *regmap;
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int irq;
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u32 addr_base;
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const struct mtk_rtc_data *data;
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struct regmap_field *spare[SPARE_RG_MAX];
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#ifdef SUPPORT_EOSC_CALI
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struct regmap_field *cali[CALI_FILED_MAX];
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bool cali_is_supported;
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#endif
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#ifdef SUPPORT_PWR_OFF_ALARM
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struct work_struct work;
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struct completion comp;
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#if IS_ENABLED(CONFIG_PM)
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struct notifier_block pm_nb;
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#endif
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#endif
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};
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#endif /* _LINUX_MFD_MT6397_RTC_H_ */
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