mirror of
https://github.com/physwizz/a155-U-u1.git
synced 2025-10-07 10:09:34 +00:00
3298 lines
231 KiB
C
3298 lines
231 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __MT6360_PRIVATE_H__
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#define __MT6360_PRIVATE_H__
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#include <linux/interrupt.h>
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/* PMU register defininition */
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#define MT6338_TOP0_ID (0x0)
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#define MT6338_TOP0_ID_H (0x1)
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#define MT6338_TOP0_REV0 (0x2)
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#define MT6338_TOP0_REV0_H (0x3)
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#define MT6338_TOP0_DSN_DBI (0x4)
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#define MT6338_TOP0_DSN_DBI_H (0x5)
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#define MT6338_TOP0_DSN_DXI (0x6)
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#define MT6338_TOP0_DMY (0x7)
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#define MT6338_HWCID_L (0x8)
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#define MT6338_HWCID_H (0x9)
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#define MT6338_SWCID_L (0xa)
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#define MT6338_SWCID_H (0xb)
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#define MT6338_TOP_CON (0xc)
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#define MT6338_TEST_OUT (0xd)
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#define MT6338_TEST_OUT_H (0xe)
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#define MT6338_TEST_CON0 (0xf)
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#define MT6338_TEST_CON1 (0x10)
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#define MT6338_TEST_CON2 (0x11)
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#define MT6338_TEST_CON3 (0x12)
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#define MT6338_TEST_CON4 (0x13)
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#define MT6338_TEST_CON5 (0x14)
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#define MT6338_TEST_CON6 (0x15)
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#define MT6338_TEST_CON7 (0x16)
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#define MT6338_TEST_CON8 (0x17)
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#define MT6338_TEST_CON9 (0x18)
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#define MT6338_TEST_CON10 (0x19)
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#define MT6338_TEST_CON11 (0x1a)
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#define MT6338_TESTMODE_SW (0x1b)
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#define MT6338_TDSEL_CON0 (0x1c)
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#define MT6338_TDSEL_CON1 (0x1d)
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#define MT6338_RDSEL_CON (0x1e)
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#define MT6338_SMT_CON0 (0x1f)
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#define MT6338_SMT_CON1 (0x20)
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#define MT6338_TOP_RSV0 (0x21)
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#define MT6338_TOP_RSV1 (0x22)
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#define MT6338_DRV_CON0 (0x23)
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#define MT6338_DRV_CON1 (0x24)
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#define MT6338_DRV_CON2 (0x25)
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#define MT6338_DRV_CON3 (0x26)
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#define MT6338_DRV_CON4 (0x27)
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#define MT6338_DRV_CON5 (0x28)
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#define MT6338_TOP_STATUS (0x29)
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#define MT6338_TOP_STATUS_SET (0x2a)
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#define MT6338_TOP_STATUS_CLR (0x2b)
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#define MT6338_TOP_PWOFF_CON (0x2c)
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#define MT6338_TOP_TRAP (0x2d)
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#define MT6338_TMBIST_CFG00 (0x2e)
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#define MT6338_TMBIST_CFG01 (0x2f)
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#define MT6338_TMBIST_CFG02 (0x30)
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#define MT6338_TMBIST_CFG10 (0x31)
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#define MT6338_TMBIST_CFG11 (0x32)
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#define MT6338_TMBIST_CFG12 (0x33)
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#define MT6338_TMBIST_CFG20 (0x34)
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#define MT6338_TMBIST_CFG21 (0x35)
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#define MT6338_TMBIST_CFG22 (0x36)
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#define MT6338_TMBIST_CFG30 (0x37)
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#define MT6338_TMBIST_CFG31 (0x38)
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#define MT6338_TMBIST_CFG32 (0x39)
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#define MT6338_TOP1_ID (0x80)
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#define MT6338_TOP1_ID_H (0x81)
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#define MT6338_TOP1_REV0 (0x82)
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#define MT6338_TOP1_REV0_H (0x83)
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#define MT6338_TOP1_DSN_DBI (0x84)
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#define MT6338_TOP1_DSN_DBI_H (0x85)
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#define MT6338_TOP1_DSN_DXI (0x86)
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#define MT6338_GPIO_DIR0 (0x87)
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#define MT6338_GPIO_DIR0_SET (0x88)
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#define MT6338_GPIO_DIR0_CLR (0x89)
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#define MT6338_GPIO_DIR1 (0x8a)
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#define MT6338_GPIO_DIR1_SET (0x8b)
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#define MT6338_GPIO_DIR1_CLR (0x8c)
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#define MT6338_GPIO_PULLEN0 (0x8d)
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#define MT6338_GPIO_PULLEN0_SET (0x8e)
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#define MT6338_GPIO_PULLEN0_CLR (0x8f)
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#define MT6338_GPIO_PULLEN1 (0x90)
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#define MT6338_GPIO_PULLEN1_SET (0x91)
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#define MT6338_GPIO_PULLEN1_CLR (0x92)
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#define MT6338_GPIO_PULLSEL0 (0x93)
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#define MT6338_GPIO_PULLSEL0_SET (0x94)
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#define MT6338_GPIO_PULLSEL0_CLR (0x95)
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#define MT6338_GPIO_PULLSEL1 (0x96)
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#define MT6338_GPIO_PULLSEL1_SET (0x97)
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#define MT6338_GPIO_PULLSEL1_CLR (0x98)
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#define MT6338_GPIO_DINV0 (0x99)
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#define MT6338_GPIO_DINV0_SET (0x9a)
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#define MT6338_GPIO_DINV0_CLR (0x9b)
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#define MT6338_GPIO_DINV1 (0x9c)
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#define MT6338_GPIO_DINV1_SET (0x9d)
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#define MT6338_GPIO_DINV1_CLR (0x9e)
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#define MT6338_GPIO_DOUT0 (0x9f)
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#define MT6338_GPIO_DOUT0_SET (0xa0)
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#define MT6338_GPIO_DOUT0_CLR (0xa1)
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#define MT6338_GPIO_DOUT1 (0xa2)
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#define MT6338_GPIO_DOUT1_SET (0xa3)
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#define MT6338_GPIO_DOUT1_CLR (0xa4)
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#define MT6338_GPIO_PI0 (0xa5)
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#define MT6338_GPIO_PI1 (0xa6)
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#define MT6338_GPIO_POE0 (0xa7)
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#define MT6338_GPIO_POE1 (0xa8)
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#define MT6338_GPIO_MODE0 (0xa9)
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#define MT6338_GPIO_MODE0_SET (0xaa)
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#define MT6338_GPIO_MODE0_CLR (0xab)
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#define MT6338_GPIO_MODE1 (0xac)
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#define MT6338_GPIO_MODE1_SET (0xad)
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#define MT6338_GPIO_MODE1_CLR (0xae)
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#define MT6338_GPIO_MODE2 (0xaf)
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#define MT6338_GPIO_MODE2_SET (0xb0)
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#define MT6338_GPIO_MODE2_CLR (0xb1)
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#define MT6338_GPIO_MODE3 (0xb2)
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#define MT6338_GPIO_MODE3_SET (0xb3)
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#define MT6338_GPIO_MODE3_CLR (0xb4)
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#define MT6338_GPIO_MODE4 (0xb5)
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#define MT6338_GPIO_MODE4_SET (0xb6)
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#define MT6338_GPIO_MODE4_CLR (0xb7)
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#define MT6338_GPIO_MODE5 (0xb8)
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#define MT6338_GPIO_MODE5_SET (0xb9)
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#define MT6338_GPIO_MODE5_CLR (0xba)
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#define MT6338_GPIO_MODE6 (0xbb)
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#define MT6338_GPIO_MODE6_SET (0xbc)
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#define MT6338_GPIO_MODE6_CLR (0xbd)
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#define MT6338_GPIO_RSV (0xbe)
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#define MT6338_GPIO_CON (0xbf)
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#define MT6338_TOP2_ID (0x100)
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#define MT6338_TOP2_ID_H (0x101)
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#define MT6338_TOP2_REV0 (0x102)
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#define MT6338_TOP2_REV0_H (0x103)
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#define MT6338_TOP2_DSN_DBI (0x104)
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#define MT6338_TOP2_DSN_DBI_H (0x105)
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#define MT6338_TOP2_DSN_DXI (0x106)
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#define MT6338_TOP_PAM0 (0x107)
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#define MT6338_TOP_PAM0_H (0x108)
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#define MT6338_TOP_PAM1 (0x109)
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#define MT6338_TOP_PAM1_H (0x10a)
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#define MT6338_TOP_CKPDN_CON0 (0x10b)
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#define MT6338_TOP_CKPDN_CON0_SET (0x10c)
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#define MT6338_TOP_CKPDN_CON0_CLR (0x10d)
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#define MT6338_TOP_CKPDN_CON1 (0x10e)
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#define MT6338_TOP_CKPDN_CON1_SET (0x10f)
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#define MT6338_TOP_CKPDN_CON1_CLR (0x110)
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#define MT6338_TOP_CKSEL_CON0 (0x111)
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#define MT6338_TOP_CKSEL_CON0_SET (0x112)
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#define MT6338_TOP_CKSEL_CON0_CLR (0x113)
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#define MT6338_TOP_CKDIVSEL_CON0 (0x114)
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#define MT6338_TOP_CKDIVSEL_CON0_SET (0x115)
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#define MT6338_TOP_CKDIVSEL_CON0_CLR (0x116)
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#define MT6338_TOP_CKHWEN_CON0 (0x117)
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#define MT6338_TOP_CKHWEN_CON0_SET (0x118)
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#define MT6338_TOP_CKHWEN_CON0_CLR (0x119)
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#define MT6338_TOP_SMPS_OSC_DBG (0x11a)
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#define MT6338_TOP_CKTST_CON0 (0x11b)
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#define MT6338_TOP_CKTST_CON1 (0x11c)
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#define MT6338_TOP_CLK_CON0 (0x11d)
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#define MT6338_TOP_RST_CON0 (0x11e)
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#define MT6338_TOP_RST_CON0_SET (0x11f)
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#define MT6338_TOP_RST_CON0_CLR (0x120)
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#define MT6338_TOP_RST_CON1 (0x121)
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#define MT6338_TOP_RST_CON1_SET (0x122)
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#define MT6338_TOP_RST_CON1_CLR (0x123)
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#define MT6338_TOP_RST_CON2 (0x124)
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#define MT6338_TOP_RST_CON3 (0x125)
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#define MT6338_TOP_RST_STATUS (0x126)
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#define MT6338_TOP_RST_STATUS_SET (0x127)
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#define MT6338_TOP_RST_STATUS_CLR (0x128)
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#define MT6338_TOP_FQMTR_CON0 (0x129)
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#define MT6338_TOP_FQMTR_CON1 (0x12a)
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#define MT6338_TOP_FQMTR_CON2 (0x12b)
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#define MT6338_TOP_FQMTR_DAT0 (0x12c)
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#define MT6338_TOP_FQMTR_DAT1 (0x12d)
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#define MT6338_TOP2_ELR_NUM (0x12e)
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#define MT6338_TOP2_ELR0 (0x12f)
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#define MT6338_TOP2_ELR1 (0x130)
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#define MT6338_TOP2_ELR2 (0x131)
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#define MT6338_TOP2_ELR3 (0x132)
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#define MT6338_TOP2_ELR4 (0x133)
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#define MT6338_TOP2_ELR5 (0x134)
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#define MT6338_TOP2_ELR6 (0x135)
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#define MT6338_TOP2_ELR7 (0x136)
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#define MT6338_TOP3_ID (0x180)
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#define MT6338_TOP3_ID_H (0x181)
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#define MT6338_TOP3_REV0 (0x182)
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#define MT6338_TOP3_REV0_H (0x183)
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#define MT6338_TOP3_DSN_DBI (0x184)
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#define MT6338_TOP3_DSN_DBI_H (0x185)
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#define MT6338_TOP3_DSN_DXI (0x186)
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#define MT6338_TOP_INT_CON0 (0x187)
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#define MT6338_TOP_INT_CON0_SET (0x188)
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#define MT6338_TOP_INT_CON0_CLR (0x189)
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#define MT6338_TOP_INT_MASK_CON0 (0x18a)
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#define MT6338_TOP_INT_MASK_CON0_SET (0x18b)
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#define MT6338_TOP_INT_MASK_CON0_CLR (0x18c)
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#define MT6338_TOP_INT_STATUS0 (0x18d)
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#define MT6338_TOP_INT_STATUS1 (0x18e)
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#define MT6338_TOP_INT_RAW_STATUS0 (0x18f)
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#define MT6338_TOP_INT_RAW_STATUS1 (0x190)
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#define MT6338_TOP_INT_CON1 (0x191)
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#define MT6338_PMRC_CON0 (0x192)
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#define MT6338_PMRC_CON0_SET (0x193)
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#define MT6338_PMRC_CON0_CLR (0x194)
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#define MT6338_PMRC_CON1 (0x195)
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#define MT6338_PMRC_CON1_SET (0x196)
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#define MT6338_PMRC_CON1_CLR (0x197)
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#define MT6338_VDIG18_CON0 (0x198)
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#define MT6338_VDIG18_CON1 (0x199)
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#define MT6338_SPMI_WR_ADDR_MASK (0x19a)
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#define MT6338_SPMI_WR_ADDR_MASK_H (0x19b)
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#define MT6338_SPMI_RD_ADDR (0x19c)
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#define MT6338_SPMI_RD_ADDR_H (0x19d)
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#define MT6338_SPMI_RD_ADDR_MASK (0x19e)
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#define MT6338_SPMI_RD_ADDR_MASK_H (0x19f)
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#define MT6338_SPMI_WR_DATA (0x1a0)
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#define MT6338_SPMI_WR_DATA_MASK (0x1a1)
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#define MT6338_SPMI_RD_DATA (0x1a2)
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#define MT6338_SPMI_RD_DATA_MASK (0x1a3)
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#define MT6338_SPMI_INT_STS (0x1a4)
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#define MT6338_SPMI_INT_EN (0x1a5)
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#define MT6338_SPMI_RCS_BUS_SEL (0x1a6)
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#define MT6338_SPMI_RCS_CLK_SEL (0x1a7)
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#define MT6338_DA_INTF_STTING0 (0x1a8)
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#define MT6338_DA_INTF_STTING1 (0x1a9)
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#define MT6338_DA_INTF_STTING2 (0x1aa)
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#define MT6338_DA_INTF_STTING3 (0x1ab)
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#define MT6338_AD_STATUS0 (0x1ac)
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#define MT6338_MTC_CTL0 (0x1ad)
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#define MT6338_MTC_CTL1 (0x1ae)
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#define MT6338_MTC_CTL2 (0x1af)
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#define MT6338_MTC_STS0 (0x1b0)
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#define MT6338_MTC_STS1 (0x1b1)
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#define MT6338_PLT0_ID_ANA_ID (0x380)
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#define MT6338_PLT0_ID_DIG_ID (0x381)
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#define MT6338_PLT0_REV0 (0x382)
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#define MT6338_PLT0_REV1 (0x383)
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#define MT6338_PLT0_REV2 (0x384)
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#define MT6338_PLT0_REV3 (0x385)
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#define MT6338_PLT0_DSN_DXI (0x386)
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#define MT6338_TOP_CLK_TRIM_0 (0x387)
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#define MT6338_TOP_CLK_TRIM_1 (0x388)
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#define MT6338_TOP_CLK_TRIM_2 (0x389)
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#define MT6338_TOP_CLK_TRIM_3 (0x38a)
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#define MT6338_PLT_CON0 (0x38b)
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#define MT6338_PLT_CON1 (0x38c)
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#define MT6338_OTP_CON0 (0x38d)
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#define MT6338_OTP_CON1 (0x38e)
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#define MT6338_OTP_CON3 (0x38f)
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#define MT6338_OTP_CON4 (0x390)
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#define MT6338_OTP_CON5 (0x391)
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#define MT6338_OTP_CON6 (0x392)
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#define MT6338_OTP_CON7 (0x393)
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#define MT6338_OTP_CON8 (0x394)
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#define MT6338_OTP_CON9 (0x395)
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#define MT6338_OTP_CON10 (0x396)
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#define MT6338_OTP_CON11 (0x397)
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#define MT6338_OTP_CON12 (0x398)
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#define MT6338_OTP_CON13 (0x399)
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#define MT6338_OTP_CON14 (0x39a)
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#define MT6338_OTP_CON15 (0x39b)
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#define MT6338_OTP_CON17 (0x39c)
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#define MT6338_OTP_CON18 (0x39d)
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#define MT6338_OTP_CON19 (0x39e)
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#define MT6338_OTP_CON20 (0x39f)
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#define MT6338_OTP_CON21 (0x3a0)
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#define MT6338_TOP_TMA_KEY (0x3a1)
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#define MT6338_TOP_TMA_KEY_H (0x3a2)
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#define MT6338_TOP_ANA_KEY (0x3a3)
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#define MT6338_TOP_ANA_KEY_H (0x3a4)
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#define MT6338_TOP_MDB_CONF0 (0x3a5)
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#define MT6338_TOP_MDB_CONF0_H (0x3a6)
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#define MT6338_TOP_MDB_CONF1 (0x3a7)
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#define MT6338_TOP_MDB_CONF1_H (0x3a8)
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#define MT6338_TOP_MDB_CONF2 (0x3a9)
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#define MT6338_TOP_DIG_WPK (0x3aa)
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#define MT6338_TOP_DIG_WPK_H (0x3ab)
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#define MT6338_PLT0_ELR_NUM (0x3ac)
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#define MT6338_PLT0_ELR0 (0x3ad)
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#define MT6338_PLT0_ELR1 (0x3ae)
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#define MT6338_I2CRECORD_ID_ANA_ID (0x400)
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#define MT6338_I2CRECORD_ID_DIG_ID (0x401)
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#define MT6338_I2CRECORD_REV0 (0x402)
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#define MT6338_I2CRECORD_REV1 (0x403)
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#define MT6338_I2CRECORD_REV2 (0x404)
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#define MT6338_I2CRECORD_REV3 (0x405)
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#define MT6338_I2CRECORD_DSN_DXI (0x406)
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#define MT6338_RECORD_CMD0_H (0x407)
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#define MT6338_RECORD_CMD0_L (0x408)
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#define MT6338_RECORD_CMD1_H (0x409)
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#define MT6338_RECORD_CMD1_L (0x40a)
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#define MT6338_RECORD_CMD2_H (0x40b)
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#define MT6338_RECORD_CMD2_L (0x40c)
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#define MT6338_RECORD_CMD3_H (0x40d)
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#define MT6338_RECORD_CMD3_L (0x40e)
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#define MT6338_RECORD_CMD4_H (0x40f)
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#define MT6338_RECORD_CMD4_L (0x410)
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#define MT6338_RECORD_CMD5_H (0x411)
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#define MT6338_RECORD_CMD5_L (0x412)
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#define MT6338_RECORD_CMD6_H (0x413)
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#define MT6338_RECORD_CMD6_L (0x414)
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#define MT6338_RECORD_CMD7_H (0x415)
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#define MT6338_RECORD_CMD7_L (0x416)
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#define MT6338_RECORD_CMD8_H (0x417)
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#define MT6338_RECORD_CMD8_L (0x418)
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#define MT6338_RECORD_CMD9_H (0x419)
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#define MT6338_RECORD_CMD9_L (0x41a)
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#define MT6338_RECORD_CMD10_H (0x41b)
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#define MT6338_RECORD_CMD10_L (0x41c)
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#define MT6338_RECORD_CMD11_H (0x41d)
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#define MT6338_RECORD_CMD11_L (0x41e)
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#define MT6338_RECORD_CMD12_H (0x41f)
|
|
#define MT6338_RECORD_CMD12_L (0x420)
|
|
#define MT6338_RECORD_CMD13_H (0x421)
|
|
#define MT6338_RECORD_CMD13_L (0x422)
|
|
#define MT6338_RECORD_CMD14_H (0x423)
|
|
#define MT6338_RECORD_CMD14_L (0x424)
|
|
#define MT6338_RECORD_CMD15_H (0x425)
|
|
#define MT6338_RECORD_CMD15_L (0x426)
|
|
#define MT6338_RECORD_DATA0 (0x427)
|
|
#define MT6338_RECORD_DATA1 (0x428)
|
|
#define MT6338_RECORD_DATA2 (0x429)
|
|
#define MT6338_RECORD_DATA3 (0x42a)
|
|
#define MT6338_RECORD_DATA4 (0x42b)
|
|
#define MT6338_RECORD_DATA5 (0x42c)
|
|
#define MT6338_RECORD_DATA6 (0x42d)
|
|
#define MT6338_RECORD_DATA7 (0x42e)
|
|
#define MT6338_RECORD_DATA8 (0x42f)
|
|
#define MT6338_RECORD_DATA9 (0x430)
|
|
#define MT6338_RECORD_DATA10 (0x431)
|
|
#define MT6338_RECORD_DATA11 (0x432)
|
|
#define MT6338_RECORD_DATA12 (0x433)
|
|
#define MT6338_RECORD_DATA13 (0x434)
|
|
#define MT6338_RECORD_DATA14 (0x435)
|
|
#define MT6338_RECORD_DATA15 (0x436)
|
|
#define MT6338_RECORD_CON0 (0x437)
|
|
#define MT6338_RECORD_CON1 (0x438)
|
|
#define MT6338_RECORD_CON2 (0x439)
|
|
#define MT6338_RECORD_CON3 (0x43a)
|
|
#define MT6338_RECORD_CON4 (0x43b)
|
|
#define MT6338_RECORD_CON5 (0x43c)
|
|
#define MT6338_RECORD_CON6 (0x43d)
|
|
#define MT6338_RECORD_CON7 (0x43e)
|
|
#define MT6338_RECORD_CON8 (0x43f)
|
|
#define MT6338_RECORD_CON9 (0x440)
|
|
#define MT6338_RECORD_CON10 (0x441)
|
|
#define MT6338_RECORD_CON11 (0x442)
|
|
#define MT6338_INT_CON0 (0x443)
|
|
#define MT6338_INT_CON1 (0x444)
|
|
#define MT6338_INT_CON2 (0x445)
|
|
#define MT6338_INT_CON3 (0x446)
|
|
#define MT6338_INT_CON4 (0x447)
|
|
#define MT6338_INT_CON5 (0x448)
|
|
#define MT6338_INT_CON6 (0x449)
|
|
#define MT6338_INT_CON7 (0x44a)
|
|
#define MT6338_INT_CON8 (0x44b)
|
|
#define MT6338_INT_CON9 (0x44c)
|
|
#define MT6338_INT_CON10 (0x44d)
|
|
#define MT6338_INT_CON11 (0x44e)
|
|
#define MT6338_RECORD_INT_CON0 (0x44f)
|
|
#define MT6338_RECORD_INT_CON1 (0x450)
|
|
#define MT6338_DEW_WRITE_TEST_L (0x451)
|
|
#define MT6338_DEW_WRITE_TEST_H (0x452)
|
|
#define MT6338_I2C_TEST_CON0 (0x453)
|
|
#define MT6338_SPMI_ANA_ID (0x480)
|
|
#define MT6338_SPMI_DIG_ID (0x481)
|
|
#define MT6338_SPMI_ANA_REV0 (0x482)
|
|
#define MT6338_SPMI_DIG_REV0 (0x483)
|
|
#define MT6338_SPMI_REV1 (0x484)
|
|
#define MT6338_SPMI_ESP (0x485)
|
|
#define MT6338_SPMI_DSN_FPI (0x486)
|
|
#define MT6338_SPMI_DSN_DXI (0x487)
|
|
#define MT6338_PLT_DIG_WPK (0x488)
|
|
#define MT6338_PLT_DIG_WPK_H (0x489)
|
|
#define MT6338_SPMI_EXT_ADDR1 (0x48a)
|
|
#define MT6338_SPMI_EXT_ADDR0 (0x48b)
|
|
#define MT6338_SPMI_EXT_ADDR0_H (0x48c)
|
|
#define MT6338_SPMI_EXT_ADDR2 (0x48d)
|
|
#define MT6338_SPMI_EXT_ADDR2_H (0x48e)
|
|
#define MT6338_SPMI_RCS_FUN0 (0x48f)
|
|
#define MT6338_SPMI_RCS_FUN1 (0x490)
|
|
#define MT6338_SPMI_RCS_FUN2 (0x491)
|
|
#define MT6338_SPMI_WR_ADDR (0x492)
|
|
#define MT6338_SPMI_WR_ADDR_H (0x493)
|
|
#define MT6338_SPMI_REG_RSV0 (0x494)
|
|
#define MT6338_SPMI_REG_RSV1 (0x495)
|
|
#define MT6338_SPMI_REG_RSV2 (0x496)
|
|
#define MT6338_SPMI_DEBUG_OUT_L (0x497)
|
|
#define MT6338_SPMI_DEBUG_OUT_H (0x498)
|
|
#define MT6338_SPMI_DEBUG_SEL (0x499)
|
|
#define MT6338_SPMI_RSV0 (0x49a)
|
|
#define MT6338_SPMI_RSV1 (0x49b)
|
|
#define MT6338_PSC_TOP_ID_ANA (0x900)
|
|
#define MT6338_PSC_TOP_ID_DIG (0x901)
|
|
#define MT6338_PSC_TOP_REV0 (0x902)
|
|
#define MT6338_PSC_TOP_REV1 (0x903)
|
|
#define MT6338_PSC_TOP_DBI0 (0x904)
|
|
#define MT6338_PSC_TOP_DBI1 (0x905)
|
|
#define MT6338_PSC_TOP_DXI (0x906)
|
|
#define MT6338_PSC_CON0 (0x907)
|
|
#define MT6338_PSC_CON1 (0x908)
|
|
#define MT6338_PSC_CON2 (0x909)
|
|
#define MT6338_PSC_WPK_L (0x90a)
|
|
#define MT6338_PSC_WPK_H (0x90b)
|
|
#define MT6338_PSC_DBG0 (0x90c)
|
|
#define MT6338_PSC_ELR_NUM (0x90d)
|
|
#define MT6338_PSC_ELR0 (0x90e)
|
|
#define MT6338_PSC_ELR1 (0x90f)
|
|
#define MT6338_ANATOP_ANA_ID (0x980)
|
|
#define MT6338_ANATOP_DIG_ID (0x981)
|
|
#define MT6338_ANATOP_ANA_REV (0x982)
|
|
#define MT6338_ANATOP_DIG_REV (0x983)
|
|
#define MT6338_ANATOP_DBI (0x984)
|
|
#define MT6338_ANATOP_ESP (0x985)
|
|
#define MT6338_ANATOP_FPI (0x986)
|
|
#define MT6338_ANATOP_DXI (0x987)
|
|
#define MT6338_STRUP_PMU_CON0 (0x988)
|
|
#define MT6338_STRUP_PMU_CON1 (0x989)
|
|
#define MT6338_STRUP_PMU_CON2 (0x98a)
|
|
#define MT6338_TSBG_PMU_CON0 (0x98b)
|
|
#define MT6338_TSBG_PMU_CON1 (0x98c)
|
|
#define MT6338_IVGEN_PMU_CON0 (0x98d)
|
|
#define MT6338_IVGEN_PMU_CON1 (0x98e)
|
|
#define MT6338_CLKSQ_PMU_CON0 (0x98f)
|
|
#define MT6338_SPIOSC_PMU_CON0 (0x990)
|
|
#define MT6338_PLL208M_PMU_CON0 (0x991)
|
|
#define MT6338_PLL208M_PMU_CON1 (0x992)
|
|
#define MT6338_PLL208M_PMU_CON2 (0x993)
|
|
#define MT6338_PLL208M_PMU_CON3 (0x994)
|
|
#define MT6338_PLL208M_PMU_CON4 (0x995)
|
|
#define MT6338_PLL208M_PMU_CON5 (0x996)
|
|
#define MT6338_VOWPLL_PMU_CON0 (0x997)
|
|
#define MT6338_VOWPLL_PMU_CON1 (0x998)
|
|
#define MT6338_VOWPLL_PMU_CON2 (0x999)
|
|
#define MT6338_VOWPLL_PMU_CON3 (0x99a)
|
|
#define MT6338_VOWPLL_PMU_CON4 (0x99b)
|
|
#define MT6338_VOWPLL_PMU_CON5 (0x99c)
|
|
#define MT6338_VOWPLL_PMU_CON6 (0x99d)
|
|
#define MT6338_VOWPLL_PMU_CON7 (0x99e)
|
|
#define MT6338_VOWPLL_PMU_CON8 (0x99f)
|
|
#define MT6338_VOWPLL_PMU_CON9 (0x9a0)
|
|
#define MT6338_ANATOP_ELR_NUM (0x9a1)
|
|
#define MT6338_STRUP_ELR_0 (0x9a2)
|
|
#define MT6338_STRUP_ELR_1 (0x9a3)
|
|
#define MT6338_STRUP_ELR_2 (0x9a4)
|
|
#define MT6338_STRUP_ELR_3 (0x9a5)
|
|
#define MT6338_HK_TOP_DSN_ID0 (0xf80)
|
|
#define MT6338_HK_TOP_DSN_ID1 (0xf81)
|
|
#define MT6338_HK_TOP_REV0 (0xf82)
|
|
#define MT6338_HK_TOP_REV1 (0xf83)
|
|
#define MT6338_HK_TOP_DBI (0xf84)
|
|
#define MT6338_HK_TOP_ESP (0xf85)
|
|
#define MT6338_HK_TOP_DXI (0xf86)
|
|
#define MT6338_HK_TPM0 (0xf87)
|
|
#define MT6338_HK_TPM1 (0xf88)
|
|
#define MT6338_HK_TPM2 (0xf89)
|
|
#define MT6338_HK_TPM3 (0xf8a)
|
|
#define MT6338_HK_TOP_CLK_CON0 (0xf8b)
|
|
#define MT6338_HK_TOP_CLK_CON1 (0xf8c)
|
|
#define MT6338_HK_TOP_RST_CON0 (0xf8d)
|
|
#define MT6338_HK_TOP_MON_CON0 (0xf8e)
|
|
#define MT6338_HK_TOP_MON_CON2 (0xf8f)
|
|
#define MT6338_HK_TOP_STRUP_CON0 (0xf90)
|
|
#define MT6338_HK_TOP_STRUP_CON1 (0xf91)
|
|
#define MT6338_HK_TOP_LDO_CON (0xf92)
|
|
#define MT6338_HK_TOP_LDO_STATUS (0xf93)
|
|
#define MT6338_HK_TOP_WKEY_L (0xf94)
|
|
#define MT6338_HK_TOP_WKEY_H (0xf95)
|
|
#define MT6338_HK_TOP_TEST_CON (0xf96)
|
|
#define MT6338_AUXADC_ANA_ID (0x1000)
|
|
#define MT6338_AUXADC_DIG_ID (0x1001)
|
|
#define MT6338_AUXADC_ANA_REV (0x1002)
|
|
#define MT6338_AUXADC_DIG_REV (0x1003)
|
|
#define MT6338_AUXADC_DBI (0x1004)
|
|
#define MT6338_AUXADC_ESP (0x1005)
|
|
#define MT6338_AUXADC_FPI (0x1006)
|
|
#define MT6338_AUXADC_PMU_CON0 (0x1007)
|
|
#define MT6338_AUXADC_PMU_CON1 (0x1008)
|
|
#define MT6338_AUXADC_PMU_CON2 (0x1009)
|
|
#define MT6338_AUXADC_PMU_CON3 (0x100a)
|
|
#define MT6338_AUXADC_DIG_1_DSN_ID0 (0x1080)
|
|
#define MT6338_AUXADC_DIG_1_DSN_ID1 (0x1081)
|
|
#define MT6338_AUXADC_DIG_1_DSN_REV0 (0x1082)
|
|
#define MT6338_AUXADC_DIG_1_DSN_REV1 (0x1083)
|
|
#define MT6338_AUXADC_DIG_1_DSN_DBI (0x1084)
|
|
#define MT6338_AUXADC_DIG_1_DSN_ESP (0x1085)
|
|
#define MT6338_AUXADC_DIG_1_DSN_FPI (0x1086)
|
|
#define MT6338_AUXADC_DIG_1_DSN_DXI (0x1087)
|
|
#define MT6338_AUXADC_ADC4_L (0x1088)
|
|
#define MT6338_AUXADC_ADC4_H (0x1089)
|
|
#define MT6338_AUXADC_ADC5_L (0x108a)
|
|
#define MT6338_AUXADC_ADC5_H (0x108b)
|
|
#define MT6338_AUXADC_ADC9_L (0x108c)
|
|
#define MT6338_AUXADC_ADC9_H (0x108d)
|
|
#define MT6338_AUXADC_ADC10_L (0x108e)
|
|
#define MT6338_AUXADC_ADC10_H (0x108f)
|
|
#define MT6338_AUXADC_ADC30_L (0x1090)
|
|
#define MT6338_AUXADC_ADC30_H (0x1091)
|
|
#define MT6338_AUXADC_ADC45_L (0x1092)
|
|
#define MT6338_AUXADC_ADC45_H (0x1093)
|
|
#define MT6338_AUXADC_ADC46_L (0x1094)
|
|
#define MT6338_AUXADC_ADC46_H (0x1095)
|
|
#define MT6338_AUXADC_STA0 (0x1096)
|
|
#define MT6338_AUXADC_STA1 (0x1097)
|
|
#define MT6338_AUXADC_STA3 (0x1098)
|
|
#define MT6338_AUXADC_STA4 (0x1099)
|
|
#define MT6338_AUXADC_SPL_LIST_0 (0x109a)
|
|
#define MT6338_AUXADC_DIG_2_DSN_ID0 (0x1100)
|
|
#define MT6338_AUXADC_DIG_2_DSN_ID1 (0x1101)
|
|
#define MT6338_AUXADC_DIG_2_DSN_REV0 (0x1102)
|
|
#define MT6338_AUXADC_DIG_2_DSN_REV1 (0x1103)
|
|
#define MT6338_AUXADC_DIG_2_DSN_DBI (0x1104)
|
|
#define MT6338_AUXADC_DIG_2_DSN_ESP (0x1105)
|
|
#define MT6338_AUXADC_DIG_2_DSN_DXI (0x1106)
|
|
#define MT6338_AUXADC_RQST0 (0x1107)
|
|
#define MT6338_AUXADC_DIG_3_DSN_ID0 (0x1180)
|
|
#define MT6338_AUXADC_DIG_3_DSN_ID1 (0x1181)
|
|
#define MT6338_AUXADC_DIG_3_DSN_REV0 (0x1182)
|
|
#define MT6338_AUXADC_DIG_3_DSN_REV1 (0x1183)
|
|
#define MT6338_AUXADC_DIG_3_DSN_DBI (0x1184)
|
|
#define MT6338_AUXADC_DIG_3_DSN_ESP (0x1185)
|
|
#define MT6338_AUXADC_DIG_3_DSN_DXI (0x1186)
|
|
#define MT6338_AUXADC_CON0 (0x1187)
|
|
#define MT6338_AUXADC_CON1 (0x1188)
|
|
#define MT6338_AUXADC_SPL_CON0 (0x1189)
|
|
#define MT6338_AUXADC_SPL_CON1 (0x118a)
|
|
#define MT6338_AUXADC_SPL_CON2 (0x118b)
|
|
#define MT6338_AUXADC_SPL_CON3 (0x118c)
|
|
#define MT6338_AUXADC_SPL_CON4 (0x118d)
|
|
#define MT6338_AUXADC_SPL_CON5 (0x118e)
|
|
#define MT6338_AUXADC_SPL_CON9 (0x118f)
|
|
#define MT6338_AUXADC_AVG_CON0 (0x1190)
|
|
#define MT6338_AUXADC_AVG_CON1 (0x1191)
|
|
#define MT6338_AUXADC_AVG_CON2 (0x1192)
|
|
#define MT6338_AUXADC_AVG_CON3 (0x1193)
|
|
#define MT6338_AUXADC_AVG_CON4 (0x1194)
|
|
#define MT6338_AUXADC_TRIM_SEL2 (0x1195)
|
|
#define MT6338_AUXADC_CON28 (0x1196)
|
|
#define MT6338_AUXADC_CON29 (0x1197)
|
|
#define MT6338_AUXADC_CON30 (0x1198)
|
|
#define MT6338_AUXADC_CON31 (0x1199)
|
|
#define MT6338_AUXADC_CON32 (0x119a)
|
|
#define MT6338_AUXADC_CON33 (0x119b)
|
|
#define MT6338_AUXADC_CON35 (0x119c)
|
|
#define MT6338_AUXADC_CON36 (0x119d)
|
|
#define MT6338_AUXADC_CON37 (0x119e)
|
|
#define MT6338_AUXADC_CON38 (0x119f)
|
|
#define MT6338_AUXADC_CON39 (0x11a0)
|
|
#define MT6338_AUXADC_CON40 (0x11a1)
|
|
#define MT6338_AUXADC_CON44 (0x11a2)
|
|
#define MT6338_AUXADC_CON45 (0x11a3)
|
|
#define MT6338_AUXADC_AUTORPT0 (0x11a4)
|
|
#define MT6338_AUXADC_AUTORPT1 (0x11a5)
|
|
#define MT6338_AUXADC_AUTORPT2 (0x11a6)
|
|
#define MT6338_AUXADC_ACCDET0 (0x11a7)
|
|
#define MT6338_AUXADC_ACCDET1 (0x11a8)
|
|
#define MT6338_AUXADC_DBG0 (0x11a9)
|
|
#define MT6338_AUXADC_DBG1 (0x11aa)
|
|
#define MT6338_AUXADC_PRI_NEW (0x11ab)
|
|
#define MT6338_AUXADC_DIG_3_ELR_NUM (0x11ac)
|
|
#define MT6338_AUXADC_DIG_3_ELR8 (0x11ad)
|
|
#define MT6338_AUXADC_DIG_3_ELR9 (0x11ae)
|
|
#define MT6338_AUXADC_DIG_3_ELR10 (0x11af)
|
|
#define MT6338_AUXADC_DIG_3_ELR11 (0x11b0)
|
|
#define MT6338_AUXADC_DIG_3_ELR20 (0x11b1)
|
|
#define MT6338_AUXADC_DIG_3_ELR21 (0x11b2)
|
|
#define MT6338_AUXADC_DIG_3_ELR22 (0x11b3)
|
|
#define MT6338_AUXADC_DIG_3_ELR23 (0x11b4)
|
|
#define MT6338_AUXADC_DIG_3_ELR24 (0x11b5)
|
|
#define MT6338_AUXADC_DIG_3_ELR25 (0x11b6)
|
|
#define MT6338_AUXADC_DIG_3_ELR26 (0x11b7)
|
|
#define MT6338_AUXADC_DIG_3_ELR27 (0x11b8)
|
|
#define MT6338_AUXADC_DIG_3_ELR36 (0x11b9)
|
|
#define MT6338_AUXADC_DIG_3_ELR37 (0x11ba)
|
|
#define MT6338_AUXADC_DIG_3_ELR38 (0x11bb)
|
|
#define MT6338_AUXADC_DIG_3_ELR39 (0x11bc)
|
|
#define MT6338_AUXADC_DIG_3_ELR40 (0x11bd)
|
|
#define MT6338_AUXADC_DIG_3_ELR41 (0x11be)
|
|
#define MT6338_AUXADC_DIG_3_ELR42 (0x11bf)
|
|
#define MT6338_AUXADC_DIG_3_ELR43 (0x11c0)
|
|
#define MT6338_AUXADC_DIG_3_ELR44 (0x11c1)
|
|
#define MT6338_AUXADC_DIG_3_ELR45 (0x11c2)
|
|
#define MT6338_AUXADC_DIG_3_ELR46 (0x11c3)
|
|
#define MT6338_AUXADC_DIG_3_ELR47 (0x11c4)
|
|
#define MT6338_AUXADC_DIG_3_ELR48 (0x11c5)
|
|
#define MT6338_AUXADC_DIG_3_ELR49 (0x11c6)
|
|
#define MT6338_AUXADC_DIG_3_ELR50 (0x11c7)
|
|
#define MT6338_AUXADC_DIG_3_ELR51 (0x11c8)
|
|
#define MT6338_AUXADC_DIG_3_ELR52 (0x11c9)
|
|
#define MT6338_AUXADC_DIG_3_ELR53 (0x11ca)
|
|
#define MT6338_AUXADC_DIG_3_ELR54 (0x11cb)
|
|
#define MT6338_AUXADC_DIG_3_ELR55 (0x11cc)
|
|
#define MT6338_LDO_TOP_ANA_ID (0x1b00)
|
|
#define MT6338_LDO_TOP_DIG_ID (0x1b01)
|
|
#define MT6338_LDO_TOP_ANA_REV (0x1b02)
|
|
#define MT6338_LDO_TOP_DIG_REV (0x1b03)
|
|
#define MT6338_LDO_TOP_DBI (0x1b04)
|
|
#define MT6338_PSC_TOP_ESP (0x1b05)
|
|
#define MT6338_LDO_TOP_FPI (0x1b06)
|
|
#define MT6338_LDO_TOP_DXI (0x1b07)
|
|
#define MT6338_LDO_TPM0 (0x1b08)
|
|
#define MT6338_LDO_TPM0_H (0x1b09)
|
|
#define MT6338_LDO_TPM1 (0x1b0a)
|
|
#define MT6338_LDO_TPM1_H (0x1b0b)
|
|
#define MT6338_LDO_TOP_CKPDN_CON0 (0x1b0c)
|
|
#define MT6338_TOP_TOP_CKHWEN_CON0 (0x1b0d)
|
|
#define MT6338_LDO_TOP_CLK_DCM_CON0 (0x1b0e)
|
|
#define MT6338_LDO_TOP_VR_CLK_CON0 (0x1b0f)
|
|
#define MT6338_LDO_VD105_OC_CON (0x1b10)
|
|
#define MT6338_LDO_TEST_CON0 (0x1b11)
|
|
#define MT6338_LDO_TEST_CON1 (0x1b12)
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#define MT6338_LDO_TOP_CON0 (0x1b13)
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#define MT6338_LDO_TOP_CON1 (0x1b14)
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#define MT6338_VAUD18_ACK (0x1b15)
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#define MT6338_LDO_TOP_ELR_NUM (0x1b16)
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#define MT6338_LDO_TOP_ELR (0x1b17)
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#define MT6338_LDO_GNR0_ANA_ID (0x1b80)
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#define MT6338_LDO_GNR0_DIG_ID (0x1b81)
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#define MT6338_LDO_GNR0_ANA_REV (0x1b82)
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#define MT6338_LDO_GNR0_DIG_REV (0x1b83)
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#define MT6338_LDO_GNR0_DSN_DBI (0x1b84)
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#define MT6338_LDO_GNR0_DSN_ESP (0x1b85)
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#define MT6338_LDO_GNR0_DSN_DXI (0x1b86)
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#define MT6338_LDO_VAUD18_CON0 (0x1b87)
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#define MT6338_LDO_VAUD18_CON1 (0x1b88)
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#define MT6338_LDO_VAUD18_CON2 (0x1b89)
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#define MT6338_LDO_VAUD18_MON (0x1b8a)
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#define MT6338_LDO_VAUD18_OP_EN0 (0x1b8b)
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#define MT6338_LDO_VAUD18_OP_EN0_SET (0x1b8c)
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#define MT6338_LDO_VAUD18_OP_EN0_CLR (0x1b8d)
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#define MT6338_LDO_VAUD18_OP_EN1 (0x1b8e)
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#define MT6338_LDO_VAUD18_OP_EN1_SET (0x1b8f)
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#define MT6338_LDO_VAUD18_OP_EN1_CLR (0x1b90)
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#define MT6338_LDO_VAUD18_OP_CFG0 (0x1b91)
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#define MT6338_LDO_VAUD18_OP_CFG0_SET (0x1b92)
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#define MT6338_LDO_VAUD18_OP_CFG0_CLR (0x1b93)
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#define MT6338_LDO_VAUD18_OP_CFG1 (0x1b94)
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#define MT6338_LDO_VAUD18_OP_CFG1_SET (0x1b95)
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#define MT6338_LDO_VAUD18_OP_CFG1_CLR (0x1b96)
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#define MT6338_LDO_VAUD18_MULTI_SW_0 (0x1b97)
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#define MT6338_LDO_VAUD18_MULTI_SW_1 (0x1b98)
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#define MT6338_LDO_ANA0_ANA_ID (0x1c00)
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#define MT6338_LDO_ANA0_DIG_ID (0x1c01)
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#define MT6338_LDO_ANA0_ANA_REV (0x1c02)
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#define MT6338_LDO_ANA0_DIG_REV (0x1c03)
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#define MT6338_LDO_ANA0_DBI (0x1c04)
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#define MT6338_LDO_ANA0_ESP (0x1c05)
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#define MT6338_LDO_ANA0_FPI (0x1c06)
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#define MT6338_LDO_ANA0_DXI (0x1c07)
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#define MT6338_VD105_PMU_CON0 (0x1c08)
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#define MT6338_VAUD18_PMU_CON0 (0x1c09)
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#define MT6338_VAUD18_PMU_CON1 (0x1c0a)
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#define MT6338_VAUD18_PMU_CON2 (0x1c0b)
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#define MT6338_VPLL18_PMU_CON0 (0x1c0c)
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#define MT6338_VPLL18_PMU_CON1 (0x1c0d)
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#define MT6338_VPLL18_PMU_CON2 (0x1c0e)
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#define MT6338_LDO_ANA0_ELR_NUM (0x1c0f)
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#define MT6338_VD105_ELR_0 (0x1c10)
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#define MT6338_AUD_TOP_ID (0x2300)
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#define MT6338_AUD_TOP_ID_H (0x2301)
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#define MT6338_AUD_TOP_REV0 (0x2302)
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#define MT6338_AUD_TOP_REV0_H (0x2303)
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#define MT6338_AUD_TOP_DBI (0x2304)
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#define MT6338_AUD_TOP_DBI_H (0x2305)
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#define MT6338_AUD_TOP_DXI (0x2306)
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#define MT6338_AUD_TOP_CKPDN_TPM0 (0x2307)
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#define MT6338_AUD_TOP_CKPDN_TPM0_H (0x2308)
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#define MT6338_AUD_TOP_CKPDN_TPM1 (0x2309)
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#define MT6338_AUD_TOP_CKPDN_TPM1_H (0x230a)
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#define MT6338_AUD_TOP_CKPDN_CON0 (0x230b)
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#define MT6338_AUD_TOP_CKPDN_CON0_SET (0x230c)
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#define MT6338_AUD_TOP_CKPDN_CON0_CLR (0x230d)
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#define MT6338_AUD_TOP_CKPDN_CON0_H (0x230e)
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#define MT6338_AUD_TOP_CKPDN_CON0_H_SET (0x230f)
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#define MT6338_AUD_TOP_CKPDN_CON0_H_CLR (0x2310)
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#define MT6338_AUD_TOP_CKSEL_CON0 (0x2311)
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#define MT6338_AUD_TOP_CKSEL_CON0_SET (0x2312)
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#define MT6338_AUD_TOP_CKSEL_CON0_CLR (0x2313)
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|
#define MT6338_AUD_TOP_CKTST_CON0 (0x2314)
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#define MT6338_AUD_TOP_CKTST_CON0_H (0x2315)
|
|
#define MT6338_AUD_TOP_CLK_HWEN_CON0 (0x2316)
|
|
#define MT6338_AUD_TOP_CLK_HWEN_CON0_SET (0x2317)
|
|
#define MT6338_AUD_TOP_CLK_HWEN_CON0_CLR (0x2318)
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|
#define MT6338_AUD_TOP_RST_CON0 (0x2319)
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|
#define MT6338_AUD_TOP_RST_CON0_SET (0x231a)
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|
#define MT6338_AUD_TOP_RST_CON0_CLR (0x231b)
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|
#define MT6338_AUD_TOP_RST_BANK_CON0 (0x231c)
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|
#define MT6338_AUD_TOP_INT_CON0 (0x231d)
|
|
#define MT6338_AUD_TOP_INT_CON0_SET (0x231e)
|
|
#define MT6338_AUD_TOP_INT_CON0_CLR (0x231f)
|
|
#define MT6338_AUD_TOP_INT_MASK_CON0 (0x2320)
|
|
#define MT6338_AUD_TOP_INT_MASK_CON0_SET (0x2321)
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|
#define MT6338_AUD_TOP_INT_MASK_CON0_CLR (0x2322)
|
|
#define MT6338_AUD_TOP_INT_STATUS0 (0x2323)
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#define MT6338_AUD_TOP_INT_RAW_STATUS0 (0x2324)
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|
#define MT6338_AUD_TOP_INT_MISC_CON0 (0x2325)
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|
#define MT6338_AUD_TOP_MON_CON0 (0x2326)
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|
#define MT6338_AUD_TOP_MON_CON0_H (0x2327)
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#define MT6338_AUDIO_DIG_CFG (0x2328)
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#define MT6338_AUDIO_DIG_CFG_H (0x2329)
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|
#define MT6338_AUDIO_DIG_CFG1 (0x232a)
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|
#define MT6338_AFE_AUD_PAD_TOP (0x232b)
|
|
#define MT6338_AFE_AUD_PAD_TOP_MON (0x232c)
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|
#define MT6338_AFE_AUD_PAD_TOP_MON_H (0x232d)
|
|
#define MT6338_AFE_AUD_PAD_TOP_MON1 (0x232e)
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|
#define MT6338_AFE_AUD_PAD_TOP_MON1_H (0x232f)
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|
#define MT6338_AFE_AUD_PAD_TOP_MON2 (0x2330)
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|
#define MT6338_AUD_TOP_SRAM_CON (0x2331)
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#define MT6338_AFE_DCCLK1_CFG0 (0x2332)
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|
#define MT6338_AFE_DCCLK1_CFG1 (0x2333)
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|
#define MT6338_AFE_DCCLK1_CFG2 (0x2334)
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|
#define MT6338_AFE_DCCLK2_CFG0 (0x2335)
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|
#define MT6338_AFE_DCCLK2_CFG1 (0x2336)
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|
#define MT6338_AFE_DCCLK2_CFG2 (0x2337)
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|
#define MT6338_AFE_DCCLK3_CFG0 (0x2338)
|
|
#define MT6338_AFE_DCCLK3_CFG1 (0x2339)
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|
#define MT6338_AFE_DCCLK3_CFG2 (0x233a)
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|
#define MT6338_AFE_DCCLK4_CFG0 (0x233b)
|
|
#define MT6338_AFE_DCCLK4_CFG1 (0x233c)
|
|
#define MT6338_AFE_DCCLK4_CFG2 (0x233d)
|
|
#define MT6338_AO_AFUNC_AUD_CON3_L (0x233e)
|
|
#define MT6338_AO_AFUNC_AUD_CON4_H (0x233f)
|
|
#define MT6338_AO_AFUNC_AUD_CON4_L (0x2340)
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|
#define MT6338_AO_AFUNC_AUD_CON7_H (0x2341)
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|
#define MT6338_AO_AFUNC_AUD_CON7_L (0x2342)
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|
#define MT6338_AO_AFE_DMIC_ARRAY_CFG (0x2343)
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|
#define MT6338_AO_AFE_ADC_ASYNC_FIFO_CFG (0x2344)
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#define MT6338_AO_AUDIO_TOP_CON0 (0x2345)
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#define MT6338_AUDIO_DIG_DSN_ID (0x2380)
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|
#define MT6338_AUDIO_DIG_DSN_ID_H (0x2381)
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|
#define MT6338_AUDIO_DIG_DSN_REV0 (0x2382)
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|
#define MT6338_AUDIO_DIG_DSN_REV0_H (0x2383)
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|
#define MT6338_AUDIO_DIG_DSN_DBI (0x2384)
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|
#define MT6338_AUDIO_DIG_DSN_DBI_H (0x2385)
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|
#define MT6338_AUDIO_DIG_DSN_DXI (0x2386)
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|
#define MT6338_AUDIO_TOP_CON0 (0x2387)
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#define MT6338_AUDIO_TOP_CON1 (0x2388)
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#define MT6338_AUDIO_TOP_CON2 (0x2389)
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|
#define MT6338_AUDIO_TOP_CON3 (0x238a)
|
|
#define MT6338_AFE_TOP_CON0 (0x238b)
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#define MT6338_AFE_MON_DEBUG0 (0x238c)
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|
#define MT6338_AFE_MON_DEBUG1 (0x238d)
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|
#define MT6338_AFE_MTKAIF_MUX_CFG_H (0x238e)
|
|
#define MT6338_AFE_MTKAIF_MUX_CFG (0x238f)
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|
#define MT6338_AFE_SINEGEN_CON0 (0x2390)
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|
#define MT6338_AFE_SINEGEN_CON1 (0x2391)
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|
#define MT6338_AFE_SINEGEN_CON2 (0x2392)
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|
#define MT6338_AFE_SINEGEN_CON3 (0x2393)
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|
#define MT6338_AFE_SINEGEN_CON4 (0x2394)
|
|
#define MT6338_AFE_STF_CON0 (0x2395)
|
|
#define MT6338_AFE_STF_CON0_M (0x2396)
|
|
#define MT6338_AFE_STF_CON0_H (0x2397)
|
|
#define MT6338_AFE_STF_CON1 (0x2398)
|
|
#define MT6338_AFE_STF_COEFF (0x2399)
|
|
#define MT6338_AFE_STF_COEFF_M (0x239a)
|
|
#define MT6338_AFE_STF_COEFF_H (0x239b)
|
|
#define MT6338_AFE_STF_GAIN (0x239c)
|
|
#define MT6338_AFE_STF_GAIN_M (0x239d)
|
|
#define MT6338_AFE_STF_GAIN_H (0x239e)
|
|
#define MT6338_AFE_STF_COEFF_RD (0x239f)
|
|
#define MT6338_AFE_STF_MON (0x23a0)
|
|
#define MT6338_AFE_STF_MON_M (0x23a1)
|
|
#define MT6338_AFE_STF_MON_H (0x23a2)
|
|
#define MT6338_AFE_STF_MON_H1 (0x23a3)
|
|
#define MT6338_AFE_NCP_CFG0 (0x23a4)
|
|
#define MT6338_AFE_NCP_CFG1 (0x23a5)
|
|
#define MT6338_AFE_NCP_CFG2 (0x23a6)
|
|
#define MT6338_AFE_NCP_CFG3 (0x23a7)
|
|
#define MT6338_AFE_NCP_CFG4 (0x23a8)
|
|
#define MT6338_AFE_TOP_DEBUG0 (0x23a9)
|
|
#define MT6338_AFE_MTKAIF_IN_MUX_CFG (0x23aa)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_ID (0x2400)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_ID_H (0x2401)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_REV0 (0x2402)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_REV0_H (0x2403)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_DBI (0x2404)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_DBI_H (0x2405)
|
|
#define MT6338_AUDIO_DIG_2ND_DSN_DXI (0x2406)
|
|
#define MT6338_GENERAL_ASRC_EN_ON (0x2407)
|
|
#define MT6338_GASRC1_MODE (0x2408)
|
|
#define MT6338_GASRC2_MODE (0x2409)
|
|
#define MT6338_GASRC3_MODE (0x240a)
|
|
#define MT6338_GASRC4_MODE (0x240b)
|
|
#define MT6338_AFE_GASRC1_CON0 (0x240c)
|
|
#define MT6338_AFE_GASRC1_CON1 (0x240d)
|
|
#define MT6338_AFE_GASRC1_CON2 (0x240e)
|
|
#define MT6338_AFE_GASRC1_CON2_M (0x240f)
|
|
#define MT6338_AFE_GASRC1_CON2_H (0x2410)
|
|
#define MT6338_AFE_GASRC1_CON3 (0x2411)
|
|
#define MT6338_AFE_GASRC1_CON3_M (0x2412)
|
|
#define MT6338_AFE_GASRC1_CON3_H (0x2413)
|
|
#define MT6338_AFE_GASRC1_CON4 (0x2414)
|
|
#define MT6338_AFE_GASRC1_CON4_M (0x2415)
|
|
#define MT6338_AFE_GASRC1_CON4_H (0x2416)
|
|
#define MT6338_AFE_GASRC1_CON5 (0x2417)
|
|
#define MT6338_AFE_GASRC1_CON5_M (0x2418)
|
|
#define MT6338_AFE_GASRC1_CON5_H0 (0x2419)
|
|
#define MT6338_AFE_GASRC1_CON5_H1 (0x241a)
|
|
#define MT6338_AFE_GASRC1_CON6 (0x241b)
|
|
#define MT6338_AFE_GASRC1_CON6_M (0x241c)
|
|
#define MT6338_AFE_GASRC1_CON6_H (0x241d)
|
|
#define MT6338_AFE_GASRC1_CON7 (0x241e)
|
|
#define MT6338_AFE_GASRC1_CON7_M (0x241f)
|
|
#define MT6338_AFE_GASRC1_CON7_H (0x2420)
|
|
#define MT6338_AFE_GASRC1_CON8 (0x2421)
|
|
#define MT6338_AFE_GASRC1_CON8_M (0x2422)
|
|
#define MT6338_AFE_GASRC1_CON8_H (0x2423)
|
|
#define MT6338_AFE_GASRC1_CON9 (0x2424)
|
|
#define MT6338_AFE_GASRC1_CON9_M (0x2425)
|
|
#define MT6338_AFE_GASRC1_CON9_H (0x2426)
|
|
#define MT6338_AFE_GASRC1_CON10 (0x2427)
|
|
#define MT6338_AFE_GASRC1_CON10_M (0x2428)
|
|
#define MT6338_AFE_GASRC1_CON10_H (0x2429)
|
|
#define MT6338_AFE_GASRC1_CON11 (0x242a)
|
|
#define MT6338_AFE_GASRC1_CON11_H (0x242b)
|
|
#define MT6338_AFE_GASRC1_CON12 (0x242c)
|
|
#define MT6338_AFE_GASRC1_CON12_M (0x242d)
|
|
#define MT6338_AFE_GASRC1_CON12_H (0x242e)
|
|
#define MT6338_AFE_GASRC1_CON13 (0x242f)
|
|
#define MT6338_AFE_GASRC1_CON14 (0x2430)
|
|
#define MT6338_AFE_GASRC1_CON14_M (0x2431)
|
|
#define MT6338_AFE_GASRC1_CON14_H (0x2432)
|
|
#define MT6338_AFE_GASRC1_CON15 (0x2433)
|
|
#define MT6338_AFE_GASRC2_CON0 (0x2434)
|
|
#define MT6338_AFE_GASRC2_CON1 (0x2435)
|
|
#define MT6338_AFE_GASRC2_CON2 (0x2436)
|
|
#define MT6338_AFE_GASRC2_CON2_M (0x2437)
|
|
#define MT6338_AFE_GASRC2_CON2_H (0x2438)
|
|
#define MT6338_AFE_GASRC2_CON3 (0x2439)
|
|
#define MT6338_AFE_GASRC2_CON3_M (0x243a)
|
|
#define MT6338_AFE_GASRC2_CON3_H (0x243b)
|
|
#define MT6338_AFE_GASRC2_CON4 (0x243c)
|
|
#define MT6338_AFE_GASRC2_CON4_M (0x243d)
|
|
#define MT6338_AFE_GASRC2_CON4_H (0x243e)
|
|
#define MT6338_AFE_GASRC2_CON5 (0x243f)
|
|
#define MT6338_AFE_GASRC2_CON5_M (0x2440)
|
|
#define MT6338_AFE_GASRC2_CON5_H0 (0x2441)
|
|
#define MT6338_AFE_GASRC2_CON5_H1 (0x2442)
|
|
#define MT6338_AFE_GASRC2_CON6 (0x2443)
|
|
#define MT6338_AFE_GASRC2_CON6_M (0x2444)
|
|
#define MT6338_AFE_GASRC2_CON6_H (0x2445)
|
|
#define MT6338_AFE_GASRC2_CON7 (0x2446)
|
|
#define MT6338_AFE_GASRC2_CON7_M (0x2447)
|
|
#define MT6338_AFE_GASRC2_CON7_H (0x2448)
|
|
#define MT6338_AFE_GASRC2_CON8 (0x2449)
|
|
#define MT6338_AFE_GASRC2_CON8_M (0x244a)
|
|
#define MT6338_AFE_GASRC2_CON8_H (0x244b)
|
|
#define MT6338_AFE_GASRC2_CON9 (0x244c)
|
|
#define MT6338_AFE_GASRC2_CON9_M (0x244d)
|
|
#define MT6338_AFE_GASRC2_CON9_H (0x244e)
|
|
#define MT6338_AFE_GASRC2_CON10 (0x244f)
|
|
#define MT6338_AFE_GASRC2_CON10_M (0x2450)
|
|
#define MT6338_AFE_GASRC2_CON10_H (0x2451)
|
|
#define MT6338_AFE_GASRC2_CON11 (0x2452)
|
|
#define MT6338_AFE_GASRC2_CON11_H (0x2453)
|
|
#define MT6338_AFE_GASRC2_CON12 (0x2454)
|
|
#define MT6338_AFE_GASRC2_CON12_M (0x2455)
|
|
#define MT6338_AFE_GASRC2_CON12_H (0x2456)
|
|
#define MT6338_AFE_GASRC2_CON13 (0x2457)
|
|
#define MT6338_AFE_GASRC2_CON14 (0x2458)
|
|
#define MT6338_AFE_GASRC2_CON14_M (0x2459)
|
|
#define MT6338_AFE_GASRC2_CON14_H (0x245a)
|
|
#define MT6338_AFE_GASRC2_CON15 (0x245b)
|
|
#define MT6338_AFE_GASRC_CK_SEL (0x245c)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_ID (0x2480)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_ID_H (0x2481)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_REV0 (0x2482)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_REV0_H (0x2483)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_DBI (0x2484)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_DBI_H (0x2485)
|
|
#define MT6338_AUDIO_DIG_3RD_DSN_DXI (0x2486)
|
|
#define MT6338_AFE_GASRC3_CON0 (0x2487)
|
|
#define MT6338_AFE_GASRC3_CON1 (0x2488)
|
|
#define MT6338_AFE_GASRC3_CON2 (0x2489)
|
|
#define MT6338_AFE_GASRC3_CON2_M (0x248a)
|
|
#define MT6338_AFE_GASRC3_CON2_H (0x248b)
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#define MT6338_AFE_GASRC3_CON3 (0x248c)
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#define MT6338_AFE_GASRC3_CON3_M (0x248d)
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#define MT6338_AFE_GASRC3_CON3_H (0x248e)
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#define MT6338_AFE_GASRC3_CON4 (0x248f)
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#define MT6338_AFE_GASRC3_CON4_M (0x2490)
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#define MT6338_AFE_GASRC3_CON4_H (0x2491)
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#define MT6338_AFE_GASRC3_CON5 (0x2492)
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#define MT6338_AFE_GASRC3_CON5_M (0x2493)
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#define MT6338_AFE_GASRC3_CON5_H0 (0x2494)
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#define MT6338_AFE_GASRC3_CON5_H1 (0x2495)
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#define MT6338_AFE_GASRC3_CON6 (0x2496)
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#define MT6338_AFE_GASRC3_CON6_M (0x2497)
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#define MT6338_AFE_GASRC3_CON6_H (0x2498)
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#define MT6338_AFE_GASRC3_CON7 (0x2499)
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#define MT6338_AFE_GASRC3_CON7_M (0x249a)
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#define MT6338_AFE_GASRC3_CON7_H (0x249b)
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#define MT6338_AFE_GASRC3_CON8 (0x249c)
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#define MT6338_AFE_GASRC3_CON8_M (0x249d)
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#define MT6338_AFE_GASRC3_CON8_H (0x249e)
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#define MT6338_AFE_GASRC3_CON9 (0x249f)
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#define MT6338_AFE_GASRC3_CON9_M (0x24a0)
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#define MT6338_AFE_GASRC3_CON9_H (0x24a1)
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#define MT6338_AFE_GASRC3_CON10 (0x24a2)
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#define MT6338_AFE_GASRC3_CON10_M (0x24a3)
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#define MT6338_AFE_GASRC3_CON10_H (0x24a4)
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#define MT6338_AFE_GASRC3_CON11 (0x24a5)
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#define MT6338_AFE_GASRC3_CON11_H (0x24a6)
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#define MT6338_AFE_GASRC3_CON12 (0x24a7)
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#define MT6338_AFE_GASRC3_CON12_M (0x24a8)
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#define MT6338_AFE_GASRC3_CON12_H (0x24a9)
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#define MT6338_AFE_GASRC3_CON13 (0x24aa)
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#define MT6338_AFE_GASRC3_CON14 (0x24ab)
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#define MT6338_AFE_GASRC3_CON14_M (0x24ac)
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#define MT6338_AFE_GASRC3_CON14_H (0x24ad)
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#define MT6338_AFE_GASRC3_CON15 (0x24ae)
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#define MT6338_AFE_GASRC4_CON0 (0x24af)
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#define MT6338_AFE_GASRC4_CON1 (0x24b0)
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#define MT6338_AFE_GASRC4_CON2 (0x24b1)
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#define MT6338_AFE_GASRC4_CON2_M (0x24b2)
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#define MT6338_AFE_GASRC4_CON2_H (0x24b3)
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#define MT6338_AFE_GASRC4_CON3 (0x24b4)
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#define MT6338_AFE_GASRC4_CON3_M (0x24b5)
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#define MT6338_AFE_GASRC4_CON3_H (0x24b6)
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#define MT6338_AFE_GASRC4_CON4 (0x24b7)
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#define MT6338_AFE_GASRC4_CON4_M (0x24b8)
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#define MT6338_AFE_GASRC4_CON4_H (0x24b9)
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#define MT6338_AFE_GASRC4_CON5 (0x24ba)
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#define MT6338_AFE_GASRC4_CON5_M (0x24bb)
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#define MT6338_AFE_GASRC4_CON5_H0 (0x24bc)
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#define MT6338_AFE_GASRC4_CON5_H1 (0x24bd)
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#define MT6338_AFE_GASRC4_CON6 (0x24be)
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#define MT6338_AFE_GASRC4_CON6_M (0x24bf)
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#define MT6338_AFE_GASRC4_CON6_H (0x24c0)
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|
#define MT6338_AFE_GASRC4_CON7 (0x24c1)
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#define MT6338_AFE_GASRC4_CON7_M (0x24c2)
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|
#define MT6338_AFE_GASRC4_CON7_H (0x24c3)
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|
#define MT6338_AFE_GASRC4_CON8 (0x24c4)
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|
#define MT6338_AFE_GASRC4_CON8_M (0x24c5)
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|
#define MT6338_AFE_GASRC4_CON8_H (0x24c6)
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|
#define MT6338_AFE_GASRC4_CON9 (0x24c7)
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|
#define MT6338_AFE_GASRC4_CON9_M (0x24c8)
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|
#define MT6338_AFE_GASRC4_CON9_H (0x24c9)
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|
#define MT6338_AFE_GASRC4_CON10 (0x24ca)
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|
#define MT6338_AFE_GASRC4_CON10_M (0x24cb)
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|
#define MT6338_AFE_GASRC4_CON10_H (0x24cc)
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|
#define MT6338_AFE_GASRC4_CON11 (0x24cd)
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|
#define MT6338_AFE_GASRC4_CON11_H (0x24ce)
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|
#define MT6338_AFE_GASRC4_CON12 (0x24cf)
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|
#define MT6338_AFE_GASRC4_CON12_M (0x24d0)
|
|
#define MT6338_AFE_GASRC4_CON12_H (0x24d1)
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|
#define MT6338_AFE_GASRC4_CON13 (0x24d2)
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|
#define MT6338_AFE_GASRC4_CON14 (0x24d3)
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|
#define MT6338_AFE_GASRC4_CON14_M (0x24d4)
|
|
#define MT6338_AFE_GASRC4_CON14_H (0x24d5)
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|
#define MT6338_AFE_GASRC4_CON15 (0x24d6)
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|
#define MT6338_AUDIO_DIG_4TH_DSN_ID (0x2500)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_ID_H (0x2501)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_REV0 (0x2502)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_REV0_H (0x2503)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_DBI (0x2504)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_DBI_H (0x2505)
|
|
#define MT6338_AUDIO_DIG_4TH_DSN_DXI (0x2506)
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|
#define MT6338_AFE_ADDA_UL_DL_CON0_2 (0x2507)
|
|
#define MT6338_AFE_ADDA_UL_DL_CON0_1 (0x2508)
|
|
#define MT6338_AFE_ADDA_UL_DL_CON0_0 (0x2509)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON0_3 (0x250a)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON0_2 (0x250b)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON0_1 (0x250c)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON0_0 (0x250d)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON1_3 (0x250e)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON1_2 (0x250f)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON1_1 (0x2510)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON1_0 (0x2511)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON2_3 (0x2512)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON2_2 (0x2513)
|
|
#define MT6338_AFE_ADDA_UL_SRC_CON2_1 (0x2514)
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|
#define MT6338_AFE_ADDA_UL_SRC_CON2_0 (0x2515)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_02_01_3 (0x2516)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_02_01_2 (0x2517)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_02_01_1 (0x2518)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_02_01_0 (0x2519)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_04_03_3 (0x251a)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_04_03_2 (0x251b)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_04_03_1 (0x251c)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_04_03_0 (0x251d)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_06_05_3 (0x251e)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_06_05_2 (0x251f)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_06_05_1 (0x2520)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_06_05_0 (0x2521)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_08_07_3 (0x2522)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_08_07_2 (0x2523)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_08_07_1 (0x2524)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_08_07_0 (0x2525)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_10_09_3 (0x2526)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_10_09_2 (0x2527)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_10_09_1 (0x2528)
|
|
#define MT6338_AFE_ADDA_IIR_COEF_10_09_0 (0x2529)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_02_01_3 (0x252a)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_02_01_2 (0x252b)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_02_01_1 (0x252c)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_02_01_0 (0x252d)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_04_03_3 (0x252e)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_04_03_2 (0x252f)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_04_03_1 (0x2530)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_04_03_0 (0x2531)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_06_05_3 (0x2532)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_06_05_2 (0x2533)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_06_05_1 (0x2534)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_06_05_0 (0x2535)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_08_07_3 (0x2536)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_08_07_2 (0x2537)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_08_07_1 (0x2538)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_08_07_0 (0x2539)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_10_09_3 (0x253a)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_10_09_2 (0x253b)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_10_09_1 (0x253c)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_10_09_0 (0x253d)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_12_11_3 (0x253e)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_12_11_2 (0x253f)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_12_11_1 (0x2540)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_12_11_0 (0x2541)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_14_13_3 (0x2542)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_14_13_2 (0x2543)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_14_13_1 (0x2544)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_14_13_0 (0x2545)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_16_15_3 (0x2546)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_16_15_2 (0x2547)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_16_15_1 (0x2548)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_16_15_0 (0x2549)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_18_17_3 (0x254a)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_18_17_2 (0x254b)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_18_17_1 (0x254c)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_18_17_0 (0x254d)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_20_19_3 (0x254e)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_20_19_2 (0x254f)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_20_19_1 (0x2550)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_20_19_0 (0x2551)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_22_21_3 (0x2552)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_22_21_2 (0x2553)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_22_21_1 (0x2554)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_22_21_0 (0x2555)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_24_23_3 (0x2556)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_24_23_2 (0x2557)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_24_23_1 (0x2558)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_24_23_0 (0x2559)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_26_25_3 (0x255a)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_26_25_2 (0x255b)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_26_25_1 (0x255c)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_26_25_0 (0x255d)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_28_27_3 (0x255e)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_28_27_2 (0x255f)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_28_27_1 (0x2560)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_28_27_0 (0x2561)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_30_29_3 (0x2562)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_30_29_2 (0x2563)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_30_29_1 (0x2564)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_30_29_0 (0x2565)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_32_31_3 (0x2566)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_32_31_2 (0x2567)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_32_31_1 (0x2568)
|
|
#define MT6338_AFE_ADDA_ULCF_CFG_32_31_0 (0x2569)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON0_3 (0x256a)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON0_2 (0x256b)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON0_1 (0x256c)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON0_0 (0x256d)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON1_3 (0x256e)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON1_2 (0x256f)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON1_1 (0x2570)
|
|
#define MT6338_AFE_ADDA_UL_SRC_MON1_0 (0x2571)
|
|
#define MT6338_AFE_ADDA_SRC_DEBUG_1 (0x2572)
|
|
#define MT6338_AFE_ADDA_SRC_DEBUG_0 (0x2573)
|
|
#define MT6338_AFE_ADDA_SRC_DEBUG_MON0_1 (0x2574)
|
|
#define MT6338_AFE_ADDA_SRC_DEBUG_MON0_0 (0x2575)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON0_3 (0x2576)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON0_2 (0x2577)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON0_1 (0x2578)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON0_0 (0x2579)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON1_3 (0x257a)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON1_2 (0x257b)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON1_1 (0x257c)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON1_0 (0x257d)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_ID (0x2580)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_ID_H (0x2581)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_REV0 (0x2582)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_REV0_H (0x2583)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_DBI (0x2584)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_DBI_H (0x2585)
|
|
#define MT6338_AUDIO_DIG_5TH_DSN_DXI (0x2586)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON2_3 (0x2587)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON2_2 (0x2588)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON2_1 (0x2589)
|
|
#define MT6338_AFE_ADDA6_UL_SRC_CON2_0 (0x258a)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_02_01_3 (0x258b)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_02_01_2 (0x258c)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_02_01_1 (0x258d)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_02_01_0 (0x258e)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_04_03_3 (0x258f)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_04_03_2 (0x2590)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_04_03_1 (0x2591)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_04_03_0 (0x2592)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_06_05_3 (0x2593)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_06_05_2 (0x2594)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_06_05_1 (0x2595)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_06_05_0 (0x2596)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_08_07_3 (0x2597)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_08_07_2 (0x2598)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_08_07_1 (0x2599)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_08_07_0 (0x259a)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_10_09_3 (0x259b)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_10_09_2 (0x259c)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_10_09_1 (0x259d)
|
|
#define MT6338_AFE_ADDA6_IIR_COEF_10_09_0 (0x259e)
|
|
#define MT6338_AFE_ADDA6_ULCF_CFG_02_01_3 (0x259f)
|
|
#define MT6338_AFE_ADDA6_ULCF_CFG_02_01_2 (0x25a0)
|
|
#define MT6338_AFE_ADDA6_ULCF_CFG_02_01_1 (0x25a1)
|
|
#define MT6338_AFE_ADDA6_ULCF_CFG_02_01_0 (0x25a2)
|
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#define MT6338_AFE_ADDA6_ULCF_CFG_04_03_3 (0x25a3)
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#define MT6338_AFE_ADDA6_ULCF_CFG_04_03_2 (0x25a4)
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#define MT6338_AFE_ADDA6_ULCF_CFG_04_03_1 (0x25a5)
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#define MT6338_AFE_ADDA6_ULCF_CFG_04_03_0 (0x25a6)
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#define MT6338_AFE_ADDA6_ULCF_CFG_06_05_3 (0x25a7)
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#define MT6338_AFE_ADDA6_ULCF_CFG_06_05_2 (0x25a8)
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#define MT6338_AFE_ADDA6_ULCF_CFG_06_05_1 (0x25a9)
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#define MT6338_AFE_ADDA6_ULCF_CFG_06_05_0 (0x25aa)
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#define MT6338_AFE_ADDA6_ULCF_CFG_08_07_3 (0x25ab)
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#define MT6338_AFE_ADDA6_ULCF_CFG_08_07_2 (0x25ac)
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#define MT6338_AFE_ADDA6_ULCF_CFG_08_07_1 (0x25ad)
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#define MT6338_AFE_ADDA6_ULCF_CFG_08_07_0 (0x25ae)
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#define MT6338_AFE_ADDA6_ULCF_CFG_10_09_3 (0x25af)
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#define MT6338_AFE_ADDA6_ULCF_CFG_10_09_2 (0x25b0)
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#define MT6338_AFE_ADDA6_ULCF_CFG_10_09_1 (0x25b1)
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#define MT6338_AFE_ADDA6_ULCF_CFG_10_09_0 (0x25b2)
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#define MT6338_AFE_ADDA6_ULCF_CFG_12_11_3 (0x25b3)
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#define MT6338_AFE_ADDA6_ULCF_CFG_12_11_2 (0x25b4)
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#define MT6338_AFE_ADDA6_ULCF_CFG_12_11_1 (0x25b5)
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#define MT6338_AFE_ADDA6_ULCF_CFG_12_11_0 (0x25b6)
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#define MT6338_AFE_ADDA6_ULCF_CFG_14_13_3 (0x25b7)
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#define MT6338_AFE_ADDA6_ULCF_CFG_14_13_2 (0x25b8)
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#define MT6338_AFE_ADDA6_ULCF_CFG_14_13_1 (0x25b9)
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#define MT6338_AFE_ADDA6_ULCF_CFG_14_13_0 (0x25ba)
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#define MT6338_AFE_ADDA6_ULCF_CFG_16_15_3 (0x25bb)
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#define MT6338_AFE_ADDA6_ULCF_CFG_16_15_2 (0x25bc)
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#define MT6338_AFE_ADDA6_ULCF_CFG_16_15_1 (0x25bd)
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#define MT6338_AFE_ADDA6_ULCF_CFG_16_15_0 (0x25be)
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#define MT6338_AFE_ADDA6_ULCF_CFG_18_17_3 (0x25bf)
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#define MT6338_AFE_ADDA6_ULCF_CFG_18_17_2 (0x25c0)
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#define MT6338_AFE_ADDA6_ULCF_CFG_18_17_1 (0x25c1)
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#define MT6338_AFE_ADDA6_ULCF_CFG_18_17_0 (0x25c2)
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#define MT6338_AFE_ADDA6_ULCF_CFG_20_19_3 (0x25c3)
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#define MT6338_AFE_ADDA6_ULCF_CFG_20_19_2 (0x25c4)
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#define MT6338_AFE_ADDA6_ULCF_CFG_20_19_1 (0x25c5)
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#define MT6338_AFE_ADDA6_ULCF_CFG_20_19_0 (0x25c6)
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#define MT6338_AFE_ADDA6_ULCF_CFG_22_21_3 (0x25c7)
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#define MT6338_AFE_ADDA6_ULCF_CFG_22_21_2 (0x25c8)
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#define MT6338_AFE_ADDA6_ULCF_CFG_22_21_1 (0x25c9)
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#define MT6338_AFE_ADDA6_ULCF_CFG_22_21_0 (0x25ca)
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#define MT6338_AFE_ADDA6_ULCF_CFG_24_23_3 (0x25cb)
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#define MT6338_AFE_ADDA6_ULCF_CFG_24_23_2 (0x25cc)
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#define MT6338_AFE_ADDA6_ULCF_CFG_24_23_1 (0x25cd)
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#define MT6338_AFE_ADDA6_ULCF_CFG_24_23_0 (0x25ce)
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#define MT6338_AFE_ADDA6_ULCF_CFG_26_25_3 (0x25cf)
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#define MT6338_AFE_ADDA6_ULCF_CFG_26_25_2 (0x25d0)
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#define MT6338_AFE_ADDA6_ULCF_CFG_26_25_1 (0x25d1)
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#define MT6338_AFE_ADDA6_ULCF_CFG_26_25_0 (0x25d2)
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#define MT6338_AFE_ADDA6_ULCF_CFG_28_27_3 (0x25d3)
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#define MT6338_AFE_ADDA6_ULCF_CFG_28_27_2 (0x25d4)
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#define MT6338_AFE_ADDA6_ULCF_CFG_28_27_1 (0x25d5)
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#define MT6338_AFE_ADDA6_ULCF_CFG_28_27_0 (0x25d6)
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#define MT6338_AFE_ADDA6_ULCF_CFG_30_29_3 (0x25d7)
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#define MT6338_AFE_ADDA6_ULCF_CFG_30_29_2 (0x25d8)
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#define MT6338_AFE_ADDA6_ULCF_CFG_30_29_1 (0x25d9)
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#define MT6338_AFE_ADDA6_ULCF_CFG_30_29_0 (0x25da)
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#define MT6338_AFE_ADDA6_ULCF_CFG_32_31_3 (0x25db)
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#define MT6338_AFE_ADDA6_ULCF_CFG_32_31_2 (0x25dc)
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#define MT6338_AFE_ADDA6_ULCF_CFG_32_31_1 (0x25dd)
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#define MT6338_AFE_ADDA6_ULCF_CFG_32_31_0 (0x25de)
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#define MT6338_AFE_ADDA6_UL_SRC_MON0_3 (0x25df)
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#define MT6338_AFE_ADDA6_UL_SRC_MON0_2 (0x25e0)
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#define MT6338_AFE_ADDA6_UL_SRC_MON0_1 (0x25e1)
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#define MT6338_AFE_ADDA6_UL_SRC_MON0_0 (0x25e2)
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#define MT6338_AFE_ADDA6_UL_SRC_MON1_3 (0x25e3)
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#define MT6338_AFE_ADDA6_UL_SRC_MON1_2 (0x25e4)
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#define MT6338_AFE_ADDA6_UL_SRC_MON1_1 (0x25e5)
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#define MT6338_AFE_ADDA6_UL_SRC_MON1_0 (0x25e6)
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#define MT6338_AFE_ADDA6_SRC_DEBUG_1 (0x25e7)
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#define MT6338_AFE_ADDA6_SRC_DEBUG_0 (0x25e8)
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#define MT6338_AFE_ADDA6_SRC_DEBUG_MON0_1 (0x25e9)
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#define MT6338_AFE_ADDA6_SRC_DEBUG_MON0_0 (0x25ea)
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#define MT6338_AUDIO_DIG_6TH_DSN_ID (0x2600)
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#define MT6338_AUDIO_DIG_6TH_DSN_ID_H (0x2601)
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#define MT6338_AUDIO_DIG_6TH_DSN_REV0 (0x2602)
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#define MT6338_AUDIO_DIG_6TH_DSN_REV0_H (0x2603)
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#define MT6338_AUDIO_DIG_6TH_DSN_DBI (0x2604)
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#define MT6338_AUDIO_DIG_6TH_DSN_DBI_H (0x2605)
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#define MT6338_AUDIO_DIG_6TH_DSN_DXI (0x2606)
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#define MT6338_AFE_DL_NLE_CF_H (0x2607)
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#define MT6338_AFE_DL_NLE_CFG_L (0x2608)
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#define MT6338_AFE_DL_NLE_MON_H (0x2609)
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#define MT6338_AFE_DL_NLE_MON_L (0x260a)
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#define MT6338_AFUNC_AUD_CON0_H (0x260b)
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#define MT6338_AFUNC_AUD_CON0_L (0x260c)
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#define MT6338_AFUNC_AUD_CON1_H (0x260d)
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#define MT6338_AFUNC_AUD_CON1_L (0x260e)
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#define MT6338_AFUNC_AUD_CON2_H (0x260f)
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#define MT6338_AFUNC_AUD_CON2_L (0x2610)
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#define MT6338_AFUNC_AUD_CON3_H (0x2611)
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#define MT6338_AFUNC_AUD_CON4_H (0x2612)
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#define MT6338_AFUNC_AUD_CON4_L (0x2613)
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#define MT6338_AFUNC_AUD_CON5_H (0x2614)
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#define MT6338_AFUNC_AUD_CON5_L (0x2615)
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#define MT6338_AFUNC_AUD_CON6_H (0x2616)
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#define MT6338_AFUNC_AUD_CON6_L (0x2617)
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#define MT6338_AFUNC_AUD_CON7_H (0x2618)
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#define MT6338_AFUNC_AUD_CON7_L (0x2619)
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#define MT6338_AFUNC_AUD_CON8_H (0x261a)
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#define MT6338_AFUNC_AUD_CON8_L (0x261b)
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#define MT6338_AFUNC_AUD_CON9_H (0x261c)
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#define MT6338_AFUNC_AUD_CON9_L (0x261d)
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#define MT6338_AFUNC_AUD_CON10_H (0x261e)
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#define MT6338_AFUNC_AUD_CON10_L (0x261f)
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#define MT6338_AFUNC_AUD_CON11_H (0x2620)
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#define MT6338_AFUNC_AUD_CON11_L (0x2621)
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#define MT6338_AFUNC_AUD_CON12_H (0x2622)
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#define MT6338_AFUNC_AUD_CON12_L (0x2623)
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#define MT6338_AFUNC_AUD_MON0_H (0x2624)
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#define MT6338_AFUNC_AUD_MON0_L (0x2625)
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#define MT6338_AFUNC_AUD_MON1_H (0x2626)
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#define MT6338_AFUNC_AUD_MON1_L (0x2627)
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#define MT6338_AFE_ADC_ASYNC_FIFO_CFG (0x2628)
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#define MT6338_AFE_AMIC_ARRAY_CFG (0x2629)
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#define MT6338_AFUNC_AUD_CON13 (0x262a)
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#define MT6338_AFUNC_AUD_CON14 (0x262b)
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#define MT6338_AFUNC_AUD_CON15_H (0x262c)
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#define MT6338_AFUNC_AUD_CON15_L (0x262d)
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#define MT6338_AFUNC_AUD_CON16_H (0x262e)
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#define MT6338_AFUNC_AUD_CON16_L (0x262f)
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#define MT6338_AFUNC_AUD_CON17_H (0x2630)
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#define MT6338_AFUNC_AUD_CON17_L (0x2631)
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#define MT6338_AFUNC_AUD_CON18_H (0x2632)
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#define MT6338_AFUNC_AUD_CON18_L (0x2633)
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#define MT6338_AUDIO_DIG_7TH_DSN_ID (0x2680)
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|
#define MT6338_AUDIO_DIG_7TH_DSN_ID_H (0x2681)
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|
#define MT6338_AUDIO_DIG_7TH_DSN_REV0 (0x2682)
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#define MT6338_AUDIO_DIG_7TH_DSN_REV0_H (0x2683)
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#define MT6338_AUDIO_DIG_7TH_DSN_DBI (0x2684)
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#define MT6338_AUDIO_DIG_7TH_DSN_DBI_H (0x2685)
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#define MT6338_AUDIO_DIG_7TH_DSN_DXI (0x2686)
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#define MT6338_AFE_ADDA_DL_SRC_CON0_H (0x2687)
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#define MT6338_AFE_ADDA_DL_SRC_CON0_M (0x2688)
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#define MT6338_AFE_ADDA_DL_SRC_CON0_L (0x2689)
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#define MT6338_AFE_ADDA_DL_SRC_CON0 (0x268a)
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#define MT6338_AFE_ADDA_DL_SRC_CON1_H (0x268b)
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#define MT6338_AFE_ADDA_DL_SRC_CON1_M (0x268c)
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#define MT6338_AFE_ADDA_DL_SRC_CON1 (0x268d)
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#define MT6338_AFE_ADDA_DL_SRC_DEBUG_MON0_H (0x268e)
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|
#define MT6338_AFE_ADDA_DL_SRC_DEBUG_MON0 (0x268f)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON0_H (0x2690)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON0_M (0x2691)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON0_L (0x2692)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON0 (0x2693)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON1_H (0x2694)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON1_M (0x2695)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON1_L (0x2696)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON1 (0x2697)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON2_H (0x2698)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON2_M (0x2699)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON2_L (0x269a)
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|
#define MT6338_AFE_ADDA_DL_PREDIS_CON2 (0x269b)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON3_H (0x269c)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON3_M (0x269d)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON3_L (0x269e)
|
|
#define MT6338_AFE_ADDA_DL_PREDIS_CON3 (0x269f)
|
|
#define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON_H (0x26a0)
|
|
#define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON_L (0x26a1)
|
|
#define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON (0x26a2)
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|
#define MT6338_AFE_ADDA_DL_SDM_TEST_L (0x26a3)
|
|
#define MT6338_AFE_ADDA_DL_SDM_TEST (0x26a4)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_H (0x26a5)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_M (0x26a6)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_L (0x26a7)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG0 (0x26a8)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_H (0x26a9)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_M (0x26aa)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_L (0x26ab)
|
|
#define MT6338_AFE_ADDA_DL_DC_COMP_CFG1 (0x26ac)
|
|
#define MT6338_AFE_ADDA_DL_SDM_OUT_MON_H (0x26ad)
|
|
#define MT6338_AFE_ADDA_DL_SDM_OUT_MON_M (0x26ae)
|
|
#define MT6338_AFE_ADDA_DL_SDM_OUT_MON_L (0x26af)
|
|
#define MT6338_AFE_ADDA_DL_SDM_OUT_MON (0x26b0)
|
|
#define MT6338_AFE_ADDA_DL_SRC_LCH_MON_M (0x26b1)
|
|
#define MT6338_AFE_ADDA_DL_SRC_LCH_MON_L (0x26b2)
|
|
#define MT6338_AFE_ADDA_DL_SRC_LCH_MON (0x26b3)
|
|
#define MT6338_AFE_ADDA_DL_SRC_RCH_MON_M (0x26b4)
|
|
#define MT6338_AFE_ADDA_DL_SRC_RCH_MON_L (0x26b5)
|
|
#define MT6338_AFE_ADDA_DL_SRC_RCH_MON (0x26b6)
|
|
#define MT6338_AFE_ADDA_DL_SRC_DEBUG_L (0x26b7)
|
|
#define MT6338_AFE_ADDA_DL_SRC_DEBUG (0x26b8)
|
|
#define MT6338_AFE_ADDA_DL_SDM_DITHER_CON_M (0x26b9)
|
|
#define MT6338_AFE_ADDA_DL_SDM_DITHER_CON (0x26ba)
|
|
#define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_H (0x26bb)
|
|
#define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_M (0x26bc)
|
|
#define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_L (0x26bd)
|
|
#define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON (0x26be)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_H (0x26bf)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_M (0x26c0)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_L (0x26c1)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0 (0x26c2)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_H (0x26c3)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_M (0x26c4)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_L (0x26c5)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0 (0x26c6)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_H (0x26c7)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_M (0x26c8)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_L (0x26c9)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0 (0x26ca)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1_M (0x26cb)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1_L (0x26cc)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1 (0x26cd)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2_M (0x26ce)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2_L (0x26cf)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2 (0x26d0)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3_M (0x26d1)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3_L (0x26d2)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3 (0x26d3)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4_M (0x26d4)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4_L (0x26d5)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4 (0x26d6)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_H (0x26d7)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_M (0x26d8)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_L (0x26d9)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0 (0x26da)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1_M (0x26db)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1_L (0x26dc)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1 (0x26dd)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2_M (0x26de)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2_L (0x26df)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2 (0x26e0)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3_M (0x26e1)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3_L (0x26e2)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3 (0x26e3)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4_M (0x26e4)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4_L (0x26e5)
|
|
#define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4 (0x26e6)
|
|
#define MT6338_AUDIO_DIG_8TH_DSN_ID (0x2700)
|
|
#define MT6338_AUDIO_DIG_8TH_DSN_ID_H (0x2701)
|
|
#define MT6338_AUDIO_DIG_8TH_DSN_REV0 (0x2702)
|
|
#define MT6338_AUDIO_DIG_8TH_DSN_REV0_H (0x2703)
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#define MT6338_AUDIO_DIG_8TH_DSN_DBI (0x2704)
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#define MT6338_AUDIO_DIG_8TH_DSN_DBI_H (0x2705)
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#define MT6338_AUDIO_DIG_8TH_DSN_DXI (0x2706)
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#define MT6338_AFE_NLE_CFG_H (0x2707)
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#define MT6338_AFE_NLE_CFG (0x2708)
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#define MT6338_AFE_NLE_PRE_BUF_CFG_H (0x2709)
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#define MT6338_AFE_NLE_PRE_BUF_CFG_M (0x270a)
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#define MT6338_AFE_NLE_PRE_BUF_CFG_L (0x270b)
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#define MT6338_AFE_NLE_PRE_BUF_CFG (0x270c)
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#define MT6338_AFE_NLE_PWR_DET_LCH_CFG_H (0x270d)
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#define MT6338_AFE_NLE_PWR_DET_LCH_CFG_M (0x270e)
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#define MT6338_AFE_NLE_PWR_DET_LCH_CFG_L (0x270f)
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#define MT6338_AFE_NLE_PWR_DET_LCH_CFG (0x2710)
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#define MT6338_AFE_NLE_ZCD_LCH_CFG (0x2711)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_H (0x2712)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_M (0x2713)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_L (0x2714)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0 (0x2715)
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#define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_H (0x2716)
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#define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_M (0x2717)
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|
#define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_L (0x2718)
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#define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0 (0x2719)
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#define MT6338_AFE_NLE_PWR_DET_LCH_MON_L (0x271a)
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#define MT6338_AFE_NLE_PWR_DET_LCH_MON (0x271b)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_H (0x271c)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_M (0x271d)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_L (0x271e)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0 (0x271f)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_H (0x2720)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_M (0x2721)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_L (0x2722)
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#define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1 (0x2723)
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#define MT6338_AFE_NLE_LCH_MON0_H (0x2724)
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#define MT6338_AFE_NLE_LCH_MON0_M (0x2725)
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#define MT6338_AFE_NLE_LCH_MON0_L (0x2726)
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#define MT6338_AFE_NLE_LCH_MON0 (0x2727)
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#define MT6338_AFE_NLE_PWR_DET_RCH_CFG_H (0x2728)
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#define MT6338_AFE_NLE_PWR_DET_RCH_CFG_M (0x2729)
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#define MT6338_AFE_NLE_PWR_DET_RCH_CFG_L (0x272a)
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|
#define MT6338_AFE_NLE_PWR_DET_RCH_CFG (0x272b)
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|
#define MT6338_AFE_NLE_ZCD_RCH_CFG (0x272c)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_H (0x272d)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_M (0x272e)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_L (0x272f)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0 (0x2730)
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|
#define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_H (0x2731)
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|
#define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_M (0x2732)
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|
#define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_L (0x2733)
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|
#define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0 (0x2734)
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#define MT6338_AFE_NLE_PWR_DET_RCH_MON_L (0x2735)
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|
#define MT6338_AFE_NLE_PWR_DET_RCH_MON (0x2736)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_H (0x2737)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_M (0x2738)
|
|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_L (0x2739)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0 (0x273a)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_H (0x273b)
|
|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_M (0x273c)
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|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_L (0x273d)
|
|
#define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1 (0x273e)
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|
#define MT6338_AFE_NLE_RCH_MON0_H (0x273f)
|
|
#define MT6338_AFE_NLE_RCH_MON0_M (0x2740)
|
|
#define MT6338_AFE_NLE_RCH_MON0_L (0x2741)
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|
#define MT6338_AFE_NLE_RCH_MON0 (0x2742)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_H (0x2743)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_M (0x2744)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_L (0x2745)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0 (0x2746)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_H (0x2747)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_M (0x2748)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_L (0x2749)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1 (0x274a)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_H (0x274b)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_M (0x274c)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_L (0x274d)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2 (0x274e)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_H (0x274f)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_M (0x2750)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_L (0x2751)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3 (0x2752)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_H (0x2753)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_M (0x2754)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_L (0x2755)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4 (0x2756)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_H (0x2757)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_M (0x2758)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_L (0x2759)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5 (0x275a)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_H (0x275b)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_M (0x275c)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_L (0x275d)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6 (0x275e)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_H (0x275f)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_M (0x2760)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_L (0x2761)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7 (0x2762)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_H (0x2763)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_M (0x2764)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_L (0x2765)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0 (0x2766)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_H (0x2767)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_M (0x2768)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_L (0x2769)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1 (0x276a)
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#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_H (0x276b)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_M (0x276c)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_L (0x276d)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2 (0x276e)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_H (0x276f)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_M (0x2770)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_L (0x2771)
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|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3 (0x2772)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_H (0x2773)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_M (0x2774)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_L (0x2775)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4 (0x2776)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_H (0x2777)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_M (0x2778)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_L (0x2779)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5 (0x277a)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_H (0x277b)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_M (0x277c)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_L (0x277d)
|
|
#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6 (0x277e)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_ID (0x2780)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_ID_H (0x2781)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_REV0 (0x2782)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_REV0_H (0x2783)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_DBI (0x2784)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_DBI_H (0x2785)
|
|
#define MT6338_AUDIO_DIG_9TH_DSN_DXI (0x2786)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_H (0x2787)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_M (0x2788)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_L (0x2789)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON0 (0x278a)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON1_H (0x278b)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON1_M (0x278c)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_CON1 (0x278d)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_MON0_L (0x278e)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_MON0 (0x278f)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_H (0x2790)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_M (0x2791)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_L (0x2792)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0 (0x2793)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_H (0x2794)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_M (0x2795)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_L (0x2796)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1 (0x2797)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_H (0x2798)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_M (0x2799)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_L (0x279a)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2 (0x279b)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_H (0x279c)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_M (0x279d)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_L (0x279e)
|
|
#define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3 (0x279f)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_H (0x27a0)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_L (0x27a1)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON (0x27a2)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_TEST_L (0x27a3)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_TEST (0x27a4)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_H (0x27a5)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_M (0x27a6)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_L (0x27a7)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0 (0x27a8)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_H (0x27a9)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_M (0x27aa)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_L (0x27ab)
|
|
#define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1 (0x27ac)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_L (0x27ad)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG (0x27ae)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON_M (0x27af)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON_L (0x27b0)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON (0x27b1)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON_M (0x27b2)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON_L (0x27b3)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON (0x27b4)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_H (0x27b5)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_M (0x27b6)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_L (0x27b7)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON (0x27b8)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_DITHER_CON_M (0x27b9)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_DITHER_CON (0x27ba)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_H (0x27bb)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_M (0x27bc)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_L (0x27bd)
|
|
#define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON (0x27be)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_H (0x27bf)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_M (0x27c0)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_L (0x27c1)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0 (0x27c2)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_H (0x27c3)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_M (0x27c4)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_L (0x27c5)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0 (0x27c6)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_H (0x27c7)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_M (0x27c8)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_L (0x27c9)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0 (0x27ca)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_M (0x27cb)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_L (0x27cc)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1 (0x27cd)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_M (0x27ce)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_L (0x27cf)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2 (0x27d0)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_M (0x27d1)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_L (0x27d2)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3 (0x27d3)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_M (0x27d4)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_L (0x27d5)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4 (0x27d6)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_H (0x27d7)
|
|
#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_M (0x27d8)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_L (0x27d9)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0 (0x27da)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_M (0x27db)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_L (0x27dc)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1 (0x27dd)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_M (0x27de)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_L (0x27df)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2 (0x27e0)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_M (0x27e1)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_L (0x27e2)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3 (0x27e3)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_M (0x27e4)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_L (0x27e5)
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#define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4 (0x27e6)
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#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_H (0x27e7)
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#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_M (0x27e8)
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#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_L (0x27e9)
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#define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7 (0x27ea)
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#define MT6338_AFE_NLE_D2A_DEBUG_H (0x27eb)
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#define MT6338_AFE_NLE_D2A_DEBUG_M (0x27ec)
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#define MT6338_AFE_NLE_D2A_DEBUG_L (0x27ed)
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#define MT6338_AFE_NLE_D2A_DEBUG (0x27ee)
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#define MT6338_AUDIO_DIG_10TH_DSN_ID (0x2800)
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#define MT6338_AUDIO_DIG_10TH_DSN_ID_H (0x2801)
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#define MT6338_AUDIO_DIG_10TH_DSN_REV0 (0x2802)
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#define MT6338_AUDIO_DIG_10TH_DSN_REV0_H (0x2803)
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#define MT6338_AUDIO_DIG_10TH_DSN_DBI (0x2804)
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#define MT6338_AUDIO_DIG_10TH_DSN_DBI_H (0x2805)
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#define MT6338_AUDIO_DIG_10TH_DSN_DXI (0x2806)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_H (0x2807)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_M (0x2808)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_L (0x2809)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG (0x280a)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H (0x280b)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M (0x280c)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L (0x280d)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG (0x280e)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H (0x280f)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M (0x2810)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L (0x2811)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG (0x2812)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H (0x2813)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M (0x2814)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L (0x2815)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG (0x2816)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H (0x2817)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M (0x2818)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L (0x2819)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG (0x281a)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H (0x281b)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M (0x281c)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L (0x281d)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG (0x281e)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H (0x281f)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M (0x2820)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L (0x2821)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG (0x2822)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H (0x2823)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M (0x2824)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L (0x2825)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG (0x2826)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H (0x2827)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M (0x2828)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L (0x2829)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG (0x282a)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H (0x282b)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M (0x282c)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L (0x282d)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG (0x282e)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H (0x282f)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M (0x2830)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L (0x2831)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG (0x2832)
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#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H (0x2833)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M (0x2834)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L (0x2835)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG (0x2836)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H (0x2837)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M (0x2838)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L (0x2839)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG (0x283a)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H (0x283b)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M (0x283c)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L (0x283d)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG (0x283e)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H (0x283f)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M (0x2840)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L (0x2841)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG (0x2842)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H (0x2843)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M (0x2844)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L (0x2845)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG (0x2846)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H (0x2847)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M (0x2848)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L (0x2849)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG (0x284a)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H (0x284b)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M (0x284c)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L (0x284d)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG (0x284e)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H (0x284f)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M (0x2850)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L (0x2851)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG (0x2852)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H (0x2853)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M (0x2854)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L (0x2855)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG (0x2856)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H (0x2857)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M (0x2858)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L (0x2859)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG (0x285a)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H (0x285b)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M (0x285c)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L (0x285d)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG (0x285e)
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|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H (0x285f)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M (0x2860)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L (0x2861)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG (0x2862)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H (0x2863)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M (0x2864)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L (0x2865)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG (0x2866)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H (0x2867)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M (0x2868)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L (0x2869)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG (0x286a)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H (0x286b)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M (0x286c)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L (0x286d)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG (0x286e)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H (0x286f)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M (0x2870)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L (0x2871)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG (0x2872)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H (0x2873)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M (0x2874)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L (0x2875)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG (0x2876)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H (0x2877)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M (0x2878)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L (0x2879)
|
|
#define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG (0x287a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_H (0x287b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_M (0x287c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_L (0x287d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG (0x287e)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_ID (0x2880)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_ID_H (0x2881)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_REV0 (0x2882)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_REV0_H (0x2883)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_DBI (0x2884)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_DBI_H (0x2885)
|
|
#define MT6338_AUDIO_DIG_11TH_DSN_DXI (0x2886)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_H (0x2887)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_M (0x2888)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_L (0x2889)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG (0x288a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_H (0x288b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_M (0x288c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_L (0x288d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG (0x288e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_H (0x288f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_M (0x2890)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_L (0x2891)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG (0x2892)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_H (0x2893)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_M (0x2894)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_L (0x2895)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG (0x2896)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_H (0x2897)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_M (0x2898)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_L (0x2899)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG (0x289a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_H (0x289b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_M (0x289c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_L (0x289d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG (0x289e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_H (0x289f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_M (0x28a0)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_L (0x28a1)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG (0x28a2)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_H (0x28a3)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_M (0x28a4)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_L (0x28a5)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG (0x28a6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_H (0x28a7)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_M (0x28a8)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_L (0x28a9)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG (0x28aa)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_H (0x28ab)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_M (0x28ac)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_L (0x28ad)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG (0x28ae)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_H (0x28af)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_M (0x28b0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_L (0x28b1)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG (0x28b2)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_H (0x28b3)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_M (0x28b4)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_L (0x28b5)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG (0x28b6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_H (0x28b7)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_M (0x28b8)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_L (0x28b9)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG (0x28ba)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_H (0x28bb)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_M (0x28bc)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_L (0x28bd)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG (0x28be)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_H (0x28bf)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_M (0x28c0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_L (0x28c1)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG (0x28c2)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_H (0x28c3)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_M (0x28c4)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_L (0x28c5)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG (0x28c6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_H (0x28c7)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_M (0x28c8)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_L (0x28c9)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG (0x28ca)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_H (0x28cb)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_M (0x28cc)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_L (0x28cd)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG (0x28ce)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_H (0x28cf)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_M (0x28d0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_L (0x28d1)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG (0x28d2)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_H (0x28d3)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_M (0x28d4)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_L (0x28d5)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG (0x28d6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_H (0x28d7)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_M (0x28d8)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_L (0x28d9)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG (0x28da)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_H (0x28db)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_M (0x28dc)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_L (0x28dd)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG (0x28de)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_H (0x28df)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_M (0x28e0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_L (0x28e1)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG (0x28e2)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_H (0x28e3)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_M (0x28e4)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_L (0x28e5)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG (0x28e6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_H (0x28e7)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_M (0x28e8)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_L (0x28e9)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG (0x28ea)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_H (0x28eb)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_M (0x28ec)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_L (0x28ed)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG (0x28ee)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_H (0x28ef)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_M (0x28f0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_L (0x28f1)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG (0x28f2)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_H (0x28f3)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_M (0x28f4)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_L (0x28f5)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG (0x28f6)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_H (0x28f7)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_M (0x28f8)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_L (0x28f9)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG (0x28fa)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_H (0x28fb)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_M (0x28fc)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_L (0x28fd)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG (0x28fe)
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#define MT6338_AUDIO_DIG_12TH_DSN_ID (0x2900)
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#define MT6338_AUDIO_DIG_12TH_DSN_ID_H (0x2901)
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#define MT6338_AUDIO_DIG_12TH_DSN_REV0 (0x2902)
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#define MT6338_AUDIO_DIG_12TH_DSN_REV0_H (0x2903)
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#define MT6338_AUDIO_DIG_12TH_DSN_DBI (0x2904)
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#define MT6338_AUDIO_DIG_12TH_DSN_DBI_H (0x2905)
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#define MT6338_AUDIO_DIG_12TH_DSN_DXI (0x2906)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_H (0x2907)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_M (0x2908)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_L (0x2909)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG (0x290a)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_H (0x290b)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_M (0x290c)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_L (0x290d)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG (0x290e)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_H (0x290f)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_M (0x2910)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_L (0x2911)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG (0x2912)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_H (0x2913)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_M (0x2914)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_L (0x2915)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG (0x2916)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_H (0x2917)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_M (0x2918)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_L (0x2919)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG (0x291a)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_H (0x291b)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_M (0x291c)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_L (0x291d)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG (0x291e)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_H (0x291f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_M (0x2920)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_L (0x2921)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG (0x2922)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_H (0x2923)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_M (0x2924)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_L (0x2925)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG (0x2926)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_H (0x2927)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_M (0x2928)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_L (0x2929)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG (0x292a)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_H (0x292b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_M (0x292c)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_L (0x292d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG (0x292e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_H (0x292f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_M (0x2930)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_L (0x2931)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG (0x2932)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_H (0x2933)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_M (0x2934)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_L (0x2935)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG (0x2936)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_H (0x2937)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_M (0x2938)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_L (0x2939)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG (0x293a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_H (0x293b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_M (0x293c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_L (0x293d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG (0x293e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_H (0x293f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_M (0x2940)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_L (0x2941)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG (0x2942)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_H (0x2943)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_M (0x2944)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_L (0x2945)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG (0x2946)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_H (0x2947)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_M (0x2948)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_L (0x2949)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG (0x294a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_H (0x294b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_M (0x294c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_L (0x294d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG (0x294e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_H (0x294f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_M (0x2950)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_L (0x2951)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG (0x2952)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_H (0x2953)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_M (0x2954)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_L (0x2955)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG (0x2956)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_H (0x2957)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_M (0x2958)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_L (0x2959)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG (0x295a)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_H (0x295b)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_M (0x295c)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_L (0x295d)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG (0x295e)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_H (0x295f)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_M (0x2960)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_L (0x2961)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG (0x2962)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_H (0x2963)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_M (0x2964)
|
|
#define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_L (0x2965)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG (0x2966)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_H (0x2967)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_M (0x2968)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_L (0x2969)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG (0x296a)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_H (0x296b)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_M (0x296c)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_L (0x296d)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG (0x296e)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_H (0x296f)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_M (0x2970)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_L (0x2971)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG (0x2972)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_H (0x2973)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_M (0x2974)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_L (0x2975)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG (0x2976)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_H (0x2977)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_M (0x2978)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_L (0x2979)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG (0x297a)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_H (0x297b)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_M (0x297c)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_L (0x297d)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG (0x297e)
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#define MT6338_AUDIO_DIG_13TH_DSN_ID (0x2980)
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#define MT6338_AUDIO_DIG_13TH_DSN_ID_H (0x2981)
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#define MT6338_AUDIO_DIG_13TH_DSN_REV0 (0x2982)
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#define MT6338_AUDIO_DIG_13TH_DSN_REV0_H (0x2983)
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#define MT6338_AUDIO_DIG_13TH_DSN_DBI (0x2984)
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#define MT6338_AUDIO_DIG_13TH_DSN_DBI_H (0x2985)
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#define MT6338_AUDIO_DIG_13TH_DSN_DXI (0x2986)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_H (0x2987)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_M (0x2988)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_L (0x2989)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG (0x298a)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_H (0x298b)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_M (0x298c)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_L (0x298d)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG (0x298e)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_H (0x298f)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_M (0x2990)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_L (0x2991)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG (0x2992)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_H (0x2993)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_M (0x2994)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_L (0x2995)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG (0x2996)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_H (0x2997)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_M (0x2998)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_L (0x2999)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG (0x299a)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_H (0x299b)
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|
#define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_M (0x299c)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_L (0x299d)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG (0x299e)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_H (0x299f)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_M (0x29a0)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_L (0x29a1)
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#define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG (0x29a2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H (0x29a3)
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|
#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M (0x29a4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L (0x29a5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG (0x29a6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H (0x29a7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M (0x29a8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L (0x29a9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG (0x29aa)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H (0x29ab)
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|
#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M (0x29ac)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L (0x29ad)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG (0x29ae)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H (0x29af)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M (0x29b0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L (0x29b1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG (0x29b2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H (0x29b3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M (0x29b4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L (0x29b5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG (0x29b6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H (0x29b7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M (0x29b8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L (0x29b9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG (0x29ba)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H (0x29bb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M (0x29bc)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L (0x29bd)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG (0x29be)
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#define MT6338_AUDIO_DIG_14TH_DSN_ID (0x2a00)
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#define MT6338_AUDIO_DIG_14TH_DSN_ID_H (0x2a01)
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#define MT6338_AUDIO_DIG_14TH_DSN_REV0 (0x2a02)
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#define MT6338_AUDIO_DIG_14TH_DSN_REV0_H (0x2a03)
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#define MT6338_AUDIO_DIG_14TH_DSN_DBI (0x2a04)
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#define MT6338_AUDIO_DIG_14TH_DSN_DBI_H (0x2a05)
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#define MT6338_AUDIO_DIG_14TH_DSN_DXI (0x2a06)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_H (0x2a07)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_M (0x2a08)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_L (0x2a09)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG (0x2a0a)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H (0x2a0b)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M (0x2a0c)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L (0x2a0d)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG (0x2a0e)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H (0x2a0f)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M (0x2a10)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L (0x2a11)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG (0x2a12)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H (0x2a13)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M (0x2a14)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L (0x2a15)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG (0x2a16)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H (0x2a17)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M (0x2a18)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L (0x2a19)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG (0x2a1a)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H (0x2a1b)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M (0x2a1c)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L (0x2a1d)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG (0x2a1e)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H (0x2a1f)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M (0x2a20)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L (0x2a21)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG (0x2a22)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H (0x2a23)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M (0x2a24)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L (0x2a25)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG (0x2a26)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H (0x2a27)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M (0x2a28)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L (0x2a29)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG (0x2a2a)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H (0x2a2b)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M (0x2a2c)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L (0x2a2d)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG (0x2a2e)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H (0x2a2f)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M (0x2a30)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L (0x2a31)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG (0x2a32)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H (0x2a33)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M (0x2a34)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L (0x2a35)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG (0x2a36)
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|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H (0x2a37)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M (0x2a38)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L (0x2a39)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG (0x2a3a)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H (0x2a3b)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M (0x2a3c)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L (0x2a3d)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG (0x2a3e)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H (0x2a3f)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M (0x2a40)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L (0x2a41)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG (0x2a42)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H (0x2a43)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M (0x2a44)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L (0x2a45)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG (0x2a46)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H (0x2a47)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M (0x2a48)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L (0x2a49)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG (0x2a4a)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H (0x2a4b)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M (0x2a4c)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L (0x2a4d)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG (0x2a4e)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H (0x2a4f)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M (0x2a50)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L (0x2a51)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG (0x2a52)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H (0x2a53)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M (0x2a54)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L (0x2a55)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG (0x2a56)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H (0x2a57)
|
|
#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M (0x2a58)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L (0x2a59)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG (0x2a5a)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H (0x2a5b)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M (0x2a5c)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L (0x2a5d)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG (0x2a5e)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H (0x2a5f)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M (0x2a60)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L (0x2a61)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG (0x2a62)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H (0x2a63)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M (0x2a64)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L (0x2a65)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG (0x2a66)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H (0x2a67)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M (0x2a68)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L (0x2a69)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG (0x2a6a)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H (0x2a6b)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M (0x2a6c)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L (0x2a6d)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG (0x2a6e)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H (0x2a6f)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M (0x2a70)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L (0x2a71)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG (0x2a72)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H (0x2a73)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M (0x2a74)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L (0x2a75)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG (0x2a76)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H (0x2a77)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M (0x2a78)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L (0x2a79)
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#define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG (0x2a7a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H (0x2a7b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M (0x2a7c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L (0x2a7d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG (0x2a7e)
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#define MT6338_AUDIO_DIG_15TH_DSN_ID (0x2a80)
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#define MT6338_AUDIO_DIG_15TH_DSN_ID_H (0x2a81)
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#define MT6338_AUDIO_DIG_15TH_DSN_REV0 (0x2a82)
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#define MT6338_AUDIO_DIG_15TH_DSN_REV0_H (0x2a83)
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#define MT6338_AUDIO_DIG_15TH_DSN_DBI (0x2a84)
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#define MT6338_AUDIO_DIG_15TH_DSN_DBI_H (0x2a85)
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#define MT6338_AUDIO_DIG_15TH_DSN_DXI (0x2a86)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H (0x2a87)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M (0x2a88)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L (0x2a89)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG (0x2a8a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H (0x2a8b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M (0x2a8c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L (0x2a8d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG (0x2a8e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H (0x2a8f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M (0x2a90)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L (0x2a91)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG (0x2a92)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H (0x2a93)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M (0x2a94)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L (0x2a95)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG (0x2a96)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H (0x2a97)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M (0x2a98)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L (0x2a99)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG (0x2a9a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H (0x2a9b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M (0x2a9c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L (0x2a9d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG (0x2a9e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H (0x2a9f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M (0x2aa0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L (0x2aa1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG (0x2aa2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H (0x2aa3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M (0x2aa4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L (0x2aa5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG (0x2aa6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H (0x2aa7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M (0x2aa8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L (0x2aa9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG (0x2aaa)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H (0x2aab)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M (0x2aac)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L (0x2aad)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG (0x2aae)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H (0x2aaf)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M (0x2ab0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L (0x2ab1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG (0x2ab2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H (0x2ab3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M (0x2ab4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L (0x2ab5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG (0x2ab6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H (0x2ab7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M (0x2ab8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L (0x2ab9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG (0x2aba)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H (0x2abb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M (0x2abc)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L (0x2abd)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG (0x2abe)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H (0x2abf)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M (0x2ac0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L (0x2ac1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG (0x2ac2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H (0x2ac3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M (0x2ac4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L (0x2ac5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG (0x2ac6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H (0x2ac7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M (0x2ac8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L (0x2ac9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG (0x2aca)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H (0x2acb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M (0x2acc)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L (0x2acd)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG (0x2ace)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H (0x2acf)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M (0x2ad0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L (0x2ad1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG (0x2ad2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H (0x2ad3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M (0x2ad4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L (0x2ad5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG (0x2ad6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H (0x2ad7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M (0x2ad8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L (0x2ad9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG (0x2ada)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H (0x2adb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M (0x2adc)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L (0x2add)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG (0x2ade)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H (0x2adf)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M (0x2ae0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L (0x2ae1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG (0x2ae2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H (0x2ae3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M (0x2ae4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L (0x2ae5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG (0x2ae6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H (0x2ae7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M (0x2ae8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L (0x2ae9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG (0x2aea)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H (0x2aeb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M (0x2aec)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L (0x2aed)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG (0x2aee)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H (0x2aef)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M (0x2af0)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L (0x2af1)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG (0x2af2)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H (0x2af3)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M (0x2af4)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L (0x2af5)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG (0x2af6)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H (0x2af7)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M (0x2af8)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L (0x2af9)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG (0x2afa)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H (0x2afb)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M (0x2afc)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L (0x2afd)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG (0x2afe)
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#define MT6338_AUDIO_DIG_16TH_DSN_ID (0x2b00)
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#define MT6338_AUDIO_DIG_16TH_DSN_ID_H (0x2b01)
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#define MT6338_AUDIO_DIG_16TH_DSN_REV0 (0x2b02)
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#define MT6338_AUDIO_DIG_16TH_DSN_REV0_H (0x2b03)
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#define MT6338_AUDIO_DIG_16TH_DSN_DBI (0x2b04)
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#define MT6338_AUDIO_DIG_16TH_DSN_DBI_H (0x2b05)
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#define MT6338_AUDIO_DIG_16TH_DSN_DXI (0x2b06)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H (0x2b07)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M (0x2b08)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L (0x2b09)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG (0x2b0a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H (0x2b0b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M (0x2b0c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L (0x2b0d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG (0x2b0e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H (0x2b0f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M (0x2b10)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L (0x2b11)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG (0x2b12)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H (0x2b13)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M (0x2b14)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L (0x2b15)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG (0x2b16)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H (0x2b17)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M (0x2b18)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L (0x2b19)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG (0x2b1a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H (0x2b1b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M (0x2b1c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L (0x2b1d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG (0x2b1e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H (0x2b1f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M (0x2b20)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L (0x2b21)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG (0x2b22)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H (0x2b23)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M (0x2b24)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L (0x2b25)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG (0x2b26)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H (0x2b27)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M (0x2b28)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L (0x2b29)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG (0x2b2a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H (0x2b2b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M (0x2b2c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L (0x2b2d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG (0x2b2e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H (0x2b2f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M (0x2b30)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L (0x2b31)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG (0x2b32)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H (0x2b33)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M (0x2b34)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L (0x2b35)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG (0x2b36)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H (0x2b37)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M (0x2b38)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L (0x2b39)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG (0x2b3a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H (0x2b3b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M (0x2b3c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L (0x2b3d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG (0x2b3e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H (0x2b3f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M (0x2b40)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L (0x2b41)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG (0x2b42)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H (0x2b43)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M (0x2b44)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L (0x2b45)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG (0x2b46)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H (0x2b47)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M (0x2b48)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L (0x2b49)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG (0x2b4a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H (0x2b4b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M (0x2b4c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L (0x2b4d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG (0x2b4e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H (0x2b4f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M (0x2b50)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L (0x2b51)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG (0x2b52)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H (0x2b53)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M (0x2b54)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L (0x2b55)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG (0x2b56)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H (0x2b57)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M (0x2b58)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L (0x2b59)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG (0x2b5a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H (0x2b5b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M (0x2b5c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L (0x2b5d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG (0x2b5e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H (0x2b5f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M (0x2b60)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L (0x2b61)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG (0x2b62)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H (0x2b63)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M (0x2b64)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L (0x2b65)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG (0x2b66)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H (0x2b67)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M (0x2b68)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L (0x2b69)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG (0x2b6a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H (0x2b6b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M (0x2b6c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L (0x2b6d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG (0x2b6e)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H (0x2b6f)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M (0x2b70)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L (0x2b71)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG (0x2b72)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H (0x2b73)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M (0x2b74)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L (0x2b75)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG (0x2b76)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H (0x2b77)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M (0x2b78)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L (0x2b79)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG (0x2b7a)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H (0x2b7b)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M (0x2b7c)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L (0x2b7d)
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#define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG (0x2b7e)
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#define MT6338_AUDIO_DIG_17TH_DSN_ID (0x2b80)
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#define MT6338_AUDIO_DIG_17TH_DSN_ID_H (0x2b81)
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#define MT6338_AUDIO_DIG_17TH_DSN_REV0 (0x2b82)
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#define MT6338_AUDIO_DIG_17TH_DSN_REV0_H (0x2b83)
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#define MT6338_AUDIO_DIG_17TH_DSN_DBI (0x2b84)
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#define MT6338_AUDIO_DIG_17TH_DSN_DBI_H (0x2b85)
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#define MT6338_AUDIO_DIG_17TH_DSN_DXI (0x2b86)
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#define MT6338_AUDIO_VAD_PBUF_MON_SEL (0x2b87)
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#define MT6338_AUDIO_VAD_PBUF_MON_L (0x2b88)
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#define MT6338_AUDIO_VAD_PBUF_MON_H (0x2b89)
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#define MT6338_AUDIO_VAD_PBUF_CON0 (0x2b8a)
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#define MT6338_AUDIO_VAD_PBUF_CON1 (0x2b8b)
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#define MT6338_AUDIO_VAD_PBUF_CON2_L (0x2b8c)
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#define MT6338_AUDIO_VAD_PBUF_CON2_H (0x2b8d)
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#define MT6338_AUDIO_VAD_PBUF_CON3_L (0x2b8e)
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#define MT6338_AUDIO_VAD_PBUF_CON3_H (0x2b8f)
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#define MT6338_AUDIO_VAD_PBUF_CON4_L (0x2b90)
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#define MT6338_AUDIO_VAD_PBUF_CON4_H (0x2b91)
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#define MT6338_AUDIO_VAD_PBUF_CON5_L (0x2b92)
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#define MT6338_AUDIO_VAD_PBUF_CON5_H (0x2b93)
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#define MT6338_AUDIO_VAD_PBUF_CON6_L (0x2b94)
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#define MT6338_AUDIO_VAD_PBUF_CON6_H (0x2b95)
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#define MT6338_AUDIO_VAD_PBUF_WPTR_MON_L (0x2b96)
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#define MT6338_AUDIO_VAD_PBUF_WPTR_MON_H (0x2b97)
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#define MT6338_AUDIO_VAD_PBUF_RPTR_MON_L (0x2b98)
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#define MT6338_AUDIO_VAD_PBUF_RPTR_MON_H (0x2b99)
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#define MT6338_AUDIO_VAD_PBUF_RSV_L (0x2b9a)
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#define MT6338_AUDIO_VAD_PBUF_RSV_H (0x2b9b)
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#define MT6338_AFE_VOW_TOP_CON0 (0x2b9c)
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#define MT6338_AFE_VOW_TOP_CON1 (0x2b9d)
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#define MT6338_AFE_VOW_TOP_CON2 (0x2b9e)
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#define MT6338_AFE_VOW_TOP_CON3 (0x2b9f)
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#define MT6338_AFE_VOW_TOP_CON4 (0x2ba0)
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#define MT6338_AFE_VOW_TOP_CON5 (0x2ba1)
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#define MT6338_AFE_VOW_TOP_CON6 (0x2ba2)
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#define MT6338_AFE_VOW_TOP_CON7 (0x2ba3)
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#define MT6338_AFE_VOW_TOP_CON8 (0x2ba4)
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#define MT6338_AFE_VOW_TOP_CON9 (0x2ba5)
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#define MT6338_AFE_VOW_TOP_CON10 (0x2ba6)
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#define MT6338_AFE_VOW_TOP_CON11 (0x2ba7)
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|
#define MT6338_AFE_VOW_VAD_CFG0 (0x2ba8)
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#define MT6338_AFE_VOW_VAD_CFG1 (0x2ba9)
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#define MT6338_AFE_VOW_VAD_CFG2 (0x2baa)
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#define MT6338_AFE_VOW_VAD_CFG3 (0x2bab)
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#define MT6338_AFE_VOW_VAD_CFG4 (0x2bac)
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#define MT6338_AFE_VOW_VAD_CFG5 (0x2bad)
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#define MT6338_AFE_VOW_VAD_CFG6 (0x2bae)
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#define MT6338_AFE_VOW_VAD_CFG7 (0x2baf)
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#define MT6338_AFE_VOW_VAD_CFG8 (0x2bb0)
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|
#define MT6338_AFE_VOW_VAD_CFG9 (0x2bb1)
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#define MT6338_AFE_VOW_VAD_CFG10 (0x2bb2)
|
|
#define MT6338_AFE_VOW_VAD_CFG11 (0x2bb3)
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|
#define MT6338_AFE_VOW_VAD_CFG12 (0x2bb4)
|
|
#define MT6338_AFE_VOW_VAD_CFG13 (0x2bb5)
|
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#define MT6338_AFE_VOW_VAD_CFG14 (0x2bb6)
|
|
#define MT6338_AFE_VOW_VAD_CFG15 (0x2bb7)
|
|
#define MT6338_AFE_VOW_VAD_CFG16 (0x2bb8)
|
|
#define MT6338_AFE_VOW_VAD_CFG17 (0x2bb9)
|
|
#define MT6338_AFE_VOW_VAD_CFG18 (0x2bba)
|
|
#define MT6338_AFE_VOW_VAD_CFG19 (0x2bbb)
|
|
#define MT6338_AFE_VOW_VAD_CFG20 (0x2bbc)
|
|
#define MT6338_AFE_VOW_VAD_CFG21 (0x2bbd)
|
|
#define MT6338_AFE_VOW_VAD_CFG22 (0x2bbe)
|
|
#define MT6338_AFE_VOW_VAD_CFG23 (0x2bbf)
|
|
#define MT6338_AFE_VOW_VAD_CFG24 (0x2bc0)
|
|
#define MT6338_AFE_VOW_VAD_CFG25 (0x2bc1)
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|
#define MT6338_AFE_VOW_VAD_CFG26 (0x2bc2)
|
|
#define MT6338_AFE_VOW_VAD_CFG27 (0x2bc3)
|
|
#define MT6338_AFE_VOW_VAD_CFG28 (0x2bc4)
|
|
#define MT6338_AFE_VOW_VAD_CFG29 (0x2bc5)
|
|
#define MT6338_AFE_VOW_VAD_CFG30 (0x2bc6)
|
|
#define MT6338_AFE_VOW_VAD_CFG31 (0x2bc7)
|
|
#define MT6338_AFE_VOW_VAD_CFG32 (0x2bc8)
|
|
#define MT6338_AFE_VOW_VAD_CFG33 (0x2bc9)
|
|
#define MT6338_AFE_VOW_VAD_CFG34 (0x2bca)
|
|
#define MT6338_AFE_VOW_VAD_CFG35 (0x2bcb)
|
|
#define MT6338_AFE_VOW_VAD_CFG36 (0x2bcc)
|
|
#define MT6338_AFE_VOW_VAD_CFG37 (0x2bcd)
|
|
#define MT6338_AFE_VOW_VAD_CFG38 (0x2bce)
|
|
#define MT6338_AFE_VOW_VAD_CFG39 (0x2bcf)
|
|
#define MT6338_AFE_VOW_VAD_CFG40 (0x2bd0)
|
|
#define MT6338_AFE_VOW_VAD_CFG41 (0x2bd1)
|
|
#define MT6338_AFE_VOW_VAD_CFG42 (0x2bd2)
|
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#define MT6338_AFE_VOW_VAD_CFG43 (0x2bd3)
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#define MT6338_AFE_VOW_VAD_CFG44 (0x2bd4)
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#define MT6338_AFE_VOW_VAD_CFG45 (0x2bd5)
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#define MT6338_AFE_VOW_VAD_CFG46 (0x2bd6)
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#define MT6338_AFE_VOW_VAD_CFG47 (0x2bd7)
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#define MT6338_AFE_VOW_VAD_CFG48 (0x2bd8)
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#define MT6338_AFE_VOW_VAD_CFG49 (0x2bd9)
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#define MT6338_AFE_VOW_VAD_CFG50 (0x2bda)
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#define MT6338_AFE_VOW_VAD_CFG51 (0x2bdb)
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#define MT6338_AFE_VOW_VAD_CFG52 (0x2bdc)
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#define MT6338_AFE_VOW_VAD_CFG53 (0x2bdd)
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#define MT6338_AFE_VOW_VAD_CFG54 (0x2bde)
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#define MT6338_AFE_VOW_VAD_CFG55 (0x2bdf)
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#define MT6338_AFE_VOW_VAD_CFG56 (0x2be0)
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#define MT6338_AFE_VOW_VAD_CFG57 (0x2be1)
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#define MT6338_AFE_VOW_VAD_CFG58 (0x2be2)
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#define MT6338_AFE_VOW_VAD_CFG59 (0x2be3)
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#define MT6338_AFE_VOW_VAD_CFG60 (0x2be4)
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#define MT6338_AFE_VOW_VAD_CFG61 (0x2be5)
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#define MT6338_AFE_VOW_VAD_CFG62 (0x2be6)
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#define MT6338_AFE_VOW_VAD_CFG63 (0x2be7)
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#define MT6338_AFE_VOW_VAD_CFG64 (0x2be8)
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#define MT6338_AFE_VOW_VAD_CFG65 (0x2be9)
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#define MT6338_AFE_VOW_TGEN_CFG0 (0x2bea)
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#define MT6338_AFE_VOW_TGEN_CFG1 (0x2beb)
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#define MT6338_AFE_VOW_TGEN_CFG2 (0x2bec)
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#define MT6338_AFE_VOW_TGEN_CFG3 (0x2bed)
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#define MT6338_AFE_VOW_TGEN_CFG4 (0x2bee)
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#define MT6338_AFE_VOW_TGEN_CFG5 (0x2bef)
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#define MT6338_AFE_VOW_TGEN_CFG6 (0x2bf0)
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#define MT6338_AFE_VOW_TGEN_CFG7 (0x2bf1)
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#define MT6338_AFE_VOW_HPF_CFG0 (0x2bf2)
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#define MT6338_AFE_VOW_HPF_CFG1 (0x2bf3)
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#define MT6338_AFE_VOW_HPF_CFG2 (0x2bf4)
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#define MT6338_AFE_VOW_HPF_CFG3 (0x2bf5)
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#define MT6338_AFE_VOW_HPF_CFG4 (0x2bf6)
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#define MT6338_AFE_VOW_HPF_CFG5 (0x2bf7)
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#define MT6338_AFE_VOW_HPF_CFG6 (0x2bf8)
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#define MT6338_AFE_VOW_HPF_CFG7 (0x2bf9)
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#define MT6338_AFE_VOW_INTR_CON (0x2bfa)
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#define MT6338_AUDIO_DIG_18TH_DSN_ID (0x2c00)
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#define MT6338_AUDIO_DIG_18TH_DSN_ID_H (0x2c01)
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#define MT6338_AUDIO_DIG_18TH_DSN_REV0 (0x2c02)
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#define MT6338_AUDIO_DIG_18TH_DSN_REV0_H (0x2c03)
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#define MT6338_AUDIO_DIG_18TH_DSN_DBI (0x2c04)
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#define MT6338_AUDIO_DIG_18TH_DSN_DBI_H (0x2c05)
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#define MT6338_AUDIO_DIG_18TH_DSN_DXI (0x2c06)
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#define MT6338_AUDIO_VOW_SRAM_L (0x2c07)
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#define MT6338_AUDIO_VOW_SRAM_H (0x2c08)
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#define MT6338_AUDIO_DIG_19TH_DSN_ID (0x2c80)
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#define MT6338_AUDIO_DIG_19TH_DSN_ID_H (0x2c81)
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#define MT6338_AUDIO_DIG_19TH_DSN_REV0 (0x2c82)
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#define MT6338_AUDIO_DIG_19TH_DSN_REV0_H (0x2c83)
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#define MT6338_AUDIO_DIG_19TH_DSN_DBI (0x2c84)
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#define MT6338_AUDIO_DIG_19TH_DSN_DBI_H (0x2c85)
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#define MT6338_AUDIO_DIG_19TH_DSN_DXI (0x2c86)
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#define MT6338_AFE_ADDA_MTKAIFV4_TX_CFG0 (0x2c87)
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#define MT6338_AFE_ADDA6_MTKAIFV4_TX_CFG0 (0x2c88)
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#define MT6338_AFE_MTKAIFV4_TX_CFG (0x2c89)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG0 (0x2c8a)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_0 (0x2c8b)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_1 (0x2c8c)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_2 (0x2c8d)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_3 (0x2c8e)
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#define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG0 (0x2c8f)
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#define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_0 (0x2c90)
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#define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_1 (0x2c91)
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#define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_2 (0x2c92)
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#define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_3 (0x2c93)
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#define MT6338_AFE_MTKAIFV4_RX_CFG (0x2c94)
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#define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_0 (0x2c95)
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#define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_1 (0x2c96)
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#define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_2 (0x2c97)
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#define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_3 (0x2c98)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_0 (0x2c99)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_1 (0x2c9a)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_2 (0x2c9b)
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#define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_3 (0x2c9c)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON0 (0x2c9d)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON0_H (0x2c9e)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON1_0 (0x2c9f)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON1_1 (0x2ca0)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON1_2 (0x2ca1)
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#define MT6338_AFE_ADDA_MTKAIFV4_MON1_3 (0x2ca2)
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#define MT6338_AFE_ADDA6_MTKAIFV4_MON0 (0x2ca3)
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#define MT6338_AFE_ADDA6_MTKAIFV4_MON0_H (0x2ca4)
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#define MT6338_AUDIO_DIG_20TH_DSN_ID (0x2d00)
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#define MT6338_AUDIO_DIG_20TH_DSN_ID_H (0x2d01)
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#define MT6338_AUDIO_DIG_20TH_DSN_REV0 (0x2d02)
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#define MT6338_AUDIO_DIG_20TH_DSN_REV0_H (0x2d03)
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#define MT6338_AUDIO_DIG_20TH_DSN_DBI (0x2d04)
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#define MT6338_AUDIO_DIG_20TH_DSN_DBI_H (0x2d05)
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#define MT6338_AUDIO_DIG_20TH_DSN_DXI (0x2d06)
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#define MT6338_ETDM_IN0_CON0_0 (0x2d07)
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#define MT6338_ETDM_IN0_CON0_1 (0x2d08)
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#define MT6338_ETDM_IN0_CON0_2 (0x2d09)
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#define MT6338_ETDM_IN0_CON0_3 (0x2d0a)
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#define MT6338_ETDM_IN0_CON1_0 (0x2d0b)
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#define MT6338_ETDM_IN0_CON1_1 (0x2d0c)
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#define MT6338_ETDM_IN0_CON1_2 (0x2d0d)
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#define MT6338_ETDM_IN0_CON1_3 (0x2d0e)
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#define MT6338_ETDM_IN0_CON2_0 (0x2d0f)
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#define MT6338_ETDM_IN0_CON2_1 (0x2d10)
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#define MT6338_ETDM_IN0_CON2_2 (0x2d11)
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#define MT6338_ETDM_IN0_CON2_3 (0x2d12)
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#define MT6338_ETDM_IN0_CON3_0 (0x2d13)
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#define MT6338_ETDM_IN0_CON3_1 (0x2d14)
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#define MT6338_ETDM_IN0_CON3_2 (0x2d15)
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#define MT6338_ETDM_IN0_CON3_3 (0x2d16)
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#define MT6338_ETDM_IN0_CON4_0 (0x2d17)
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#define MT6338_ETDM_IN0_CON4_1 (0x2d18)
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#define MT6338_ETDM_IN0_CON4_2 (0x2d19)
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#define MT6338_ETDM_IN0_CON4_3 (0x2d1a)
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#define MT6338_ETDM_IN0_CON5_0 (0x2d1b)
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#define MT6338_ETDM_IN0_CON5_1 (0x2d1c)
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#define MT6338_ETDM_IN0_CON5_2 (0x2d1d)
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#define MT6338_ETDM_IN0_CON5_3 (0x2d1e)
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#define MT6338_ETDM_IN0_CON6_0 (0x2d1f)
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#define MT6338_ETDM_IN0_CON6_1 (0x2d20)
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#define MT6338_ETDM_IN0_CON6_2 (0x2d21)
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#define MT6338_ETDM_IN0_CON6_3 (0x2d22)
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#define MT6338_ETDM_IN0_CON7_0 (0x2d23)
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#define MT6338_ETDM_IN0_CON7_1 (0x2d24)
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#define MT6338_ETDM_IN0_CON7_2 (0x2d25)
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#define MT6338_ETDM_IN0_CON7_3 (0x2d26)
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#define MT6338_ETDM_IN0_CON8_0 (0x2d27)
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#define MT6338_ETDM_IN0_CON8_1 (0x2d28)
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#define MT6338_ETDM_IN0_CON8_2 (0x2d29)
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#define MT6338_ETDM_IN0_CON8_3 (0x2d2a)
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#define MT6338_ETDM_OUT0_CON0_0 (0x2d2b)
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#define MT6338_ETDM_OUT0_CON0_1 (0x2d2c)
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#define MT6338_ETDM_OUT0_CON0_2 (0x2d2d)
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#define MT6338_ETDM_OUT0_CON0_3 (0x2d2e)
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#define MT6338_ETDM_OUT0_CON1_0 (0x2d2f)
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#define MT6338_ETDM_OUT0_CON1_1 (0x2d30)
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#define MT6338_ETDM_OUT0_CON1_2 (0x2d31)
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#define MT6338_ETDM_OUT0_CON1_3 (0x2d32)
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#define MT6338_ETDM_OUT0_CON2_0 (0x2d33)
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#define MT6338_ETDM_OUT0_CON2_1 (0x2d34)
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#define MT6338_ETDM_OUT0_CON2_2 (0x2d35)
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#define MT6338_ETDM_OUT0_CON2_3 (0x2d36)
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#define MT6338_ETDM_OUT0_CON3_0 (0x2d37)
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#define MT6338_ETDM_OUT0_CON3_1 (0x2d38)
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#define MT6338_ETDM_OUT0_CON3_2 (0x2d39)
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#define MT6338_ETDM_OUT0_CON3_3 (0x2d3a)
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#define MT6338_ETDM_OUT0_CON4_0 (0x2d3b)
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#define MT6338_ETDM_OUT0_CON4_1 (0x2d3c)
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#define MT6338_ETDM_OUT0_CON4_2 (0x2d3d)
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#define MT6338_ETDM_OUT0_CON4_3 (0x2d3e)
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#define MT6338_ETDM_OUT0_CON5_0 (0x2d3f)
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#define MT6338_ETDM_OUT0_CON5_1 (0x2d40)
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#define MT6338_ETDM_OUT0_CON5_2 (0x2d41)
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#define MT6338_ETDM_OUT0_CON5_3 (0x2d42)
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#define MT6338_ETDM_OUT0_CON6_0 (0x2d43)
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#define MT6338_ETDM_OUT0_CON6_1 (0x2d44)
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#define MT6338_ETDM_OUT0_CON6_2 (0x2d45)
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#define MT6338_ETDM_OUT0_CON6_3 (0x2d46)
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#define MT6338_ETDM_OUT0_CON7_0 (0x2d47)
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#define MT6338_ETDM_OUT0_CON7_1 (0x2d48)
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#define MT6338_ETDM_OUT0_CON7_2 (0x2d49)
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#define MT6338_ETDM_OUT0_CON7_3 (0x2d4a)
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#define MT6338_ETDM_OUT0_CON8_0 (0x2d4b)
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#define MT6338_ETDM_OUT0_CON8_1 (0x2d4c)
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#define MT6338_ETDM_OUT0_CON8_2 (0x2d4d)
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#define MT6338_ETDM_OUT0_CON8_3 (0x2d4e)
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#define MT6338_ETDM_OUT0_CON9_0 (0x2d4f)
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#define MT6338_ETDM_OUT0_CON9_1 (0x2d50)
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#define MT6338_ETDM_OUT0_CON9_2 (0x2d51)
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#define MT6338_ETDM_OUT0_CON9_3 (0x2d52)
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#define MT6338_ETDM_0_3_COWORK_CON0_0 (0x2d53)
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#define MT6338_ETDM_0_3_COWORK_CON0_1 (0x2d54)
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#define MT6338_ETDM_0_3_COWORK_CON0_2 (0x2d55)
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#define MT6338_ETDM_0_3_COWORK_CON0_3 (0x2d56)
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#define MT6338_ETDM_0_3_COWORK_CON1_0 (0x2d57)
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#define MT6338_ETDM_0_3_COWORK_CON1_1 (0x2d58)
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#define MT6338_ETDM_0_3_COWORK_CON1_2 (0x2d59)
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#define MT6338_ETDM_0_3_COWORK_CON1_3 (0x2d5a)
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#define MT6338_ETDM_IN0_MON_0 (0x2d5b)
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#define MT6338_ETDM_IN1_MON_1 (0x2d5c)
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#define MT6338_ETDM_IN2_MON_2 (0x2d5d)
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#define MT6338_ETDM_IN3_MON_3 (0x2d5e)
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#define MT6338_ETDM_OUT0_MON_0 (0x2d5f)
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#define MT6338_ETDM_OUT1_MON_1 (0x2d60)
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#define MT6338_ETDM_OUT2_MON_2 (0x2d61)
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#define MT6338_ETDM_OUT3_MON_3 (0x2d62)
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#define MT6338_AUDIO_DIG_21TH_DSN_ID (0x2d80)
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#define MT6338_AUDIO_DIG_21TH_DSN_ID_H (0x2d81)
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#define MT6338_AUDIO_DIG_21TH_DSN_REV0 (0x2d82)
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#define MT6338_AUDIO_DIG_21TH_DSN_REV0_H (0x2d83)
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#define MT6338_AUDIO_DIG_21TH_DSN_DBI (0x2d84)
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#define MT6338_AUDIO_DIG_21TH_DSN_DBI_H (0x2d85)
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#define MT6338_AUDIO_DIG_21TH_DSN_DXI (0x2d86)
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#define MT6338_AFE_GAIN1_CON0_1 (0x2d87)
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#define MT6338_AFE_GAIN1_CON0_0 (0x2d88)
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#define MT6338_AFE_GAIN1_CON1_3 (0x2d89)
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#define MT6338_AFE_GAIN1_CON1_2 (0x2d8a)
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#define MT6338_AFE_GAIN1_CON1_1 (0x2d8b)
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#define MT6338_AFE_GAIN1_CON1_0 (0x2d8c)
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#define MT6338_AFE_GAIN1_CON2_2 (0x2d8d)
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#define MT6338_AFE_GAIN1_CON2_1 (0x2d8e)
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#define MT6338_AFE_GAIN1_CON2_0 (0x2d8f)
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#define MT6338_AFE_GAIN1_CON3_2 (0x2d90)
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#define MT6338_AFE_GAIN1_CON3_1 (0x2d91)
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#define MT6338_AFE_GAIN1_CON3_0 (0x2d92)
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#define MT6338_AFE_GAIN1_CUR_3 (0x2d93)
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#define MT6338_AFE_GAIN1_CUR_2 (0x2d94)
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#define MT6338_AFE_GAIN1_CUR_1 (0x2d95)
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#define MT6338_AFE_GAIN1_CUR_0 (0x2d96)
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#define MT6338_AFE_GAIN1_CUR_PRE_3 (0x2d97)
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|
#define MT6338_AFE_GAIN1_CUR_PRE_2 (0x2d98)
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|
#define MT6338_AFE_GAIN1_CUR_PRE_1 (0x2d99)
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|
#define MT6338_AFE_GAIN1_CUR_PRE_0 (0x2d9a)
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|
#define MT6338_AFE_GAIN2_CON0_1 (0x2d9b)
|
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#define MT6338_AFE_GAIN2_CON0_0 (0x2d9c)
|
|
#define MT6338_AFE_GAIN2_CON1_3 (0x2d9d)
|
|
#define MT6338_AFE_GAIN2_CON1_2 (0x2d9e)
|
|
#define MT6338_AFE_GAIN2_CON1_1 (0x2d9f)
|
|
#define MT6338_AFE_GAIN2_CON1_0 (0x2da0)
|
|
#define MT6338_AFE_GAIN2_CON2_2 (0x2da1)
|
|
#define MT6338_AFE_GAIN2_CON2_1 (0x2da2)
|
|
#define MT6338_AFE_GAIN2_CON2_0 (0x2da3)
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|
#define MT6338_AFE_GAIN2_CON3_2 (0x2da4)
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|
#define MT6338_AFE_GAIN2_CON3_1 (0x2da5)
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|
#define MT6338_AFE_GAIN2_CON3_0 (0x2da6)
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|
#define MT6338_AFE_GAIN2_CUR_3 (0x2da7)
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|
#define MT6338_AFE_GAIN2_CUR_2 (0x2da8)
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|
#define MT6338_AFE_GAIN2_CUR_1 (0x2da9)
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|
#define MT6338_AFE_GAIN2_CUR_0 (0x2daa)
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|
#define MT6338_AFE_GAIN2_CUR_PRE_3 (0x2dab)
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|
#define MT6338_AFE_GAIN2_CUR_PRE_2 (0x2dac)
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|
#define MT6338_AFE_GAIN2_CUR_PRE_1 (0x2dad)
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|
#define MT6338_AFE_GAIN2_CUR_PRE_0 (0x2dae)
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|
#define MT6338_AUDIO_DIG_22TH_DSN_ID (0x2e00)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_ID_H (0x2e01)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_REV0 (0x2e02)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_REV0_H (0x2e03)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_DBI (0x2e04)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_DBI_H (0x2e05)
|
|
#define MT6338_AUDIO_DIG_22TH_DSN_DXI (0x2e06)
|
|
#define MT6338_AFE_VOW_VAD_MON0 (0x2e07)
|
|
#define MT6338_AFE_VOW_VAD_MON1 (0x2e08)
|
|
#define MT6338_AFE_VOW_VAD_MON2 (0x2e09)
|
|
#define MT6338_AFE_VOW_VAD_MON3 (0x2e0a)
|
|
#define MT6338_AFE_VOW_VAD_MON4 (0x2e0b)
|
|
#define MT6338_AFE_VOW_VAD_MON5 (0x2e0c)
|
|
#define MT6338_AFE_VOW_VAD_MON6 (0x2e0d)
|
|
#define MT6338_AFE_VOW_VAD_MON7 (0x2e0e)
|
|
#define MT6338_AFE_VOW_VAD_MON8 (0x2e0f)
|
|
#define MT6338_AFE_VOW_VAD_MON9 (0x2e10)
|
|
#define MT6338_AFE_VOW_VAD_MON10 (0x2e11)
|
|
#define MT6338_AFE_VOW_VAD_MON11 (0x2e12)
|
|
#define MT6338_AFE_VOW_VAD_MON12 (0x2e13)
|
|
#define MT6338_AFE_VOW_VAD_MON13 (0x2e14)
|
|
#define MT6338_AFE_VOW_VAD_MON14 (0x2e15)
|
|
#define MT6338_AFE_VOW_VAD_MON15 (0x2e16)
|
|
#define MT6338_AFE_VOW_VAD_MON16 (0x2e17)
|
|
#define MT6338_AFE_VOW_VAD_MON17 (0x2e18)
|
|
#define MT6338_AFE_VOW_VAD_MON18 (0x2e19)
|
|
#define MT6338_AFE_VOW_VAD_MON19 (0x2e1a)
|
|
#define MT6338_AFE_VOW_VAD_MON20 (0x2e1b)
|
|
#define MT6338_AFE_VOW_VAD_MON21 (0x2e1c)
|
|
#define MT6338_AFE_VOW_VAD_MON22 (0x2e1d)
|
|
#define MT6338_AFE_VOW_VAD_MON23 (0x2e1e)
|
|
#define MT6338_AFE_VOW_VAD_MON24 (0x2e1f)
|
|
#define MT6338_AFE_VOW_VAD_MON25 (0x2e20)
|
|
#define MT6338_AFE_VOW_VAD_MON26 (0x2e21)
|
|
#define MT6338_AFE_VOW_VAD_MON27 (0x2e22)
|
|
#define MT6338_AFE_VOW_VAD_MON28 (0x2e23)
|
|
#define MT6338_AFE_VOW_VAD_MON29 (0x2e24)
|
|
#define MT6338_AFE_VOW_VAD_MON30 (0x2e25)
|
|
#define MT6338_AFE_VOW_VAD_MON31 (0x2e26)
|
|
#define MT6338_AFE_VOW_VAD_MON32 (0x2e27)
|
|
#define MT6338_AFE_VOW_VAD_MON33 (0x2e28)
|
|
#define MT6338_AFE_VOW_VAD_MON34 (0x2e29)
|
|
#define MT6338_AFE_VOW_VAD_MON35 (0x2e2a)
|
|
#define MT6338_AFE_VOW_VAD_MON36 (0x2e2b)
|
|
#define MT6338_AFE_VOW_VAD_MON37 (0x2e2c)
|
|
#define MT6338_AFE_VOW_VAD_MON38 (0x2e2d)
|
|
#define MT6338_AFE_VOW_VAD_MON39 (0x2e2e)
|
|
#define MT6338_AFE_VOW_VAD_MON40 (0x2e2f)
|
|
#define MT6338_AFE_VOW_VAD_MON41 (0x2e30)
|
|
#define MT6338_AFE_VOW_VAD_MON42 (0x2e31)
|
|
#define MT6338_AFE_VOW_VAD_MON43 (0x2e32)
|
|
#define MT6338_AFE_VOW_VAD_MON44 (0x2e33)
|
|
#define MT6338_AFE_VOW_VAD_MON45 (0x2e34)
|
|
#define MT6338_AFE_VOW_VAD_MON46 (0x2e35)
|
|
#define MT6338_AFE_VOW_VAD_MON47 (0x2e36)
|
|
#define MT6338_AUDENC_ANA_ID (0x2e80)
|
|
#define MT6338_AUDENC_DIG_ID (0x2e81)
|
|
#define MT6338_AUDENC_ANA_REV (0x2e82)
|
|
#define MT6338_AUDENC_DIG_REV (0x2e83)
|
|
#define MT6338_AUDENC_DBI (0x2e84)
|
|
#define MT6338_AUDENC_ESP (0x2e85)
|
|
#define MT6338_AUDENC_FPI (0x2e86)
|
|
#define MT6338_AUDENC_DXI (0x2e87)
|
|
#define MT6338_AUDENC_PMU_CON0 (0x2e88)
|
|
#define MT6338_AUDENC_PMU_CON1 (0x2e89)
|
|
#define MT6338_AUDENC_PMU_CON2 (0x2e8a)
|
|
#define MT6338_AUDENC_PMU_CON3 (0x2e8b)
|
|
#define MT6338_AUDENC_PMU_CON4 (0x2e8c)
|
|
#define MT6338_AUDENC_PMU_CON5 (0x2e8d)
|
|
#define MT6338_AUDENC_PMU_CON6 (0x2e8e)
|
|
#define MT6338_AUDENC_PMU_CON7 (0x2e8f)
|
|
#define MT6338_AUDENC_PMU_CON8 (0x2e90)
|
|
#define MT6338_AUDENC_PMU_CON9 (0x2e91)
|
|
#define MT6338_AUDENC_PMU_CON10 (0x2e92)
|
|
#define MT6338_AUDENC_PMU_CON11 (0x2e93)
|
|
#define MT6338_AUDENC_PMU_CON12 (0x2e94)
|
|
#define MT6338_AUDENC_PMU_CON13 (0x2e95)
|
|
#define MT6338_AUDENC_PMU_CON14 (0x2e96)
|
|
#define MT6338_AUDENC_PMU_CON15 (0x2e97)
|
|
#define MT6338_AUDENC_PMU_CON16 (0x2e98)
|
|
#define MT6338_AUDENC_PMU_CON17 (0x2e99)
|
|
#define MT6338_AUDENC_PMU_CON18 (0x2e9a)
|
|
#define MT6338_AUDENC_PMU_CON19 (0x2e9b)
|
|
#define MT6338_AUDENC_PMU_CON20 (0x2e9c)
|
|
#define MT6338_AUDENC_PMU_CON21 (0x2e9d)
|
|
#define MT6338_AUDENC_PMU_CON22 (0x2e9e)
|
|
#define MT6338_AUDENC_PMU_CON23 (0x2e9f)
|
|
#define MT6338_AUDENC_PMU_CON24 (0x2ea0)
|
|
#define MT6338_AUDENC_PMU_CON25 (0x2ea1)
|
|
#define MT6338_AUDENC_PMU_CON26 (0x2ea2)
|
|
#define MT6338_AUDENC_PMU_CON27 (0x2ea3)
|
|
#define MT6338_AUDENC_PMU_CON28 (0x2ea4)
|
|
#define MT6338_AUDENC_PMU_CON29 (0x2ea5)
|
|
#define MT6338_AUDENC_PMU_CON30 (0x2ea6)
|
|
#define MT6338_AUDENC_PMU_CON31 (0x2ea7)
|
|
#define MT6338_AUDENC_PMU_CON32 (0x2ea8)
|
|
#define MT6338_AUDENC_PMU_CON33 (0x2ea9)
|
|
#define MT6338_AUDENC_PMU_CON34 (0x2eaa)
|
|
#define MT6338_AUDENC_PMU_CON35 (0x2eab)
|
|
#define MT6338_AUDENC_PMU_CON36 (0x2eac)
|
|
#define MT6338_AUDENC_PMU_CON37 (0x2ead)
|
|
#define MT6338_AUDENC_PMU_CON38 (0x2eae)
|
|
#define MT6338_AUDENC_PMU_CON39 (0x2eaf)
|
|
#define MT6338_AUDENC_PMU_CON40 (0x2eb0)
|
|
#define MT6338_AUDENC_PMU_CON41 (0x2eb1)
|
|
#define MT6338_AUDENC_PMU_CON42 (0x2eb2)
|
|
#define MT6338_AUDENC_PMU_CON43 (0x2eb3)
|
|
#define MT6338_AUDENC_PMU_CON44 (0x2eb4)
|
|
#define MT6338_AUDENC_PMU_CON45 (0x2eb5)
|
|
#define MT6338_AUDENC_PMU_CON46 (0x2eb6)
|
|
#define MT6338_AUDENC_PMU_CON47 (0x2eb7)
|
|
#define MT6338_AUDENC_PMU_CON48 (0x2eb8)
|
|
#define MT6338_AUDENC_PMU_CON49 (0x2eb9)
|
|
#define MT6338_AUDENC_PMU_CON50 (0x2eba)
|
|
#define MT6338_AUDENC_PMU_CON51 (0x2ebb)
|
|
#define MT6338_AUDENC_PMU_CON52 (0x2ebc)
|
|
#define MT6338_AUDENC_PMU_CON53 (0x2ebd)
|
|
#define MT6338_AUDENC_PMU_CON54 (0x2ebe)
|
|
#define MT6338_AUDENC_PMU_CON55 (0x2ebf)
|
|
#define MT6338_AUDENC_PMU_CON56 (0x2ec0)
|
|
#define MT6338_AUDENC_PMU_CON57 (0x2ec1)
|
|
#define MT6338_AUDENC_PMU_CON58 (0x2ec2)
|
|
#define MT6338_AUDENC_PMU_CON59 (0x2ec3)
|
|
#define MT6338_AUDENC_PMU_CON60 (0x2ec4)
|
|
#define MT6338_AUDENC_PMU_CON61 (0x2ec5)
|
|
#define MT6338_AUDENC_PMU_CON62 (0x2ec6)
|
|
#define MT6338_AUDENC_PMU_CON63 (0x2ec7)
|
|
#define MT6338_AUDENC_PMU_CON64 (0x2ec8)
|
|
#define MT6338_AUDENC_PMU_CON65 (0x2ec9)
|
|
#define MT6338_AUDENC_PMU_CON66 (0x2eca)
|
|
#define MT6338_AUDENC_PMU_CON67 (0x2ecb)
|
|
#define MT6338_AUDENC_PMU_CON68 (0x2ecc)
|
|
#define MT6338_AUDENC_PMU_CON69 (0x2ecd)
|
|
#define MT6338_AUDENC_PMU_CON70 (0x2ece)
|
|
#define MT6338_AUDENC_PMU_CON71 (0x2ecf)
|
|
#define MT6338_AUDENC_PMU_CON72 (0x2ed0)
|
|
#define MT6338_AUDENC_PMU_CON73 (0x2ed1)
|
|
#define MT6338_AUDENC_PMU_CON74 (0x2ed2)
|
|
#define MT6338_AUDENC_PMU_CON75 (0x2ed3)
|
|
#define MT6338_AUDENC_PMU_CON76 (0x2ed4)
|
|
#define MT6338_AUDENC_PMU_CON77 (0x2ed5)
|
|
#define MT6338_AUDENC_PMU_CON78 (0x2ed6)
|
|
#define MT6338_AUDENC_PMU_CON79 (0x2ed7)
|
|
#define MT6338_AUDENC_PMU_CON80 (0x2ed8)
|
|
#define MT6338_AUDENC_PMU_CON81 (0x2ed9)
|
|
#define MT6338_AUDENC_2_PMU_CON1 (0x2edb)
|
|
#define MT6338_AUDENC_2_PMU_CON2 (0x2edc)
|
|
#define MT6338_AUDENC_2_PMU_CON3 (0x2edd)
|
|
#define MT6338_AUDENC_2_PMU_CON4 (0x2ede)
|
|
#define MT6338_AUDENC_2_PMU_CON5 (0x2edf)
|
|
#define MT6338_AUDENC_2_PMU_CON6 (0x2ee0)
|
|
#define MT6338_AUDENC_2_PMU_CON7 (0x2ee1)
|
|
#define MT6338_AUDENC_2_PMU_CON8 (0x2ee2)
|
|
#define MT6338_AUDENC_2_PMU_CON9 (0x2ee3)
|
|
#define MT6338_AUDENC_2_PMU_CON10 (0x2ee4)
|
|
#define MT6338_AUDENC_2_PMU_CON11 (0x2ee5)
|
|
#define MT6338_AUDENC_2_PMU_CON12 (0x2ee6)
|
|
#define MT6338_AUDENC_2_PMU_CON13 (0x2ee7)
|
|
#define MT6338_AUDENC_ELR_NUM (0x2ee8)
|
|
#define MT6338_AUDENC_ELR_0 (0x2ee9)
|
|
#define MT6338_AUDENC_ELR_1 (0x2eea)
|
|
#define MT6338_AUDENC_ELR_2 (0x2eeb)
|
|
#define MT6338_AUDENC_ELR_3 (0x2eec)
|
|
#define MT6338_AUDENC_ELR_4 (0x2eed)
|
|
#define MT6338_AUDDEC_ANA_ID (0x2f00)
|
|
#define MT6338_AUDDEC_DIG_ID (0x2f01)
|
|
#define MT6338_AUDDEC_ANA_REV (0x2f02)
|
|
#define MT6338_AUDDEC_DIG_REV (0x2f03)
|
|
#define MT6338_AUDDEC_DBI (0x2f04)
|
|
#define MT6338_AUDDEC_ESP (0x2f05)
|
|
#define MT6338_AUDDEC_FPI (0x2f06)
|
|
#define MT6338_AUDDEC_DXI (0x2f07)
|
|
#define MT6338_AUDDEC_PMU_CON0 (0x2f08)
|
|
#define MT6338_AUDDEC_PMU_CON1 (0x2f09)
|
|
#define MT6338_AUDDEC_PMU_CON2 (0x2f0a)
|
|
#define MT6338_AUDDEC_PMU_CON3 (0x2f0b)
|
|
#define MT6338_AUDDEC_PMU_CON4 (0x2f0c)
|
|
#define MT6338_AUDDEC_PMU_CON5 (0x2f0d)
|
|
#define MT6338_AUDDEC_PMU_CON6 (0x2f0e)
|
|
#define MT6338_AUDDEC_PMU_CON7 (0x2f0f)
|
|
#define MT6338_AUDDEC_PMU_CON8 (0x2f10)
|
|
#define MT6338_AUDDEC_PMU_CON9 (0x2f11)
|
|
#define MT6338_AUDDEC_PMU_CON10 (0x2f12)
|
|
#define MT6338_AUDDEC_PMU_CON11 (0x2f13)
|
|
#define MT6338_AUDDEC_PMU_CON12 (0x2f14)
|
|
#define MT6338_AUDDEC_PMU_CON13 (0x2f15)
|
|
#define MT6338_AUDDEC_PMU_CON14 (0x2f16)
|
|
#define MT6338_AUDDEC_PMU_CON15 (0x2f17)
|
|
#define MT6338_AUDDEC_PMU_CON16 (0x2f18)
|
|
#define MT6338_AUDDEC_PMU_CON17 (0x2f19)
|
|
#define MT6338_AUDDEC_PMU_CON18 (0x2f1a)
|
|
#define MT6338_AUDDEC_PMU_CON19 (0x2f1b)
|
|
#define MT6338_AUDDEC_PMU_CON20 (0x2f1c)
|
|
#define MT6338_AUDDEC_PMU_CON21 (0x2f1d)
|
|
#define MT6338_AUDDEC_PMU_CON22 (0x2f1e)
|
|
#define MT6338_AUDDEC_PMU_CON23 (0x2f1f)
|
|
#define MT6338_AUDDEC_PMU_CON24 (0x2f20)
|
|
#define MT6338_AUDDEC_PMU_CON25 (0x2f21)
|
|
#define MT6338_AUDDEC_PMU_CON26 (0x2f22)
|
|
#define MT6338_AUDDEC_PMU_CON27 (0x2f23)
|
|
#define MT6338_AUDDEC_PMU_CON28 (0x2f24)
|
|
#define MT6338_AUDDEC_PMU_CON29 (0x2f25)
|
|
#define MT6338_AUDDEC_PMU_CON30 (0x2f26)
|
|
#define MT6338_AUDDEC_PMU_CON31 (0x2f27)
|
|
#define MT6338_AUDDEC_PMU_CON32 (0x2f28)
|
|
#define MT6338_AUDDEC_PMU_CON33 (0x2f29)
|
|
#define MT6338_AUDDEC_PMU_CON34 (0x2f2a)
|
|
#define MT6338_AUDDEC_PMU_CON35 (0x2f2b)
|
|
#define MT6338_AUDDEC_PMU_CON36 (0x2f2c)
|
|
#define MT6338_AUDDEC_PMU_CON37 (0x2f2d)
|
|
#define MT6338_AUDDEC_PMU_CON38 (0x2f2e)
|
|
#define MT6338_AUDDEC_PMU_CON39 (0x2f2f)
|
|
#define MT6338_AUDDEC_PMU_CON40 (0x2f30)
|
|
#define MT6338_AUDDEC_PMU_CON41 (0x2f31)
|
|
#define MT6338_AUDDEC_PMU_CON42 (0x2f32)
|
|
#define MT6338_AUDDEC_PMU_CON43 (0x2f33)
|
|
#define MT6338_AUDDEC_PMU_CON44 (0x2f34)
|
|
#define MT6338_AUDDEC_PMU_CON45 (0x2f35)
|
|
#define MT6338_AUDDEC_PMU_CON46 (0x2f36)
|
|
#define MT6338_AUDDEC_PMU_CON47 (0x2f37)
|
|
#define MT6338_AUDDEC_PMU_CON48 (0x2f38)
|
|
#define MT6338_AUDDEC_PMU_CON49 (0x2f39)
|
|
#define MT6338_AUDDEC_2_PMU_CON0 (0x2f3a)
|
|
#define MT6338_AUDDEC_2_PMU_CON1 (0x2f3b)
|
|
#define MT6338_AUDDEC_2_PMU_CON2 (0x2f3c)
|
|
#define MT6338_AUDDEC_2_PMU_CON3 (0x2f3d)
|
|
#define MT6338_AUDDEC_2_PMU_CON4 (0x2f3e)
|
|
#define MT6338_AUDDEC_2_PMU_CON5 (0x2f3f)
|
|
#define MT6338_AUDDEC_2_PMU_CON6 (0x2f40)
|
|
#define MT6338_AUDDEC_2_PMU_CON7 (0x2f41)
|
|
#define MT6338_AUDDEC_2_PMU_CON8 (0x2f42)
|
|
#define MT6338_AUDDEC_2_PMU_CON9 (0x2f43)
|
|
#define MT6338_AUDDEC_2_PMU_CON10 (0x2f44)
|
|
#define MT6338_AUDDEC_2_PMU_CON11 (0x2f45)
|
|
#define MT6338_AUDDEC_2_PMU_CON12 (0x2f46)
|
|
#define MT6338_AUDZCD_DSN_ID (0x2f80)
|
|
#define MT6338_AUDZCD_DSN_ID_H (0x2f81)
|
|
#define MT6338_AUDZCD_DSN_REV0 (0x2f82)
|
|
#define MT6338_AUDZCD_DSN_REV0_H (0x2f83)
|
|
#define MT6338_AUDZCD_DSN_DBI (0x2f84)
|
|
#define MT6338_AUDZCD_DSN_DBI_H (0x2f85)
|
|
#define MT6338_AUDZCD_DSN_FPI (0x2f86)
|
|
#define MT6338_ZCD_CON0 (0x2f87)
|
|
#define MT6338_ZCD_CON1 (0x2f88)
|
|
#define MT6338_ZCD_CON1_H (0x2f89)
|
|
#define MT6338_ZCD_CON2 (0x2f8a)
|
|
#define MT6338_ZCD_CON2_H (0x2f8b)
|
|
#define MT6338_ZCD_CON3 (0x2f8c)
|
|
#define MT6338_ZCD_CON4 (0x2f8d)
|
|
#define MT6338_ZCD_CON4_H (0x2f8e)
|
|
#define MT6338_ZCD_CON5 (0x2f8f)
|
|
#define MT6338_ZCD_CON5_H (0x2f90)
|
|
#define MT6338_ACCDET_DSN_DIG_ID (0x3000)
|
|
#define MT6338_ACCDET_DSN_DIG_ID_H (0x3001)
|
|
#define MT6338_ACCDET_DSN_DIG_REV0 (0x3002)
|
|
#define MT6338_ACCDET_DSN_DIG_REV0_H (0x3003)
|
|
#define MT6338_ACCDET_DSN_DBI (0x3004)
|
|
#define MT6338_ACCDET_DSN_DBI_H (0x3005)
|
|
#define MT6338_ACCDET_DSN_FPI (0x3006)
|
|
#define MT6338_ACCDET_CON0_L (0x3007)
|
|
#define MT6338_ACCDET_CON0_H (0x3008)
|
|
#define MT6338_ACCDET_CON1_L (0x3009)
|
|
#define MT6338_ACCDET_CON1_H (0x300a)
|
|
#define MT6338_ACCDET_CON2_L (0x300b)
|
|
#define MT6338_ACCDET_CON2_H (0x300c)
|
|
#define MT6338_ACCDET_CON3_L (0x300d)
|
|
#define MT6338_ACCDET_CON3_H (0x300e)
|
|
#define MT6338_ACCDET_CON4_L (0x300f)
|
|
#define MT6338_ACCDET_CON4_H (0x3010)
|
|
#define MT6338_ACCDET_CON5_L (0x3011)
|
|
#define MT6338_ACCDET_CON5_H (0x3012)
|
|
#define MT6338_ACCDET_CON6 (0x3013)
|
|
#define MT6338_ACCDET_CON7_L (0x3014)
|
|
#define MT6338_ACCDET_CON7_H (0x3015)
|
|
#define MT6338_ACCDET_CON8_L (0x3016)
|
|
#define MT6338_ACCDET_CON8_H (0x3017)
|
|
#define MT6338_ACCDET_CON9_L (0x3018)
|
|
#define MT6338_ACCDET_CON9_H (0x3019)
|
|
#define MT6338_ACCDET_CON10_L (0x301a)
|
|
#define MT6338_ACCDET_CON10_H (0x301b)
|
|
#define MT6338_ACCDET_CON11_L (0x301c)
|
|
#define MT6338_ACCDET_CON11_H (0x301d)
|
|
#define MT6338_ACCDET_CON12_L (0x301e)
|
|
#define MT6338_ACCDET_CON12_H (0x301f)
|
|
#define MT6338_ACCDET_CON13_L (0x3020)
|
|
#define MT6338_ACCDET_CON13_H (0x3021)
|
|
#define MT6338_ACCDET_CON14_L (0x3022)
|
|
#define MT6338_ACCDET_CON14_H (0x3023)
|
|
#define MT6338_ACCDET_CON15 (0x3024)
|
|
#define MT6338_ACCDET_CON16_L (0x3025)
|
|
#define MT6338_ACCDET_CON16_H (0x3026)
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#define MT6338_ACCDET_CON17 (0x3027)
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#define MT6338_ACCDET_CON18_L (0x3028)
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#define MT6338_ACCDET_CON18_H (0x3029)
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#define MT6338_ACCDET_CON19_L (0x302a)
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#define MT6338_ACCDET_CON19_H (0x302b)
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#define MT6338_ACCDET_CON20_L (0x302c)
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#define MT6338_ACCDET_CON20_H (0x302d)
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#define MT6338_ACCDET_CON21_L (0x302e)
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#define MT6338_ACCDET_CON21_H (0x302f)
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#define MT6338_ACCDET_CON22_L (0x3030)
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#define MT6338_ACCDET_CON22_H (0x3031)
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#define MT6338_ACCDET_CON23_L (0x3032)
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#define MT6338_ACCDET_CON23_H (0x3033)
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#define MT6338_ACCDET_CON24 (0x3034)
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#define MT6338_ACCDET_CON25_L (0x3035)
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#define MT6338_ACCDET_CON25_H (0x3036)
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#define MT6338_ACCDET_CON26_L (0x3037)
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#define MT6338_ACCDET_CON26_H (0x3038)
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#define MT6338_ACCDET_CON27_L (0x3039)
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#define MT6338_ACCDET_CON27_H (0x303a)
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#define MT6338_ACCDET_CON28_L (0x303b)
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#define MT6338_ACCDET_CON28_H (0x303c)
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#define MT6338_ACCDET_CON29_L (0x303d)
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#define MT6338_ACCDET_CON29_H (0x303e)
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#define MT6338_ACCDET_CON30_L (0x303f)
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#define MT6338_ACCDET_CON30_H (0x3040)
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#define MT6338_ACCDET_CON31_L (0x3041)
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#define MT6338_ACCDET_CON31_H (0x3042)
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#define MT6338_ACCDET_CON32_L (0x3043)
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#define MT6338_ACCDET_CON32_H (0x3044)
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#define MT6338_ACCDET_CON33_L (0x3045)
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#define MT6338_ACCDET_CON33_H (0x3046)
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#define MT6338_ACCDET_CON34_L (0x3047)
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#define MT6338_ACCDET_CON34_H (0x3048)
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#define MT6338_ACCDET_CON35_L (0x3049)
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#define MT6338_ACCDET_CON35_H (0x304a)
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#define MT6338_ACCDET_CON36 (0x304b)
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#define MT6338_ACCDET_CON37 (0x304c)
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#define MT6338_ACCDET_CON38_L (0x304d)
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#define MT6338_ACCDET_CON38_H (0x304e)
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#define MT6338_ACCDET_CON39 (0x304f)
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#define MT6338_ACCDET_CON40 (0x3050)
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#define MT6338_REG_COUNT 3045
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#define MT6338_MAX_REGISTER MT6338_ACCDET_CON40
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#define MT6338_SWCID_H_CODE 0x38
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#define MT6338_SWCID_L_E1_CODE 0x10
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#define MT6338_SWCID_L_E2_CODE 0x20
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#define MT6338_SWCID_L_E3_CODE 0x30
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/* TOP0_ID */
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#define TOP0_ANA_ID_SFT 0
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#define TOP0_ANA_ID_MASK 0xff
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#define TOP0_ANA_ID_MASK_SFT (0xff << 0)
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/* TOP0_ID_H */
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#define TOP0_DIG_ID_SFT 0
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#define TOP0_DIG_ID_MASK 0xff
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#define TOP0_DIG_ID_MASK_SFT (0xff << 0)
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/* TOP0_REV0 */
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#define TOP0_ANA_MINOR_REV_SFT 0
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#define TOP0_ANA_MINOR_REV_MASK 0xf
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#define TOP0_ANA_MINOR_REV_MASK_SFT (0xf << 0)
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#define TOP0_ANA_MAJOR_REV_SFT 4
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#define TOP0_ANA_MAJOR_REV_MASK 0xf
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#define TOP0_ANA_MAJOR_REV_MASK_SFT (0xf << 4)
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/* TOP0_REV0_H */
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#define TOP0_DIG_MINOR_REV_SFT 0
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#define TOP0_DIG_MINOR_REV_MASK 0xf
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#define TOP0_DIG_MINOR_REV_MASK_SFT (0xf << 0)
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#define TOP0_DIG_MAJOR_REV_SFT 4
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#define TOP0_DIG_MAJOR_REV_MASK 0xf
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#define TOP0_DIG_MAJOR_REV_MASK_SFT (0xf << 4)
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#define TOP0_DSN_FPI_MASK_SFT (0xff << 0)
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/* HWCID_L */
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#define HWCID_L_SFT 0
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#define HWCID_L_MASK 0xff
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#define HWCID_L_MASK_SFT (0xff << 0)
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/* HWCID_H */
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#define HWCID_H_SFT 0
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#define HWCID_H_MASK 0xff
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#define HWCID_H_MASK_SFT (0xff << 0)
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/* SWCID_L */
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#define SWCID_L_SFT 0
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#define SWCID_L_MASK 0xff
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#define SWCID_L_MASK_SFT (0xff << 0)
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/* SWCID_H */
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#define SWCID_H_SFT 0
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#define SWCID_H_MASK 0xff
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#define SWCID_H_MASK_SFT (0xff << 0)
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/* TOP_CON */
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#define RG_OSC_EN_AUTO_OFF_SFT 3
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#define RG_OSC_EN_AUTO_OFF_MASK 0x1
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#define RG_OSC_EN_AUTO_OFF_MASK_SFT (0x1 << 3)
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#define RG_SRCLKEN_IN_SYNC_EN_SFT 2
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#define RG_SRCLKEN_IN_SYNC_EN_MASK 0x1
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#define RG_SRCLKEN_IN_SYNC_EN_MASK_SFT (0x1 << 2)
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#define RG_SRCLKEN_IN_HW_MODE_SFT 1
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#define RG_SRCLKEN_IN_HW_MODE_MASK 0x1
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#define RG_SRCLKEN_IN_HW_MODE_MASK_SFT (0x1 << 1)
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#define RG_SRCLKEN_IN_EN_SFT 0
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#define RG_SRCLKEN_IN_EN_MASK 0x1
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#define RG_SRCLKEN_IN_EN_MASK_SFT (0x1 << 0)
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/* TEST_CON0 */
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#define RG_MON_GRP_SEL_SFT 0
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#define RG_MON_GRP_SEL_MASK 0x1f
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#define RG_MON_GRP_SEL_MASK_SFT (0x1f << 0)
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/* SMT_CON0 */
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#define RG_SMT_SRCLKEN_IN0_SFT 0
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#define RG_SMT_SRCLKEN_IN0_MASK 0x1
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#define RG_SMT_SRCLKEN_IN0_MASK_SFT (0x1 << 0)
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#define RG_RSV_SCL_SPMI_CLK_SFT 1
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#define RG_RSV_SCL_SPMI_CLK_MASK 0x1
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#define RG_RSV_SCL_SPMI_CLK_MASK_SFT (0x1 << 1)
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#define RG_RSV_SDA_SPMI_DAT_SFT 2
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#define RG_RSV_SDA_SPMI_DAT_MASK 0x1
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#define RG_RSV_SDA_SPMI_DAT_MASK_SFT (0x1 << 2)
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#define RG_SMT_INT_SFT 3
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#define RG_SMT_INT_MASK 0x1
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#define RG_SMT_INT_MASK_SFT (0x1 << 3)
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#define RG_SMT_AUD_DAT_MOSI0_SFT 4
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#define RG_SMT_AUD_DAT_MOSI0_MASK 0x1
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#define RG_SMT_AUD_DAT_MOSI0_MASK_SFT (0x1 << 4)
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#define RG_SMT_AUD_DAT_MOSI1_SFT 5
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#define RG_SMT_AUD_DAT_MOSI1_MASK 0x1
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#define RG_SMT_AUD_DAT_MOSI1_MASK_SFT (0x1 << 5)
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#define RG_SMT_AUD_DAT_MISO0_SFT 6
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#define RG_SMT_AUD_DAT_MISO0_MASK 0x1
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#define RG_SMT_AUD_DAT_MISO0_MASK_SFT (0x1 << 6)
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#define RG_SMT_AUD_CLK_MOSI_SFT 7
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#define RG_SMT_AUD_CLK_MOSI_MASK 0x1
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#define RG_SMT_AUD_CLK_MOSI_MASK_SFT (0x1 << 7)
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/* TOP_CKPDN_CON0 */
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#define RG_I2C_CK_PDN_SFT 7
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#define RG_I2C_CK_PDN_MASK 0x1
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#define RG_I2C_CK_PDN_MASK_SFT (0x1 << 7)
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#define RG_SPMI_CK_PDN_SFT 6
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#define RG_SPMI_CK_PDN_MASK 0x1
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#define RG_SPMI_CK_PDN_MASK_SFT (0x1 << 6)
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#define RG_INTRP_CK_PDN_SFT 5
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#define RG_INTRP_CK_PDN_MASK 0x1
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#define RG_INTRP_CK_PDN_MASK_SFT (0x1 << 5)
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#define RG_FQMTR_CK_PDN_SFT 4
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#define RG_FQMTR_CK_PDN_MASK 0x1
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#define RG_FQMTR_CK_PDN_MASK_SFT (0x1 << 4)
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#define RG_FQMTR_32K_CK_PDN_SFT 3
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#define RG_FQMTR_32K_CK_PDN_MASK 0x1
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#define RG_FQMTR_32K_CK_PDN_MASK_SFT (0x1 << 3)
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#define RG_EFUSE_CK_PDN_SFT 2
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#define RG_EFUSE_CK_PDN_MASK 0x1
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#define RG_EFUSE_CK_PDN_MASK_SFT (0x1 << 2)
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#define RG_TRIM_26M_CK_PDN_SFT 1
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#define RG_TRIM_26M_CK_PDN_MASK 0x1
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#define RG_TRIM_26M_CK_PDN_MASK_SFT (0x1 << 1)
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#define RG_TRIM_75K_CK_PDN_SFT 0
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#define RG_TRIM_75K_CK_PDN_MASK 0x1
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#define RG_TRIM_75K_CK_PDN_MASK_SFT (0x1 << 0)
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/* TOP_CKPDN_CON0_SET */
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#define TOP_CKPDN_CON0_SET_SFT 0
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#define TOP_CKPDN_CON0_SET_MASK 0xff
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#define TOP_CKPDN_CON0_SET_MASK_SFT (0xff << 0)
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/* TOP_CKPDN_CON0_CLR */
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#define TOP_CKPDN_CON0_CLR_SFT 0
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#define TOP_CKPDN_CON0_CLR_MASK 0xff
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#define TOP_CKPDN_CON0_CLR_MASK_SFT (0xff << 0)
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/* PMRC_CON1 */
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#define RG_VR_SPM_MODE_SFT 0
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#define RG_VR_SPM_MODE_MASK 0x1
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#define RG_VR_SPM_MODE_MASK_SFT (0x1 << 0)
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#define RG_TOP_SPM_MODE_SFT 1
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#define RG_TOP_SPM_MODE_MASK 0x1
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#define RG_TOP_SPM_MODE_MASK_SFT (0x1 << 1)
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#define RG_INT_EN_VOW1_SFT 2
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#define RG_INT_EN_VOW1_MASK 0x1
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#define RG_INT_EN_VOW1_MASK_SFT (0x1 << 2)
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#define RG_INT_MASK_VOW1_SFT 3
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#define RG_INT_MASK_VOW1_MASK 0x1
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#define RG_INT_MASK_VOW1_MASK_SFT (0x1 << 3)
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#define RG_INT_EN_RCS0_SFT 4
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#define RG_INT_EN_RCS0_MASK 0x1
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#define RG_INT_EN_RCS0_MASK_SFT (0x1 << 4)
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#define RG_INT_MASK_RCS0_SFT 5
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#define RG_INT_MASK_RCS0_MASK 0x1
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#define RG_INT_MASK_RCS0_MASK_SFT (0x1 << 5)
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/* PMRC_CON1_SET */
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#define RG_PMRC_CON1_SET_SFT 0
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#define RG_PMRC_CON1_SET_MASK 0xff
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#define RG_PMRC_CON1_SET_MASK_SFT (0xff << 0)
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/* PMRC_CON1_CLR */
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#define RG_PMRC_CON1_CLR_SFT 0
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#define RG_PMRC_CON1_CLR_MASK 0xff
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#define RG_PMRC_CON1_CLR_MASK_SFT (0xff << 0)
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/* AUXADC_CON0 */
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#define AUXADC_CK_AON_SFT 7
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#define AUXADC_CK_AON_MASK 0x1
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#define AUXADC_CK_AON_MASK_SFT (0x1 << 7)
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#define AUXADC_CK_AON_MD_SFT 6
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#define AUXADC_CK_AON_MD_MASK 0x1
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#define AUXADC_CK_AON_MD_MASK_SFT (0x1 << 6)
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#define AUXADC_CK_AON_GPS_SFT 5
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#define AUXADC_CK_AON_GPS_MASK 0x1
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#define AUXADC_CK_AON_GPS_MASK_SFT (0x1 << 5)
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#define AUXADC_SRCLKEN_CK_EN_SFT 4
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#define AUXADC_SRCLKEN_CK_EN_MASK 0x1
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#define AUXADC_SRCLKEN_CK_EN_MASK_SFT (0x1 << 4)
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#define AUXADC_STRUP_CK_ON_ENB_SFT 3
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#define AUXADC_STRUP_CK_ON_ENB_MASK 0x1
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#define AUXADC_STRUP_CK_ON_ENB_MASK_SFT (0x1 << 3)
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#define AUXADC_ADC_PWDB_SWCTRL_SFT 2
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#define AUXADC_ADC_PWDB_SWCTRL_MASK 0x1
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#define AUXADC_ADC_PWDB_SWCTRL_MASK_SFT (0x1 << 2)
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#define AUXADC_ADC_PWDB_SFT 1
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#define AUXADC_ADC_PWDB_MASK 0x1
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#define AUXADC_ADC_PWDB_MASK_SFT (0x1 << 1)
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/* AUXADC_TRIM_SEL2 */
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#define AUXADC_TRIM_CH4_SEL_SFT 0
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#define AUXADC_TRIM_CH4_SEL_MASK 0x3
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#define AUXADC_TRIM_CH4_SEL_MASK_SFT (0x3 << 0)
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#define AUXADC_TRIM_CH5_SEL_SFT 2
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#define AUXADC_TRIM_CH5_SEL_MASK 0x3
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#define AUXADC_TRIM_CH5_SEL_MASK_SFT (0x3 << 2)
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#define AUXADC_TRIM_CH9_SEL_SFT 4
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#define AUXADC_TRIM_CH9_SEL_MASK 0x3
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#define AUXADC_TRIM_CH9_SEL_MASK_SFT (0x3 << 4)
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#define AUXADC_TRIM_CH13_SEL_SFT 6
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#define AUXADC_TRIM_CH13_SEL_MASK 0x3
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#define AUXADC_TRIM_CH13_SEL_MASK_SFT (0x3 << 6)
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/* LDO_VAUD18_MULTI_SW_0 */
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#define RG_LDO_VAUD18_EN_1_SFT 0
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#define RG_LDO_VAUD18_EN_1_MASK 0x1
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#define RG_LDO_VAUD18_EN_1_MASK_SFT (0x1 << 0)
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/* LDO_VAUD18_MULTI_SW_1 */
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#define RG_LDO_VAUD18_EN_2_SFT 0
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#define RG_LDO_VAUD18_EN_2_MASK 0x1
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#define RG_LDO_VAUD18_EN_2_MASK_SFT (0x1 << 0)
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/* LDO_VAUD18_CON2 */
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#define RG_LDO_VAUD18_DUMMY_LOAD_SFT 0
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#define RG_LDO_VAUD18_DUMMY_LOAD_MASK 0x3
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#define RG_LDO_VAUD18_DUMMY_LOAD_MASK_SFT (0x3 << 0)
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#define RG_LDO_VAUD18_OP_MODE_SFT 2
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#define RG_LDO_VAUD18_OP_MODE_MASK 0x7
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#define RG_LDO_VAUD18_OP_MODE_MASK_SFT (0x7 << 2)
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#define RG_LDO_VAUD18_CK_SW_MODE_SFT 7
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#define RG_LDO_VAUD18_CK_SW_MODE_MASK 0x1
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#define RG_LDO_VAUD18_CK_SW_MODE_MASK_SFT (0x1 << 7)
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/* VPLL18_PMU_CON0 */
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#define RG_VPLL18_LDO_VREF_EN_VA32_SFT 0
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#define RG_VPLL18_LDO_VREF_EN_VA32_MASK 0x1
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#define RG_VPLL18_LDO_VREF_EN_VA32_MASK_SFT (0x1 << 0)
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#define RG_VPLL18_LDO_VREF_SEL_VA32_SFT 2
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#define RG_VPLL18_LDO_VREF_SEL_VA32_MASK 0x7
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#define RG_VPLL18_LDO_VREF_SEL_VA32_MASK_SFT (0x7 << 2)
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#define RG_VPLL18_LDO_VOWPLL_EN_VA18_SFT 6
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#define RG_VPLL18_LDO_VOWPLL_EN_VA18_MASK 0x1
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#define RG_VPLL18_LDO_VOWPLL_EN_VA18_MASK_SFT (0x1 << 6)
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#define RG_VPLL18_LDO_PLL208M_EN_VA18_SFT 7
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#define RG_VPLL18_LDO_PLL208M_EN_VA18_MASK 0x1
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#define RG_VPLL18_LDO_PLL208M_EN_VA18_MASK_SFT (0x1 << 7)
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#endif /* __MT6360_PRIVATE_H__ */
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