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https://github.com/physwizz/a155-U-u1.git
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312 lines
8.0 KiB
C
312 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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#include <linux/bitops.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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#include <linux/pm_qos.h>
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#ifdef CONFIG_UFSFEATURE
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#include "ufshcd.h"
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#include "ufsfeature.h"
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#endif
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_XOUFS_CTRL 0x140
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#define REG_UFS_REFCLK_CTRL 0x144
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#define REG_UFS_EXTREG 0x2100
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#define REG_UFS_MPHYCTRL 0x2200
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#define REG_UFS_MTK_HW_VER 0x2240
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#define REG_UFS_REJECT_MON 0x22AC
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#define REG_UFS_DEBUG_SEL 0x22C0
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#define REG_UFS_PROBE 0x22C8
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#define REG_UFS_DEBUG_SEL_B0 0x22D0
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#define REG_UFS_DEBUG_SEL_B1 0x22D4
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#define REG_UFS_DEBUG_SEL_B2 0x22D8
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#define REG_UFS_DEBUG_SEL_B3 0x22DC
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/*
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* Ref-clk control
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*
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* Values for register REG_UFS_REFCLK_CTRL
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*/
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#define REFCLK_RELEASE 0x0
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#define REFCLK_REQUEST BIT(0)
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#define REFCLK_ACK BIT(1)
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#define REFCLK_REQ_TIMEOUT_US 3000
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/*
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* Vendor specific pre-defined parameters
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*/
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#define UFS_MTK_LIMIT_NUM_LANES_RX 2
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#define UFS_MTK_LIMIT_NUM_LANES_TX 2
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#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G4
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#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G4
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#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
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#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
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#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
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#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* Vendor specific link state
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*/
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enum {
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VS_LINK_DISABLED = 0,
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VS_LINK_DOWN = 1,
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VS_LINK_UP = 2,
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VS_LINK_HIBERN8 = 3,
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VS_LINK_LOST = 4,
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VS_LINK_CFG = 5,
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};
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/*
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* Vendor specific host controller state
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*/
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enum {
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VS_HCE_RESET = 0,
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VS_HCE_BASE = 1,
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VS_HCE_OOCPR_WAIT = 2,
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VS_HCE_DME_RESET = 3,
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VS_HCE_MIDDLE = 4,
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VS_HCE_DME_ENABLE = 5,
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VS_HCE_DEFAULTS = 6,
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VS_HIB_IDLEEN = 7,
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VS_HIB_ENTER = 8,
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VS_HIB_ENTER_CONF = 9,
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VS_HIB_MIDDLE = 10,
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VS_HIB_WAITTIMER = 11,
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VS_HIB_EXIT_CONF = 12,
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VS_HIB_EXIT = 13,
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};
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/*
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* SiP commands
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*/
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#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
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#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
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#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
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#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
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#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
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#define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5)
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#define UFS_MTK_SIP_GET_VCC_INFO BIT(6)
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#define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7)
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/*
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* SMC call wapper function
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*/
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#define _ufs_mtk_smc(cmd, res, v1, v2, v3, v4, v5, v6) \
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arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
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cmd, v1, v2, v3, v4, v5, v6, &(res))
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#define _ufs_mtk_smc_0(cmd, res) \
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_ufs_mtk_smc(cmd, res, 0, 0, 0, 0, 0, 0)
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#define _ufs_mtk_smc_1(cmd, res, v1) \
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_ufs_mtk_smc(cmd, res, v1, 0, 0, 0, 0, 0)
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#define _ufs_mtk_smc_2(cmd, res, v1, v2) \
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_ufs_mtk_smc(cmd, res, v1, v2, 0, 0, 0, 0)
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#define _ufs_mtk_smc_3(cmd, res, v1, v2, v3) \
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_ufs_mtk_smc(cmd, res, v1, v2, v3, 0, 0, 0)
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#define _ufs_mtk_smc_4(cmd, res, v1, v2, v3, v4) \
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_ufs_mtk_smc(cmd, res, v1, v2, v3, v4, 0, 0)
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#define _ufs_mtk_smc_5(cmd, res, v1, v2, v3, v4, v5) \
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_ufs_mtk_smc(cmd, res, v1, v2, v3, v4, v5, 0)
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#define _ufs_mtk_smc_6(cmd, res, v1, v2, v3, v4, v5, v6) \
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_ufs_mtk_smc(cmd, res, v1, v2, v3, v4, v5, v6)
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#define _ufs_mtk_smc_selector(cmd, res, v1, v2, v3, v4, v5, v6, FUNC, ...) FUNC
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#define ufs_mtk_smc(...) \
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_ufs_mtk_smc_selector(__VA_ARGS__, \
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_ufs_mtk_smc_6(__VA_ARGS__), \
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_ufs_mtk_smc_5(__VA_ARGS__), \
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_ufs_mtk_smc_4(__VA_ARGS__), \
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_ufs_mtk_smc_3(__VA_ARGS__), \
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_ufs_mtk_smc_2(__VA_ARGS__), \
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_ufs_mtk_smc_1(__VA_ARGS__), \
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_ufs_mtk_smc_0(__VA_ARGS__) \
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)
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/* Sip UFS GET VCC INFO */
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enum {
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VCC_NONE = 0,
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VCC_1,
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VCC_2
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};
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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/*
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* Host capability
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*/
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enum ufs_mtk_host_caps {
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UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
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UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
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UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
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UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
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UFS_MTK_CAP_DEALY_AFTER_VCC_OFF = 1 << 4,
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/* Override UFS_MTK_CAP_BROKEN_VCC's behavior to
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* allow vccqx upstream to enter LPM
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*/
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UFS_MTK_CAP_FORCE_VSx_LPM = 1 << 5,
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};
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struct ufs_mtk_crypt_cfg {
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struct regulator *reg_vcore;
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struct clk *clk_crypt_perf;
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struct clk *clk_crypt_mux;
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struct clk *clk_crypt_lp;
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int vcore_volt;
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};
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struct ufs_mtk_hw_ver {
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u8 step;
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u8 minor;
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u8 major;
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};
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struct ufs_mtk_host {
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struct phy *mphy;
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struct regulator *reg_va09;
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struct reset_control *hci_reset;
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struct reset_control *unipro_reset;
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struct reset_control *crypto_reset;
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struct ufs_hba *hba;
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struct ufs_mtk_crypt_cfg *crypt;
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struct ufs_mtk_hw_ver hw_ver;
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enum ufs_mtk_host_caps caps;
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bool mphy_powered_on;
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bool unipro_lpm;
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bool ref_clk_enabled;
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u16 ref_clk_ungating_wait_us;
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u16 ref_clk_gating_wait_us;
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bool pm_qos_init;
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struct pm_qos_request pm_qos_req;
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bool qos_allowed;
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bool qos_enabled;
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bool boot_device;
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struct ufs_vreg *vcc;
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bool skip_flush;
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struct semaphore rpmb_sem;
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#if defined(CONFIG_UFSFEATURE)
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struct ufsf_feature ufsf;
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#endif
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};
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/*
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* IOCTL opcode for ufs queries has the following opcode after
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* SCSI_IOCTL_GET_PCI
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*/
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#define UFS_IOCTL_QUERY 0x5388
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/**
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* struct ufs_ioctl_query_data - used to transfer data to and from user via
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* ioctl
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* @opcode: type of data to query (descriptor/attribute/flag)
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* @idn: id of the data structure
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* @buf_size: number of allocated bytes/data size on return
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* @buffer: data location
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*
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* Received: buffer and buf_size (available space for transferred data)
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* Submitted: opcode, idn, length, buf_size
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*/
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struct ufs_ioctl_query_data {
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/*
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* User should select one of the opcode defined in "enum query_opcode".
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* Please check include/uapi/scsi/ufs/ufs.h for the definition of it.
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* Note that only UPIU_QUERY_OPCODE_READ_DESC,
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* UPIU_QUERY_OPCODE_READ_ATTR & UPIU_QUERY_OPCODE_READ_FLAG are
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* supported as of now. All other query_opcode would be considered
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* invalid.
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* As of now only read query operations are supported.
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*/
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__u32 opcode;
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/*
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* User should select one of the idn from "enum flag_idn" or "enum
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* attr_idn" or "enum desc_idn" based on whether opcode above is
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* attribute, flag or descriptor.
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* Please check include/uapi/scsi/ufs/ufs.h for the definition of it.
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*/
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__u8 idn;
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/*
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* User should specify the size of the buffer (buffer[0] below) where
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* it wants to read the query data (attribute/flag/descriptor).
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* As we might end up reading less data then what is specified in
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* buf_size. So we are updating buf_size to what exactly we have read.
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*/
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__u16 buf_size;
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/*
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* placeholder for the start of the data buffer where kernel will copy
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* the query data (attribute/flag/descriptor) read from the UFS device
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* Note:
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* For Read/Write Attribute you will have to allocate 4 bytes
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* For Read/Write Flag you will have to allocate 1 byte
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*/
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__u8 buffer[0];
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};
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enum {
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BOOTDEV_SDMMC = 1,
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BOOTDEV_UFS = 2
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};
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struct tag_bootmode {
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u32 size;
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u32 tag;
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u32 bootmode;
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u32 boottype;
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};
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#if IS_ENABLED(CONFIG_RPMB)
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struct rpmb_dev *ufs_mtk_rpmb_get_raw_dev(void);
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#endif
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#if defined(CONFIG_UFSFEATURE)
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static inline struct ufsf_feature *ufs_mtk_get_ufsf(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return &host->ufsf;
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}
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#endif
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#endif /* !_UFS_MEDIATEK_H */
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