mirror of
https://github.com/physwizz/a155-U-u1.git
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142 lines
4.6 KiB
C
142 lines
4.6 KiB
C
/*
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* Copyright (C) 2012-2020 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef _P61_H_
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#define _P61_H_
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#ifdef CONFIG_NFC_FEATURE_SN100U
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#define DEFAULT_BUFFER_SIZE 780
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#else
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#define DEFAULT_BUFFER_SIZE 258
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#endif
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#define P61_MAGIC 0xEB
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#if !defined(CONFIG_NFC_FEATURE_SN100U)
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#define P61_SET_PWR _IOW(P61_MAGIC, 0x01, unsigned long)
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#define P61_SET_DBG _IOW(P61_MAGIC, 0x02, unsigned long)
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#define P61_SET_POLL _IOW(P61_MAGIC, 0x03, unsigned long)
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/* To set SPI configurations like gpio, clks */
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#define P61_SET_SPI_CONFIG _IO(P61_MAGIC, 0x04)
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/* Set the baud rate of SPI master clock nonTZ */
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#define P61_ENABLE_SPI_CLK _IO(P61_MAGIC, 0x05)
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/* To disable spi core clock */
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#define P61_DISABLE_SPI_CLK _IO(P61_MAGIC, 0x06)
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/* only nonTZ +++++*/
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/* Transmit data to the device and retrieve data from it simultaneously.*/
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#define P61_RW_SPI_DATA _IOWR(P61_MAGIC, 0x07, unsigned long)
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/* only nonTZ -----*/
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/*
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* SPI Request NFCC to enable p61 power, only in param
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* Only for SPI
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* level 1 = Enable power
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* level 0 = Disable power
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*/
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#define P61_SET_SPM_PWR _IOW(P61_MAGIC, 0x08, unsigned int)
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/* SPI or DWP can call this ioctl to get the current
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* power state of P61
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*
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*/
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#define P61_GET_SPM_STATUS _IOR(P61_MAGIC, 0x09, unsigned int)
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#define P61_GET_ESE_ACCESS _IOW(P61_MAGIC, 0x0A, unsigned int)
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#define P61_SET_DWNLD_STATUS _IOW(P61_MAGIC, 0x0B, unsigned long)
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#else
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#define P61_SET_PWR _IOW(P61_MAGIC, 0x01, long)
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#define P61_SET_DBG _IOW(P61_MAGIC, 0x02, long)
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#define P61_SET_POLL _IOW(P61_MAGIC, 0x03, long)
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/* SPI Request NFCC to enable p61 power, only in param
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* Only for SPI
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* level 1 = Enable power
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* level 0 = Disable power
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*/
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#define P61_SET_SPM_PWR _IOW(P61_MAGIC, 0x04, long)
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/* SPI or DWP can call this ioctl to get the current
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* power state of P61
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*/
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#define P61_GET_SPM_STATUS _IOR(P61_MAGIC, 0x05, long)
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#define P61_SET_THROUGHPUT _IOW(P61_MAGIC, 0x06, long)
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#define P61_GET_ESE_ACCESS _IOW(P61_MAGIC, 0x07, long)
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#define P61_SET_POWER_SCHEME _IOW(P61_MAGIC, 0x08, long)
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#define P61_SET_DWNLD_STATUS _IOW(P61_MAGIC, 0x09, long)
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#define P61_INHIBIT_PWR_CNTRL _IOW(P61_MAGIC, 0x0A, long)
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#ifdef CONFIG_NFC_FEATURE_SN100U
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/*
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* SPI can call this IOCTL to perform the eSE COLD_RESET
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* via NFC driver.
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*/
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#define ESE_PERFORM_COLD_RESET _IOW(P61_MAGIC, 0x0C, long)
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#define PERFORM_RESET_PROTECTION _IOW(P61_MAGIC, 0x0D, long)
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#endif
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/* only nonTZ +++++*/
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/* Transmit data to the device and retrieve data from it simultaneously.*/
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#define P61_RW_SPI_DATA _IOWR(P61_MAGIC, 0x0F, unsigned long)
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/* only nonTZ -----*/
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#endif
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#ifdef CONFIG_COMPAT
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#define P61_SET_PWR_COMPAT _IOW(P61_MAGIC, 0x01, unsigned int)
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#define P61_SET_DBG_COMPAT _IOW(P61_MAGIC, 0x02, unsigned int)
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#define P61_SET_POLL_COMPAT _IOW(P61_MAGIC, 0x03, unsigned int)
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#define P61_SET_SPM_PWR_COMPAT _IOW(P61_MAGIC, 0x04, unsigned int)
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#define P61_GET_SPM_STATUS_COMPAT _IOR(P61_MAGIC, 0x05, unsigned int)
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#define P61_SET_THROUGHPUT_COMPAT _IOW(P61_MAGIC, 0x06, unsigned int)
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#define P61_GET_ESE_ACCESS_COMPAT _IOW(P61_MAGIC, 0x07, unsigned int)
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#define P61_SET_POWER_SCHEME_COMPAT _IOW(P61_MAGIC, 0x08, unsigned int)
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#define P61_SET_DWNLD_STATUS_COMPAT _IOW(P61_MAGIC, 0x09, unsigned int)
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#define P61_INHIBIT_PWR_CNTRL_COMPAT _IOW(P61_MAGIC, 0x0A, unsigned int)
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#define P61_RW_SPI_DATA_COMPAT _IOWR(P61_MAGIC, 0x0F, unsigned int)
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#ifdef CONFIG_NFC_FEATURE_SN100U
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#define ESE_PERFORM_COLD_RESET_COMPAT _IOW(P61_MAGIC, 0x0C, unsigned int)
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#define PERFORM_RESET_PROTECTION_COMPAT _IOW(P61_MAGIC, 0x0D, unsigned int)
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#endif
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#endif
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struct p61_ioctl_transfer {
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unsigned char *rx_buffer;
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unsigned char *tx_buffer;
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unsigned int len;
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};
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#ifdef CONFIG_COMPAT
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struct p61_ioctl_transfer32 {
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u32 rx_buffer;
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u32 tx_buffer;
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u32 len;
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};
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#endif
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struct p61_spi_platform_data {
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unsigned int irq_gpio;
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unsigned int rst_gpio;
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};
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enum {
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SPI_CLK, /* gate_spi_clk */
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SPI_SRC_CLK, /* ipclk_spi */
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MAX_SPI_CLK_CNT,
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};
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#endif
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