mirror of
https://github.com/physwizz/a155-U-u1.git
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318 lines
7.8 KiB
C
318 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef __HCLGEVF_CMD_H
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#define __HCLGEVF_CMD_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include "hnae3.h"
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#define HCLGEVF_CMDQ_TX_TIMEOUT 30000
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#define HCLGEVF_CMDQ_CLEAR_WAIT_TIME 200
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#define HCLGEVF_CMDQ_RX_INVLD_B 0
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#define HCLGEVF_CMDQ_RX_OUTVLD_B 1
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struct hclgevf_hw;
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struct hclgevf_dev;
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struct hclgevf_desc {
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__le16 opcode;
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__le16 flag;
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__le16 retval;
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__le16 rsv;
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__le32 data[6];
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};
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struct hclgevf_desc_cb {
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dma_addr_t dma;
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void *va;
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u32 length;
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};
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struct hclgevf_cmq_ring {
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dma_addr_t desc_dma_addr;
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struct hclgevf_desc *desc;
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struct hclgevf_desc_cb *desc_cb;
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struct hclgevf_dev *dev;
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u32 head;
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u32 tail;
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u16 buf_size;
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u16 desc_num;
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int next_to_use;
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int next_to_clean;
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u8 flag;
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spinlock_t lock; /* Command queue lock */
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};
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enum hclgevf_cmd_return_status {
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HCLGEVF_CMD_EXEC_SUCCESS = 0,
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HCLGEVF_CMD_NO_AUTH = 1,
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HCLGEVF_CMD_NOT_SUPPORTED = 2,
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HCLGEVF_CMD_QUEUE_FULL = 3,
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HCLGEVF_CMD_NEXT_ERR = 4,
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HCLGEVF_CMD_UNEXE_ERR = 5,
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HCLGEVF_CMD_PARA_ERR = 6,
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HCLGEVF_CMD_RESULT_ERR = 7,
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HCLGEVF_CMD_TIMEOUT = 8,
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HCLGEVF_CMD_HILINK_ERR = 9,
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HCLGEVF_CMD_QUEUE_ILLEGAL = 10,
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HCLGEVF_CMD_INVALID = 11,
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};
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enum hclgevf_cmd_status {
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HCLGEVF_STATUS_SUCCESS = 0,
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HCLGEVF_ERR_CSQ_FULL = -1,
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HCLGEVF_ERR_CSQ_TIMEOUT = -2,
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HCLGEVF_ERR_CSQ_ERROR = -3
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};
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struct hclgevf_cmq {
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struct hclgevf_cmq_ring csq;
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struct hclgevf_cmq_ring crq;
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u16 tx_timeout; /* Tx timeout */
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enum hclgevf_cmd_status last_status;
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};
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#define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0
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#define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1
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#define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2
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#define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3
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#define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4
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#define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5
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#define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
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#define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
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#define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
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#define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
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#define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
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#define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
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enum hclgevf_opcode_type {
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/* Generic command */
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HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
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HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
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HCLGEVF_OPC_QUERY_DEV_SPECS = 0x0050,
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/* TQP command */
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HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
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HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
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HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
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/* GRO command */
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HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10,
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/* RSS cmd */
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HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
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HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02,
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HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07,
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HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
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/* Mailbox cmd */
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HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
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};
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#define HCLGEVF_TQP_REG_OFFSET 0x80000
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#define HCLGEVF_TQP_REG_SIZE 0x200
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struct hclgevf_tqp_map {
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__le16 tqp_id; /* Absolute tqp id for in this pf */
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u8 tqp_vf; /* VF id */
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#define HCLGEVF_TQP_MAP_TYPE_PF 0
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#define HCLGEVF_TQP_MAP_TYPE_VF 1
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#define HCLGEVF_TQP_MAP_TYPE_B 0
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#define HCLGEVF_TQP_MAP_EN_B 1
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u8 tqp_flag; /* Indicate it's pf or vf tqp */
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__le16 tqp_vid; /* Virtual id in this pf/vf */
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u8 rsv[18];
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};
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#define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
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enum hclgevf_int_type {
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HCLGEVF_INT_TX = 0,
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HCLGEVF_INT_RX,
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HCLGEVF_INT_EVENT,
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};
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struct hclgevf_ctrl_vector_chain {
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u8 int_vector_id;
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u8 int_cause_num;
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#define HCLGEVF_INT_TYPE_S 0
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#define HCLGEVF_INT_TYPE_M 0x3
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#define HCLGEVF_TQP_ID_S 2
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#define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S)
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__le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
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u8 vfid;
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u8 resv;
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};
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enum HCLGEVF_CAP_BITS {
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HCLGEVF_CAP_UDP_GSO_B,
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HCLGEVF_CAP_QB_B,
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HCLGEVF_CAP_FD_FORWARD_TC_B,
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HCLGEVF_CAP_PTP_B,
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HCLGEVF_CAP_INT_QL_B,
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HCLGEVF_CAP_SIMPLE_BD_B,
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HCLGEVF_CAP_TX_PUSH_B,
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HCLGEVF_CAP_PHY_IMP_B,
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HCLGEVF_CAP_TQP_TXRX_INDEP_B,
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HCLGEVF_CAP_HW_PAD_B,
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HCLGEVF_CAP_STASH_B,
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};
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#define HCLGEVF_QUERY_CAP_LENGTH 3
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struct hclgevf_query_version_cmd {
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__le32 firmware;
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__le32 hardware;
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__le32 rsv;
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__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
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};
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#define HCLGEVF_MSIX_OFT_ROCEE_S 0
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#define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
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#define HCLGEVF_VEC_NUM_S 0
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#define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
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struct hclgevf_query_res_cmd {
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__le16 tqp_num;
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__le16 reserved;
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__le16 msixcap_localid_ba_nic;
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__le16 msixcap_localid_ba_rocee;
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__le16 vf_intr_vector_number;
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__le16 rsv[7];
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};
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#define HCLGEVF_GRO_EN_B 0
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struct hclgevf_cfg_gro_status_cmd {
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u8 gro_en;
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u8 rsv[23];
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};
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#define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4
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#define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4
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#define HCLGEVF_RSS_HASH_KEY_NUM 16
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struct hclgevf_rss_config_cmd {
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u8 hash_config;
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u8 rsv[7];
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u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
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};
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struct hclgevf_rss_input_tuple_cmd {
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u8 ipv4_tcp_en;
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u8 ipv4_udp_en;
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u8 ipv4_sctp_en;
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u8 ipv4_fragment_en;
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u8 ipv6_tcp_en;
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u8 ipv6_udp_en;
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u8 ipv6_sctp_en;
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u8 ipv6_fragment_en;
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u8 rsv[16];
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};
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#define HCLGEVF_RSS_CFG_TBL_SIZE 16
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struct hclgevf_rss_indirection_table_cmd {
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u16 start_table_index;
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u16 rss_set_bitmap;
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u8 rsv[4];
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u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
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};
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#define HCLGEVF_RSS_TC_OFFSET_S 0
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#define HCLGEVF_RSS_TC_OFFSET_M (0x3ff << HCLGEVF_RSS_TC_OFFSET_S)
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#define HCLGEVF_RSS_TC_SIZE_S 12
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#define HCLGEVF_RSS_TC_SIZE_M (0x7 << HCLGEVF_RSS_TC_SIZE_S)
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#define HCLGEVF_RSS_TC_VALID_B 15
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#define HCLGEVF_MAX_TC_NUM 8
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struct hclgevf_rss_tc_mode_cmd {
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u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
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u8 rsv[8];
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};
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#define HCLGEVF_LINK_STS_B 0
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#define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
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struct hclgevf_link_status_cmd {
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u8 status;
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u8 rsv[23];
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};
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#define HCLGEVF_RING_ID_MASK 0x3ff
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#define HCLGEVF_TQP_ENABLE_B 0
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struct hclgevf_cfg_com_tqp_queue_cmd {
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__le16 tqp_id;
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__le16 stream_id;
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u8 enable;
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u8 rsv[19];
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};
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struct hclgevf_cfg_tx_queue_pointer_cmd {
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__le16 tqp_id;
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__le16 tx_tail;
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__le16 tx_head;
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__le16 fbd_num;
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__le16 ring_offset;
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u8 rsv[14];
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};
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#define HCLGEVF_TYPE_CRQ 0
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#define HCLGEVF_TYPE_CSQ 1
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#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
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#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
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#define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
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#define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
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#define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
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#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
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#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c
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#define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
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#define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
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#define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
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/* this bit indicates that the driver is ready for hardware reset */
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#define HCLGEVF_NIC_SW_RST_RDY_B 16
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#define HCLGEVF_NIC_SW_RST_RDY BIT(HCLGEVF_NIC_SW_RST_RDY_B)
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#define HCLGEVF_NIC_CMQ_DESC_NUM 1024
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#define HCLGEVF_NIC_CMQ_DESC_NUM_S 3
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#define HCLGEVF_NIC_CMDQ_INT_SRC_REG 0x27100
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#define HCLGEVF_QUERY_DEV_SPECS_BD_NUM 4
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struct hclgevf_dev_specs_0_cmd {
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__le32 rsv0;
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__le32 mac_entry_num;
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__le32 mng_entry_num;
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__le16 rss_ind_tbl_size;
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__le16 rss_key_size;
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__le16 int_ql_max;
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u8 max_non_tso_bd_num;
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u8 rsv1[5];
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};
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static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
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{
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writel(value, base + reg);
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}
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static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
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{
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u8 __iomem *reg_addr = READ_ONCE(base);
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return readl(reg_addr + reg);
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}
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#define hclgevf_write_dev(a, reg, value) \
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hclgevf_write_reg((a)->io_base, (reg), (value))
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#define hclgevf_read_dev(a, reg) \
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hclgevf_read_reg((a)->io_base, (reg))
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#define HCLGEVF_SEND_SYNC(flag) \
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((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
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int hclgevf_cmd_init(struct hclgevf_dev *hdev);
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void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
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int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
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int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
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void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
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enum hclgevf_opcode_type opcode,
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bool is_read);
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#endif
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