mirror of
https://github.com/physwizz/a155-U-u1.git
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173 lines
6.8 KiB
C
173 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __VCP_REG_H
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#define __VCP_REG_H
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#define VCP_SEMAPHORE (vcpreg.cfg + 0x0018)
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#define VCP_VCP2SPM_VOL_LV (vcpreg.cfg + 0x0020)
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/* VCP to SPM IPC clear */
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#define VCP_TO_SPM_REG (vcpreg.cfg + 0x0094)
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#define R_GIPC_IN_SET (vcpreg.cfg + 0x0098)
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#define R_GIPC_IN_CLR (vcpreg.cfg + 0x009c)
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#define B_GIPC0_SETCLR_0 (1 << 0)
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#define B_GIPC0_SETCLR_1 (1 << 1)
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#define B_GIPC0_SETCLR_2 (1 << 2)
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#define B_GIPC0_SETCLR_3 (1 << 3)
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#define B_GIPC1_SETCLR_0 (1 << 4)
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#define B_GIPC1_SETCLR_1 (1 << 5)
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#define B_GIPC1_SETCLR_2 (1 << 6)
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#define B_GIPC1_SETCLR_3 (1 << 7)
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#define B_GIPC2_SETCLR_0 (1 << 8)
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#define B_GIPC2_SETCLR_1 (1 << 9)
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#define B_GIPC2_SETCLR_2 (1 << 10)
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#define B_GIPC2_SETCLR_3 (1 << 11)
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#define B_GIPC3_SETCLR_0 (1 << 12)
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#define B_GIPC3_SETCLR_1 (1 << 13)
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#define B_GIPC3_SETCLR_2 (1 << 14)
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#define B_GIPC3_SETCLR_3 (1 << 15)
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#define B_GIPC4_SETCLR_0 (1 << 16)
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#define B_GIPC4_SETCLR_1 (1 << 17)
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#define B_GIPC4_SETCLR_2 (1 << 18)
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#define B_GIPC4_SETCLR_3 (1 << 19)
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#define VCP_BUS_DEBUG_OUT (vcpreg.cfg + 0x0150)
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#define R_CORE0_SW_RSTN_CLR (vcpreg.cfg_core0 + 0x0000)
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#define R_CORE1_SW_RSTN_CLR (vcpreg.cfg_core1 + 0x0000)
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#define R_CORE0_SW_RSTN_SET (vcpreg.cfg_core0 + 0x0004)
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#define R_CORE1_SW_RSTN_SET (vcpreg.cfg_core1 + 0x0004)
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#define R_CORE0_DBG_CTRL (vcpreg.cfg_core0 + 0x0010)
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#define R_CORE1_DBG_CTRL (vcpreg.cfg_core1 + 0x0010)
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#define M_CORE_TBUF_DBG_SEL (7 << 4)
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#define S_CORE_TBUF_DBG_SEL (4)
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#define M_CORE_TBUF_DBG_SEL_RV55 (0xfff0ff0f)
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#define S_CORE_TBUF_S (4)
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#define S_CORE_TBUF1_S (16)
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#define R_CORE0_WDT_IRQ (vcpreg.cfg_core0 + 0x0030)
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#define R_CORE1_WDT_IRQ (vcpreg.cfg_core1 + 0x0030)
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#define B_WDT_IRQ (1 << 0)
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#define R_CORE0_WDT_CFG (vcpreg.cfg_core0 + 0x0034)
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#define R_CORE1_WDT_CFG (vcpreg.cfg_core1 + 0x0034)
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#define V_INSTANT_WDT 0x80000000
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#define R_CORE0_STATUS (vcpreg.cfg_core0 + 0x0070)
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#define B_CORE_GATED (1 << 0)
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#define B_HART0_HALT (1 << 1)
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#define B_HART1_HALT (1 << 2)
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#define R_CORE0_MON_PC (vcpreg.cfg_core0 + 0x0080)
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#define R_CORE0_MON_LR (vcpreg.cfg_core0 + 0x0084)
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#define R_CORE0_MON_SP (vcpreg.cfg_core0 + 0x0088)
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#define R_CORE0_TBUF_WPTR (vcpreg.cfg_core0 + 0x008c)
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#define R_CORE0_MON_PC_LATCH (vcpreg.cfg_core0 + 0x00d0)
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#define R_CORE0_MON_LR_LATCH (vcpreg.cfg_core0 + 0x00d4)
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#define R_CORE0_MON_SP_LATCH (vcpreg.cfg_core0 + 0x00d8)
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#define R_CORE0_T1_MON_PC (vcpreg.cfg_core0 + 0x0160)
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#define R_CORE0_T1_MON_LR (vcpreg.cfg_core0 + 0x0164)
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#define R_CORE0_T1_MON_SP (vcpreg.cfg_core0 + 0x0168)
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#define R_CORE0_T1_MON_PC_LATCH (vcpreg.cfg_core0 + 0x0170)
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#define R_CORE0_T1_MON_LR_LATCH (vcpreg.cfg_core0 + 0x0174)
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#define R_CORE0_T1_MON_SP_LATCH (vcpreg.cfg_core0 + 0x0178)
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#define R_CORE1_STATUS (vcpreg.cfg_core1 + 0x0070)
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#define R_CORE1_MON_PC (vcpreg.cfg_core1 + 0x0080)
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#define R_CORE1_MON_LR (vcpreg.cfg_core1 + 0x0084)
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#define R_CORE1_MON_SP (vcpreg.cfg_core1 + 0x0088)
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#define R_CORE1_TBUF_WPTR (vcpreg.cfg_core1 + 0x008c)
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#define R_CORE1_MON_PC_LATCH (vcpreg.cfg_core1 + 0x00d0)
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#define R_CORE1_MON_LR_LATCH (vcpreg.cfg_core1 + 0x00d4)
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#define R_CORE1_MON_SP_LATCH (vcpreg.cfg_core1 + 0x00d8)
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#define R_CORE1_T1_MON_PC (vcpreg.cfg_core1 + 0x0160)
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#define R_CORE1_T1_MON_LR (vcpreg.cfg_core1 + 0x0164)
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#define R_CORE1_T1_MON_SP (vcpreg.cfg_core1 + 0x0168)
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#define R_CORE1_T1_MON_PC_LATCH (vcpreg.cfg_core1 + 0x0170)
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#define R_CORE1_T1_MON_LR_LATCH (vcpreg.cfg_core1 + 0x0174)
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#define R_CORE1_T1_MON_SP_LATCH (vcpreg.cfg_core1 + 0x0178)
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#define R_CORE0_TBUF_DATA31_0 (vcpreg.cfg_core0 + 0x00e0)
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#define R_CORE0_TBUF_DATA63_32 (vcpreg.cfg_core0 + 0x00e4)
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#define R_CORE0_TBUF_DATA95_64 (vcpreg.cfg_core0 + 0x00e8)
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#define R_CORE0_TBUF_DATA127_96 (vcpreg.cfg_core0 + 0x00ec)
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#define R_CORE0_TBUF1_DATA31_0 (vcpreg.cfg_core0 + 0x00f0)
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#define R_CORE0_TBUF1_DATA63_32 (vcpreg.cfg_core0 + 0x00f4)
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#define R_CORE0_TBUF1_DATA95_64 (vcpreg.cfg_core0 + 0x00f8)
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#define R_CORE0_TBUF1_DATA127_96 (vcpreg.cfg_core0 + 0x00fc)
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#define R_CORE1_TBUF_DATA31_0 (vcpreg.cfg_core1 + 0x00e0)
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#define R_CORE1_TBUF_DATA63_32 (vcpreg.cfg_core1 + 0x00e4)
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#define R_CORE1_TBUF_DATA95_64 (vcpreg.cfg_core1 + 0x00e8)
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#define R_CORE1_TBUF_DATA127_96 (vcpreg.cfg_core1 + 0x00ec)
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#define R_CORE1_TBUF1_DATA31_0 (vcpreg.cfg_core1 + 0x00f0)
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#define R_CORE1_TBUF1_DATA63_32 (vcpreg.cfg_core1 + 0x00f4)
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#define R_CORE1_TBUF1_DATA95_64 (vcpreg.cfg_core1 + 0x00f8)
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#define R_CORE1_TBUF1_DATA127_96 (vcpreg.cfg_core1 + 0x00fc)
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#define VCP_A_GENERAL_REG0 (vcpreg.cfg_core0 + 0x0040)
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/* DRAM reserved address and size */
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#define VCP_A_GENERAL_REG1 (vcpreg.cfg_core0 + 0x0044)
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#define DRAM_RESV_ADDR_REG VCP_A_GENERAL_REG1
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#define VCP_A_GENERAL_REG2 (vcpreg.cfg_core0 + 0x0048)
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#define DRAM_RESV_SIZE_REG VCP_A_GENERAL_REG2
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/*EXPECTED_FREQ_REG*/
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#define VCP_A_GENERAL_REG3 (vcpreg.cfg_core0 + 0x004C)
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#define EXPECTED_FREQ_REG VCP_A_GENERAL_REG3
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/*CURRENT_FREQ_REG*/
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#define VCP_A_GENERAL_REG4 (vcpreg.cfg_core0 + 0x0050)
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#define CURRENT_FREQ_REG VCP_A_GENERAL_REG4
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/*VCP_GPR_CM4_A_REBOOT*/
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#define VCP_A_GENERAL_REG5 (vcpreg.cfg_core0 + 0x0054)
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#define VCP_GPR_CORE0_REBOOT VCP_A_GENERAL_REG5
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#define CORE_RDY_TO_REBOOT 0x34
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#define CORE_REBOOT_OK 0x1
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#define VCP_GPR_CORE1_REBOOT (vcpreg.cfg_core1 + 0x0054)
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#define VCP_A_GENERAL_REG6 (vcpreg.cfg_core0 + 0x0058)
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#define VCP_A_GENERAL_REG7 (vcpreg.cfg_core0 + 0x005C)
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/* bus tracker reg */
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#define VCP_BUS_DBG_CON (vcpreg.bus_tracker)
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#define VCP_BUS_DBG_AR_TRACK0_L (vcpreg.bus_tracker + 0x100)
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#define VCP_BUS_DBG_AR_TRACK1_L (vcpreg.bus_tracker + 0x108)
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#define VCP_BUS_DBG_AR_TRACK2_L (vcpreg.bus_tracker + 0x110)
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#define VCP_BUS_DBG_AR_TRACK3_L (vcpreg.bus_tracker + 0x118)
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#define VCP_BUS_DBG_AR_TRACK4_L (vcpreg.bus_tracker + 0x120)
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#define VCP_BUS_DBG_AR_TRACK5_L (vcpreg.bus_tracker + 0x128)
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#define VCP_BUS_DBG_AR_TRACK6_L (vcpreg.bus_tracker + 0x130)
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#define VCP_BUS_DBG_AR_TRACK7_L (vcpreg.bus_tracker + 0x138)
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#define VCP_BUS_DBG_AW_TRACK0_L (vcpreg.bus_tracker + 0x300)
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#define VCP_BUS_DBG_AW_TRACK1_L (vcpreg.bus_tracker + 0x308)
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#define VCP_BUS_DBG_AW_TRACK2_L (vcpreg.bus_tracker + 0x310)
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#define VCP_BUS_DBG_AW_TRACK3_L (vcpreg.bus_tracker + 0x318)
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#define VCP_BUS_DBG_AW_TRACK4_L (vcpreg.bus_tracker + 0x320)
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#define VCP_BUS_DBG_AW_TRACK5_L (vcpreg.bus_tracker + 0x328)
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#define VCP_BUS_DBG_AW_TRACK6_L (vcpreg.bus_tracker + 0x330)
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#define VCP_BUS_DBG_AW_TRACK7_L (vcpreg.bus_tracker + 0x338)
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#define R_SEC_CTRL (vcpreg.cfg_sec + 0x0000)
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#define B_CORE0_CACHE_DBG_EN (1 << 28)
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#define B_CORE1_CACHE_DBG_EN (1 << 29)
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#define R_CORE0_CACHE_RAM (vcpreg.l1cctrl + 0x00000)
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#define R_CORE1_CACHE_RAM (vcpreg.l1cctrl + 0x20000)
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#define VCP_GCE_MMU (vcpreg.cfg_mmu + 0x0000)
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#define B_MMU_EN (0x3 << 14)
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#endif
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