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45 lines
769 B
C
45 lines
769 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __SSC_SYSFS_H__
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#define __SSC_SYSFS_H__
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enum MT_SSC_REG {
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PW_SSC_BASIC_SET = 0,
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PW_SSC_SRAM_SW_REQ1,
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PW_SSC_SRAM_SW_REQ2,
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PW_SSC_SRAM_SW_REQ3,
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PW_SSC_SRAM_SW_REQ4,
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PW_SSC_VGPU_SET,
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PW_SSC_VISP_SET,
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PW_SSC_VCORE_SET,
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PW_SSC_FORCE_SET,
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PW_SSC_FORCE_CUR,
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PW_SSC_FORCE_TAR,
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PW_SSC_VSRAM_STA,
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PW_SSC_VGPU_STA,
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PW_SSC_VISP_STA,
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PW_SSC_VCORE_STA,
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PW_SSC_MUMTAS_STA,
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PW_SSC_MUMTAS_SET,
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PW_SSC_MUMTAS_CLR,
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PW_SSC_VSRAM_MASK,
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PW_SSC_VGPU_MASK,
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PW_SSC_VISP_MASK,
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PW_SSC_VCORE_MASK,
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PW_SSC_RESERVED,
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PW_SSC_VGPU_RETRY,
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PW_SSC_VISP_RETRY,
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PW_SSC_VCORE_RETRY,
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PW_SSC_TIMEOUT_1,
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PW_SSC_TIMEOUT_2,
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PW_SSC_TIMEOUT_STA,
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PW_SSC_IRQ_SET,
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PW_SSC_REG_NUM,
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};
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#endif
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