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285 lines
6.0 KiB
C
285 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Samuel Hsieh <samuel.hsieh@mediatek.com>
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*/
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#ifndef _MTK_MDPM_PLATFORM_H_
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#define _MTK_MDPM_PLATFORM_H_
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#ifdef DISABLE_DLPT_FEATURE
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#define MD_POWER_METER_ENABLE 0
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#else
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#define MD_POWER_METER_ENABLE 1
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#endif
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#define GET_MD_SCEANRIO_BY_SHARE_MEMORY
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#define MAX_MD1_POWER 4000 /* mW */
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#define MAX_TX_POWER 3500 /* mW */
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#define SHARE_REG_MASK 0xFFFF
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#define DBM_TABLE_SIZE 2
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#define DBM_SECTION_MASK 0x1F
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#define END_GUARDING_PATERN (2)
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#define DBM_RESERVE_OFFSET (128 - SHARE_MEM_BLOCK_NUM - END_GUARDING_PATERN)
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#define DBM_GEN95_OFFSET (90 + DBM_RESERVE_OFFSET)
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#define MDPM_SHARE_MEMORY_MASK 0xFFFFFFFF
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#define MDPM_SHARE_MEMORY_SHIFT 0
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#define VERSION_CHECK_VERSION_MASK 0xFFFF
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#define VERSION_CHECK_VERSION_SHIFT 0
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#define VERSION_CHECK_VALID_MASK 0x3
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#define VERSION_CHECK_VALID_SHIFT 16
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#define RF_HW_VERSION_MASK 0x3
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#define RF_HW_VERSION_SHIFT 0
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#define RF_HW_VALID_MASK 0x3
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#define RF_HW_VALID_SHIFT 2
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#define AP_MD_MDPM_VERSION 0x1001
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#define VERSION_VALID 0x3
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#define VERSION_INVALID 0x1
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#define VERSION_INIT 0x0
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#define RF_HW_VALID 0x3
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#define RF_HW_INVALID 0x1
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#define RF_HW_INIT 0x0
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enum section_level_tbl {
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DBM_SECTION_1 = 0,
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DBM_SECTION_2 = 5,
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DBM_SECTION_3 = 10,
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DBM_SECTION_4 = 15,
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DBM_SECTION_5 = 20,
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DBM_SECTION_6 = 25,
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DBM_SECTION_7 = 32,
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DBM_SECTION_8 = 37,
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DBM_SECTION_9 = 42,
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DBM_SECTION_10 = 47,
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DBM_SECTION_11 = 52,
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DBM_SECTION_12 = 57,
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DBM_SECTION_NUM = 12
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};
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enum md_scenario {
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S_STANDBY = 0,
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S_2G_IDLE,
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S_2G_NON_IDLE,
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S_2G_NON_CONN,
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S_2G_CONN,
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S_C2K_DATALINK,
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S_C2K_SHDR,
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S_C2K_1X_TRAFFIC,
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S_C2K_PAGING,
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S_C2K_EVDO,
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S_C2K_1X,
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S_3G_TDD_PAGING,
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S_3G_TDD_TALKING,
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S_3G_TDD_DATALINK,
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S_3G_IDLE,
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S_3G_WCDMA_TALKING,
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S_3G_1C,
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S_3G_2C,
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S_3G_UL1_TALKING,
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S_3G_UL1_PAGING,
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S_3G_UL1_DATA_1C,
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S_3G_UL1_DATA_2C,
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S_4G_0D0U,
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S_4G_1CC,
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S_4G_2CC,
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S_4G_3CC,
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S_4G_4CC,
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S_4G_5CC,
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S_4G_3D1U,
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S_4G_3D2U,
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S_4G_4D1U,
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S_4G_4D2U,
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S_4G_4D3U,
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S_4G_POS,
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S_5G_1CC_2CC,
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S_5G_1CC_2CC_4G_4CC,
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S_5G_1CC_2CC_4G_1CC,
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S_5G_NR_0CC_1TG,
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S_5G_NR_0CC_2TG,
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S_5G_NR_0CC_3TG,
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S_5G_FR1_1CC_1TG,
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S_5G_FR1_2CC_1TG,
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S_5G_FR1_3_4CC_1TG,
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S_5G_FR1_1_4CC_2TG,
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S_5G_FR2_1CC_1TG,
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S_5G_FR2_2_4CC_1TG,
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S_5G_FR2_5_8CC_1TG,
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S_5G_FR2_1_8CC_2TG,
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S_5G_FR1_FR2_3TG,
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S_5G_FR1_FR2,
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S_5G_FR1_1CC_1TG_4G_1CC,
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S_5G_FR2_1CC_1TG_4G_1CC_NR_0CC,
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S_5G_FR2_2_4CC_1TG_4G_1CC,
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S_5G_FR1_FR2_4G,
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S_4G_POS_URGENT,
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S_4G_5G_POS_URGENT,
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SCENARIO_NUM
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};
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enum tx_rat_type {
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RAT_2G = 1,
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RAT_3G,
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RAT_3GTDD,
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RAT_4G,
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RAT_C2K,
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RAT_5G,
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RAT_MMW,
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RAT_NUM = RAT_MMW,
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};
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enum tx_power_table {
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TX_2G_DBM = 0,
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TX_3G_DBM,
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TX_3GTDD_DBM,
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TX_4G_CC0_DBM,
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TX_4G_CC1_DBM,
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TX_C2K_DBM,
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TX_NR_CC0_DBM,
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TX_NR_CC1_DBM,
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TX_MMW_TX1_DBM,
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TX_MMW_TX2_DBM,
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TX_DBM_NUM
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};
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enum share_mem_mapping { /* each of 8 bytes */
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DBM_TABLE_2_START = 0,
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DBM_TABLE_2_END = 40,
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SECTION_LEVEL_2_START = 41,
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M_MMW_SECTION_LEVEL = 78,
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M_MMW_SECTION_1_LEVEL,
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M_MMW_SECTION_2_LEVEL,
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M_MMW_SECTION_3_LEVEL,
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SECTION_LEVEL_2_END = M_MMW_SECTION_3_LEVEL,
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DBM_TABLE_START,
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M_MMW_DBM_TABLE = DBM_TABLE_START,
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M_MMW_DBM_1_TABLE,
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M_2G_DBM_TABLE,
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M_3G_DBM_TABLE,
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M_4G_DBM_TABLE,
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M_4G_DBM_1_TABLE,
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M_4G_DBM_2_TABLE,
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M_4G_DBM_3_TABLE,
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M_NR_DBM_TABLE,
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M_NR_DBM_1_TABLE,
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M_NR_DBM_2_TABLE,
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M_NR_DBM_3_TABLE,
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M_MMW_DBM_2_TABLE,
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M_MMW_DBM_3_TABLE,
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M_4G_DBM_10_TABLE,
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M_2G_DBM_1_TABLE,
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M_3G_DBM_1_TABLE,
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M_TDD_DBM_TABLE,
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M_C2K_DBM_1_TABLE,
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M_C2K_DBM_2_TABLE,
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M_C2K_DBM_3_TABLE,
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M_TDD_DBM_1_TABLE,
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DBM_TABLE_END = M_TDD_DBM_1_TABLE,
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SECTION_LEVEL_START,
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M_2G_SECTION_LEVEL = SECTION_LEVEL_START,
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M_3G_SECTION_LEVEL,
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M_4G_SECTION_LEVEL,
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M_NR_SECTION_LEVEL,
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M_NR_SECTION_1_LEVEL,
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M_NR_SECTION_2_LEVEL,
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M_NR_SECTION_3_LEVEL,
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M_4G_SECTION_5_LEVEL,
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M_4G_SECTION_6_LEVEL,
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M_4G_SECTION_7_LEVEL,
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M_MD_SCENARIO,
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M_2G_SECTION_1_LEVEL,
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M_3G_SECTION_1_LEVEL,
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M_4G_SECTION_9_LEVEL,
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M_VERSION_CHECK,
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M_TDD_SECTION_LEVEL,
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M_C2K_SECTION_1_LEVEL,
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M_RF_HW,
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M_C2K_SECTION_2_LEVEL,
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M_TDD_SECTION_1_LEVEL,
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SECTION_LEVEL_END = M_TDD_SECTION_1_LEVEL,
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SHARE_MEM_BLOCK_NUM
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};
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#define MAX_DBM_FUNC_NUM 5
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#define MAX_MDPM_NAME_LEN 32
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#define RF_HW_NUM 2
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#define SHARE_MEM_SIZE (SHARE_MEM_BLOCK_NUM)
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struct md_power_status {
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char scenario_name[MAX_MDPM_NAME_LEN];
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enum md_scenario scenario_id;
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enum tx_rat_type rat;
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enum mdpm_power_type power_type;
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int dbm_section;
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int scanario_power;
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int rfhw_sel;
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int pa_power;
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int rf_power;
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int tx_power;
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int total_power;
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};
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struct tx_power_type_t {
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int max[DBM_SECTION_NUM];
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int avg[DBM_SECTION_NUM];
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};
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struct rfhw_power_t {
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struct tx_power_type_t pa_power;
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struct tx_power_type_t rf_power;
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int section[DBM_SECTION_NUM];
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};
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struct tx_power {
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char dbm_name[MAX_MDPM_NAME_LEN];
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enum share_mem_mapping shm_dbm_idx[DBM_TABLE_SIZE];
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enum share_mem_mapping shm_sec_idx[DBM_TABLE_SIZE];
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struct rfhw_power_t *rfhw;
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};
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struct scenario_power_type_t {
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int max;
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int avg;
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};
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struct mdpm_scenario {
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u32 scenario_reg;
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char scenario_name[MAX_MDPM_NAME_LEN];
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struct scenario_power_type_t *scenario_power;
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enum tx_rat_type tx_power_rat[MAX_DBM_FUNC_NUM];
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int tx_power_rat_sum;
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int (*tx_power_func)(u32 *dbm_mem, u32 *old_dbm_mem,
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enum tx_rat_type rat, enum mdpm_power_type power_type,
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struct md_power_status *md_power_s);
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};
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struct mdpm_data {
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struct device *dev;
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unsigned int platform;
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struct mdpm_scenario *scenario_power_t;
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struct tx_power *tx_power_t;
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void *prority_t;
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};
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extern void mt_mdpm_init(void);
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extern void init_md1_section_level(u32 *share_mem);
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extern void init_version_check(u32 *share_mem);
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extern unsigned int get_md1_status_reg(void);
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extern unsigned int get_md1_scenario(u32 share_reg,
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enum mdpm_power_type power_type);
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extern int get_md1_scenario_power(unsigned int scenario,
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enum mdpm_power_type power_type, struct md_power_status *mdpm_pwr_sta);
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extern int get_md1_tx_power(enum md_scenario scenario, u32 *share_mem,
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enum mdpm_power_type power_type, struct md_power_status *mdpm_pwr_sta);
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#ifdef GET_MD_SCEANRIO_BY_SHARE_MEMORY
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extern unsigned int get_md1_scenario_by_shm(u32 *share_mem);
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#endif
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#endif /* _MTK_MDPM_PLATFORM_H_ */
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