mirror of
https://github.com/physwizz/a155-U-u1.git
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4762 lines
201 KiB
C
4762 lines
201 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#define pr_fmt(fmt) "mtk_iommu: debug " fmt
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/*
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* For IOMMU EP/bring up phase, you must be enable "IOMMU_BRING_UP".
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* If you need to do some special config, you can also use this macro.
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*/
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#define IOMMU_BRING_UP (0)
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/list_sort.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/sched/clock.h>
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#include <linux/export.h>
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#include <dt-bindings/memory/mtk-memory-port.h>
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#include <trace/hooks/iommu.h>
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#if IS_ENABLED(CONFIG_MTK_AEE_FEATURE) && !IOMMU_BRING_UP
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#include <aee.h>
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#endif
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#include "mtk_iommu.h"
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#include "iommu_secure.h"
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#include "iommu_debug.h"
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#include "iommu_iova_dbg.h"
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#define ERROR_LARB_PORT_ID 0xFFFF
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#define F_MMU_INT_TF_MSK GENMASK(12, 2)
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#define F_MMU_INT_TF_CCU_MSK GENMASK(12, 7)
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#define F_MMU_INT_TF_LARB(id) FIELD_GET(GENMASK(13, 7), id)
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#define F_MMU_INT_TF_PORT(id) FIELD_GET(GENMASK(6, 2), id)
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#define F_APU_MMU_INT_TF_MSK(id) FIELD_GET(GENMASK(11, 7), id)
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enum mtk_iova_space {
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MTK_IOVA_SPACE0, /* 0GB ~ 4GB */
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MTK_IOVA_SPACE1, /* 4GB ~ 8GB */
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MTK_IOVA_SPACE2, /* 8GB ~ 12GB */
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MTK_IOVA_SPACE3, /* 12GB ~ 16GB */
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MTK_IOVA_SPACE_NUM
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};
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enum port_type {
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NORMAL,
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CCU_FAKE,
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GCE_VIDEOUP_FAKE
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};
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static struct iova_buf_list iova_list = {.init_flag = ATOMIC_INIT(0)};
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#if IS_ENABLED(CONFIG_MTK_AEE_FEATURE) && !IOMMU_BRING_UP
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#define m4u_aee_print(string, args...) do {\
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char m4u_name[150];\
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if (snprintf(m4u_name, 150, "[M4U]"string, ##args) < 0) \
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break; \
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aee_kernel_warning_api(__FILE__, __LINE__, \
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DB_OPT_MMPROFILE_BUFFER | DB_OPT_DUMP_DISPLAY, \
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m4u_name, "[M4U] error"string, ##args); \
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pr_err("[M4U] error:"string, ##args); \
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} while (0)
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#else
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#define m4u_aee_print(string, args...) do {\
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char m4u_name[150];\
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if (snprintf(m4u_name, 150, "[M4U]"string, ##args) < 0) \
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break; \
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pr_err("[M4U] error:"string, ##args); \
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} while (0)
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#endif
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#define MM_IOMMU_PORT_INIT(name, m4u_id, larb_id, tf_larb, port_id) {\
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name, m4u_id, larb_id, port_id, (((tf_larb)<<7)|((port_id)<<2)), 1\
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}
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#define MM_IOMMU_FAKE_PORT_INIT( \
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name, m4u_id, larb_id, tf_larb, port_id, port_type) { \
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name, m4u_id, larb_id, port_id, (((tf_larb)<<7)|((port_id)<<2)), 1, \
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port_type \
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}
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#define APU_IOMMU_PORT_INIT(name, m4u_id, larb_id, port_id, tf_id) {\
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name, m4u_id, larb_id, port_id, tf_id\
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}
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#define PERI_IOMMU_PORT_INIT(name, m4u_id, larb_id, port_id, tf_id) {\
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name, m4u_id, larb_id, port_id, tf_id\
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}
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#define MAU_CONFIG_INIT(iommu_type, iommu_id, slave, mau, start, end,\
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port_mask, larb_mask, wr, virt, io, start_bit32, end_bit32) {\
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iommu_type, iommu_id, slave, mau, start, end, port_mask, larb_mask,\
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wr, virt, io, start_bit32, end_bit32\
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}
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#define mmu_translation_log_format \
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"CRDISPATCH_KEY:M4U_%s\ntranslation fault:port=%s,mva=0x%llx,pa=0x%llx\n"
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#define mau_assert_log_format \
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"CRDISPATCH_KEY:IOMMU\nMAU ASRT:ASRT_ID=0x%x,FALUT_ID=0x%x(%s),ADDR=0x%x(0x%x)\n"
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struct mtk_iommu_port {
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char *name;
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unsigned m4u_id: 2;
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unsigned larb_id: 6;
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unsigned port_id: 8;
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unsigned tf_id: 14; /* 14 bits */
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bool enable_tf;
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unsigned int port_type;
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};
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struct mtk_iommu_cb {
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int port;
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mtk_iommu_fault_callback_t fault_fn;
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void *fault_data;
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};
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struct mtk_m4u_data {
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struct device *dev;
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struct proc_dir_entry *debug_root;
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struct mtk_iommu_cb *m4u_cb;
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const struct mtk_m4u_plat_data *plat_data;
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};
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struct mtk_m4u_plat_data {
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struct peri_iommu_data *peri_data;
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const struct mtk_iommu_port *port_list[TYPE_NUM];
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u32 port_nr[TYPE_NUM];
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const struct mau_config_info *mau_config;
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u32 mau_config_nr;
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u32 mm_tf_ccu_support;
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int (*mm_tf_is_gce_videoup)(u32 port_tf, u32 vld_tf);
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char *(*peri_tf_analyse)(enum peri_iommu bus_id, u32 id);
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};
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struct peri_iommu_data {
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enum peri_iommu id;
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u32 bus_id;
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};
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static struct peri_iommu_data mt6983_peri_iommu_data[PERI_IOMMU_NUM] = {
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[PERI_IOMMU_M4] = {
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.id = PERI_IOMMU_M4,
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.bus_id = 4,
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},
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[PERI_IOMMU_M6] = {
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.id = PERI_IOMMU_M6,
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.bus_id = 6,
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},
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[PERI_IOMMU_M7] = {
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.id = PERI_IOMMU_M7,
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.bus_id = 7,
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},
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};
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static const struct mtk_iommu_port iommu_port_mt6779[] = {
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/* larb0 -MMSYS-9 */
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MM_IOMMU_PORT_INIT("DISP_POSTMASK0", 0, 0, 0, 0),
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MM_IOMMU_PORT_INIT("DISP_OVL0_HDR", 0, 0, 0, 1),
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MM_IOMMU_PORT_INIT("DISP_OVL1_HDR", 0, 0, 0, 2),
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MM_IOMMU_PORT_INIT("DISP_OVL0", 0, 0, 0, 3),
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MM_IOMMU_PORT_INIT("DISP_OVL1", 0, 0, 0, 4),
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MM_IOMMU_PORT_INIT("DISP_PVRIC0", 0, 0, 0, 5),
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MM_IOMMU_PORT_INIT("DISP_RDMA0", 0, 0, 0, 6),
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MM_IOMMU_PORT_INIT("DISP_WDMA0", 0, 0, 0, 7),
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MM_IOMMU_PORT_INIT("DISP_FAKE0", 0, 0, 0, 8),
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/*larb1-MMSYS-14*/
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MM_IOMMU_PORT_INIT("DISP_OVL0_2L_HDR", 0, 1, 4, 0),
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MM_IOMMU_PORT_INIT("DISP_OVL1_2L_HDR", 0, 1, 4, 1),
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MM_IOMMU_PORT_INIT("DISP_OVL0_2L", 0, 1, 4, 2),
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MM_IOMMU_PORT_INIT("DISP_OVL1_2L", 0, 1, 4, 3),
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MM_IOMMU_PORT_INIT("DISP_RDMA1", 0, 1, 4, 4),
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MM_IOMMU_PORT_INIT("MDP_PVRIC0", 0, 1, 4, 5),
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MM_IOMMU_PORT_INIT("MDP_PVRIC1", 0, 1, 4, 6),
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MM_IOMMU_PORT_INIT("MDP_RDMA0", 0, 1, 4, 7),
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MM_IOMMU_PORT_INIT("MDP_RDMA1", 0, 1, 4, 8),
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MM_IOMMU_PORT_INIT("MDP_WROT0_R", 0, 1, 4, 9),
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MM_IOMMU_PORT_INIT("MDP_WROT0_W", 0, 1, 4, 10),
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MM_IOMMU_PORT_INIT("MDP_WROT1_R", 0, 1, 4, 11),
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MM_IOMMU_PORT_INIT("MDP_WROT1_W", 0, 1, 4, 12),
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MM_IOMMU_PORT_INIT("DISP_FAKE1", 0, 1, 4, 13),
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/*larb2-VDEC-12*/
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MM_IOMMU_PORT_INIT("VDEC_MC_EXT", 0, 2, 8, 0),
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MM_IOMMU_PORT_INIT("VDEC_UFO_EXT", 0, 2, 8, 1),
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MM_IOMMU_PORT_INIT("VDEC_PP_EXT", 0, 2, 8, 2),
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MM_IOMMU_PORT_INIT("VDEC_PRED_RD_EXT", 0, 2, 8, 3),
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MM_IOMMU_PORT_INIT("VDEC_PRED_WR_EXT", 0, 2, 8, 4),
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MM_IOMMU_PORT_INIT("VDEC_PPWRAP_EXT", 0, 2, 8, 5),
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MM_IOMMU_PORT_INIT("VDEC_TILE_EXT", 0, 2, 8, 6),
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MM_IOMMU_PORT_INIT("VDEC_VLD_EXT", 0, 2, 8, 7),
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MM_IOMMU_PORT_INIT("VDEC_VLD2_EXT", 0, 2, 8, 8),
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MM_IOMMU_PORT_INIT("VDEC_AVC_MV_EXT", 0, 2, 8, 9),
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MM_IOMMU_PORT_INIT("VDEC_UFO_ENC_EXT", 0, 2, 8, 10),
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MM_IOMMU_PORT_INIT("VDEC_RG_CTRL_DMA_EXT", 0, 2, 8, 11),
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/*larb3-VENC-19*/
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MM_IOMMU_PORT_INIT("VENC_RCPU", 0, 3, 12, 0),
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MM_IOMMU_PORT_INIT("VENC_REC", 0, 3, 12, 1),
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MM_IOMMU_PORT_INIT("VENC_BSDMA", 0, 3, 12, 2),
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MM_IOMMU_PORT_INIT("VENC_SV_COMV", 0, 3, 12, 3),
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MM_IOMMU_PORT_INIT("VENC_RD_COMV", 0, 3, 12, 4),
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MM_IOMMU_PORT_INIT("VENC_NBM_RDMA", 0, 3, 12, 5),
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MM_IOMMU_PORT_INIT("VENC_NBM_RDMA_LITE", 0, 3, 12, 6),
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MM_IOMMU_PORT_INIT("JPGENC_Y_RDMA", 0, 3, 12, 7),
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MM_IOMMU_PORT_INIT("JPGENC_C_RDMA", 0, 3, 12, 8),
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MM_IOMMU_PORT_INIT("JPGENC_Q_TABLE", 0, 3, 12, 9),
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MM_IOMMU_PORT_INIT("JPGENC_BSDMA", 0, 3, 12, 10),
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MM_IOMMU_PORT_INIT("JPGEDC_WDMA", 0, 3, 12, 11),
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MM_IOMMU_PORT_INIT("JPGEDC_BSDMA", 0, 3, 12, 12),
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MM_IOMMU_PORT_INIT("VENC_NBM_WDMA", 0, 3, 12, 13),
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MM_IOMMU_PORT_INIT("VENC_NBM_WDMA_LITE", 0, 3, 12, 14),
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MM_IOMMU_PORT_INIT("VENC_CUR_LUMA", 0, 3, 12, 15),
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MM_IOMMU_PORT_INIT("VENC_CUR_CHROMA", 0, 3, 12, 16),
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MM_IOMMU_PORT_INIT("VENC_REF_LUMA", 0, 3, 12, 17),
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MM_IOMMU_PORT_INIT("VENC_REF_CHROMA", 0, 3, 12, 18),
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/*larb4-dummy*/
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/*larb5-IMG-26*/
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MM_IOMMU_PORT_INIT("IMGI_D1", 0, 5, 16, 0),
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MM_IOMMU_PORT_INIT("IMGBI_D1", 0, 5, 16, 1),
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MM_IOMMU_PORT_INIT("DMGI_D1", 0, 5, 16, 2),
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MM_IOMMU_PORT_INIT("DEPI_D1", 0, 5, 16, 3),
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MM_IOMMU_PORT_INIT("LCEI_D1", 0, 5, 16, 4),
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MM_IOMMU_PORT_INIT("SMTI_D1", 0, 5, 16, 5),
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MM_IOMMU_PORT_INIT("SMTO_D2", 0, 5, 16, 6),
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MM_IOMMU_PORT_INIT("SMTO_D1", 0, 5, 16, 7),
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MM_IOMMU_PORT_INIT("CRZO_D1", 0, 5, 16, 8),
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MM_IOMMU_PORT_INIT("IMG3O_D1", 0, 5, 16, 9),
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MM_IOMMU_PORT_INIT("VIPI_D1", 0, 5, 16, 10),
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MM_IOMMU_PORT_INIT("WPE_A_RDMA1", 0, 5, 16, 11),
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MM_IOMMU_PORT_INIT("WPE_A_RDMA0", 0, 5, 16, 12),
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MM_IOMMU_PORT_INIT("WPE_A_WDMA", 0, 5, 16, 13),
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MM_IOMMU_PORT_INIT("TIMGO_D1", 0, 5, 16, 14),
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MM_IOMMU_PORT_INIT("MFB_RDMA0", 0, 5, 16, 15),
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MM_IOMMU_PORT_INIT("MFB_RDMA1", 0, 5, 16, 16),
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MM_IOMMU_PORT_INIT("MFB_RDMA2", 0, 5, 16, 17),
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MM_IOMMU_PORT_INIT("MFB_RDMA3", 0, 5, 16, 18),
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MM_IOMMU_PORT_INIT("MFB_WDMA", 0, 5, 16, 19),
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MM_IOMMU_PORT_INIT("RESERVED1", 0, 5, 16, 20),
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MM_IOMMU_PORT_INIT("RESERVED2", 0, 5, 16, 21),
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MM_IOMMU_PORT_INIT("RESERVED3", 0, 5, 16, 22),
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MM_IOMMU_PORT_INIT("RESERVED4", 0, 5, 16, 23),
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MM_IOMMU_PORT_INIT("RESERVED5", 0, 5, 16, 24),
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MM_IOMMU_PORT_INIT("RESERVED6", 0, 5, 16, 25),
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/*larb7-IPESYS-4*/
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MM_IOMMU_PORT_INIT("DVS_RDMA", 0, 7, 20, 0),
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MM_IOMMU_PORT_INIT("DVS_WDMA", 0, 7, 20, 1),
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MM_IOMMU_PORT_INIT("DVP_RDMA,", 0, 7, 20, 2),
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MM_IOMMU_PORT_INIT("DVP_WDMA,", 0, 7, 20, 3),
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/*larb8-IPESYS-10*/
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MM_IOMMU_PORT_INIT("FDVT_RDA", 0, 8, 21, 0),
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MM_IOMMU_PORT_INIT("FDVT_RDB", 0, 8, 21, 1),
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MM_IOMMU_PORT_INIT("FDVT_WRA", 0, 8, 21, 2),
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MM_IOMMU_PORT_INIT("FDVT_WRB", 0, 8, 21, 3),
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MM_IOMMU_PORT_INIT("FE_RD0", 0, 8, 21, 4),
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MM_IOMMU_PORT_INIT("FE_RD1", 0, 8, 21, 5),
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MM_IOMMU_PORT_INIT("FE_WR0", 0, 8, 21, 6),
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MM_IOMMU_PORT_INIT("FE_WR1", 0, 8, 21, 7),
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MM_IOMMU_PORT_INIT("RSC_RDMA0", 0, 8, 21, 8),
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MM_IOMMU_PORT_INIT("RSC_WDMA", 0, 8, 21, 9),
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/*larb9-CAM-24*/
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MM_IOMMU_PORT_INIT("CAM_IMGO_R1_C", 0, 9, 28, 0),
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MM_IOMMU_PORT_INIT("CAM_RRZO_R1_C", 0, 9, 28, 1),
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MM_IOMMU_PORT_INIT("CAM_LSCI_R1_C", 0, 9, 28, 2),
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MM_IOMMU_PORT_INIT("CAM_BPCI_R1_C", 0, 9, 28, 3),
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MM_IOMMU_PORT_INIT("CAM_YUVO_R1_C", 0, 9, 28, 4),
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MM_IOMMU_PORT_INIT("CAM_UFDI_R2_C", 0, 9, 28, 5),
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MM_IOMMU_PORT_INIT("CAM_RAWI_R2_C", 0, 9, 28, 6),
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MM_IOMMU_PORT_INIT("CAM_RAWI_R5_C", 0, 9, 28, 7),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_1", 0, 9, 28, 8),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_2", 0, 9, 28, 9),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_3", 0, 9, 28, 10),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_4", 0, 9, 28, 11),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_5", 0, 9, 28, 12),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_6", 0, 9, 28, 13),
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MM_IOMMU_PORT_INIT("CAM_AAO_R1_C", 0, 9, 28, 14),
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MM_IOMMU_PORT_INIT("CAM_AFO_R1_C", 0, 9, 28, 15),
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MM_IOMMU_PORT_INIT("CAM_FLKO_R1_C", 0, 9, 28, 16),
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MM_IOMMU_PORT_INIT("CAM_LCESO_R1_C", 0, 9, 28, 17),
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MM_IOMMU_PORT_INIT("CAM_CRZO_R1_C", 0, 9, 28, 18),
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MM_IOMMU_PORT_INIT("CAM_LTMSO_R1_C", 0, 9, 28, 19),
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MM_IOMMU_PORT_INIT("CAM_RSSO_R1_C", 0, 9, 28, 20),
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MM_IOMMU_PORT_INIT("CAM_CCUI", 0, 9, 28, 21),
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MM_IOMMU_PORT_INIT("CAM_CCUO", 0, 9, 28, 22),
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MM_IOMMU_PORT_INIT("CAM_FAKE", 0, 9, 28, 23),
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/*larb10-CAM-31*/
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MM_IOMMU_PORT_INIT("CAM_IMGO_R1_A", 0, 10, 25, 0),
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MM_IOMMU_PORT_INIT("CAM_RRZO_R1_A", 0, 10, 25, 1),
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MM_IOMMU_PORT_INIT("CAM_LSCI_R1_A", 0, 10, 25, 2),
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MM_IOMMU_PORT_INIT("CAM_BPCI_R1_A", 0, 10, 25, 3),
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MM_IOMMU_PORT_INIT("CAM_YUVO_R1_A", 0, 10, 25, 4),
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MM_IOMMU_PORT_INIT("CAM_UFDI_R2_A", 0, 10, 25, 5),
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MM_IOMMU_PORT_INIT("CAM_RAWI_R5_A", 0, 10, 25, 7),
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MM_IOMMU_PORT_INIT("CAM_IMGO_R1_B", 0, 10, 25, 8),
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MM_IOMMU_PORT_INIT("CAM_RRZO_R1_B", 0, 10, 25, 9),
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MM_IOMMU_PORT_INIT("CAM_LSCI_R1_B", 0, 10, 25, 10),
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MM_IOMMU_PORT_INIT("CAM_BPCI_R1_B", 0, 10, 25, 11),
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MM_IOMMU_PORT_INIT("CAM_YUVO_R1_B,", 0, 10, 25, 12),
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MM_IOMMU_PORT_INIT("CAM_UFDI_R2_B", 0, 10, 25, 13),
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MM_IOMMU_PORT_INIT("CAM_RAWI_R2_B", 0, 10, 25, 14),
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MM_IOMMU_PORT_INIT("CAM_RAWI_R5_B", 0, 10, 25, 15),
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MM_IOMMU_PORT_INIT("CAM_CAMSV_0", 0, 10, 25, 16),
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MM_IOMMU_PORT_INIT("CAM_AAO_R1_A", 0, 10, 25, 17),
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MM_IOMMU_PORT_INIT("CAM_AFO_R1_A", 0, 10, 25, 18),
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MM_IOMMU_PORT_INIT("CAM_FLKO_R1_A", 0, 10, 25, 19),
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MM_IOMMU_PORT_INIT("CAM_LCESO_R1_A", 0, 10, 25, 20),
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MM_IOMMU_PORT_INIT("CAM_CRZO_R1_A", 0, 10, 25, 21),
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MM_IOMMU_PORT_INIT("CAM_AAO_R1_B", 0, 10, 25, 22),
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MM_IOMMU_PORT_INIT("CAM_AFO_R1_B", 0, 10, 25, 23),
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MM_IOMMU_PORT_INIT("CAM_FLKO_R1_B", 0, 10, 25, 24),
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MM_IOMMU_PORT_INIT("CAM_LCESO_R1_B", 0, 10, 25, 25),
|
|
MM_IOMMU_PORT_INIT("CAM_CRZO_R1_B", 0, 10, 25, 26),
|
|
MM_IOMMU_PORT_INIT("CAM_LTMSO_R1_A", 0, 10, 25, 27),
|
|
MM_IOMMU_PORT_INIT("CAM_RSSO_R1_A", 0, 10, 25, 28),
|
|
MM_IOMMU_PORT_INIT("CAM_LTMSO_R1_B", 0, 10, 25, 29),
|
|
MM_IOMMU_PORT_INIT("CAM_RSSO_R1_B", 0, 10, 25, 30),
|
|
/* CCU */
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU0", 0, 9, 24, 0, CCU_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU1", 0, 9, 24, 1, CCU_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6789[] = {
|
|
/* Larb0 -- 4 */
|
|
MM_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_FAKE0", 0, 0, 0x0, 3),
|
|
/* Larb1 -- 5(4) */
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0, 1, 0x4, 0),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0, 1, 0x4, 1),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_RDMA0", 0, 1, 0x4, 2),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_WDMA0", 0, 1, 0x4, 3),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0, 1, 0x4, 4),
|
|
/* Larb2 --5(9) */
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA0", 0, 2, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA1", 0, 2, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT0", 0, 2, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT1", 0, 2, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_DISP_FAKE0", 0, 2, 0x10, 4),
|
|
/* Larb4 -- 14(30) */
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", 0, 4, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", 0, 4, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", 0, 4, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", 0, 4, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", 0, 4, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", 0, 4, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", 0, 4, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", 0, 4, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", 0, 4, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", 0, 4, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_ENC_EXT", 0, 4, 0x8, 10),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT", 0, 4, 0x8, 11),
|
|
MM_IOMMU_PORT_INIT("L4_MINI_MDP_R0_EXT", 0, 4, 0x8, 12),
|
|
MM_IOMMU_PORT_INIT("L4_MINI_MDP_W0_EXT", 0, 4, 0x8, 13),
|
|
/* Larb7 --13(53) */
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RCPU", 0, 7, 0xc, 0),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REC", 0, 7, 0xc, 1),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_BSDMA", 0, 7, 0xc, 2),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SV_COMV", 0, 7, 0xc, 3),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RD_COMV", 0, 7, 0xc, 4),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA", 0, 7, 0xc, 5),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA", 0, 7, 0xc, 6),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_LUMA", 0, 7, 0xc, 7),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA", 0, 7, 0xc, 8),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA", 0, 7, 0xc, 9),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA", 0, 7, 0xc, 10),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE", 0, 7, 0xc, 11),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA", 0, 7, 0xc, 12),
|
|
/*Larb9 -- 29(82) */
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGI_D1", 0, 9, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1", 0, 9, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DMGI_D1", 0, 9, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DEPI_D1", 0, 9, 0x14, 3),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_ICE_D1", 0, 9, 0x14, 4),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D1", 0, 9, 0x14, 5),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D2", 0, 9, 0x14, 6),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D1", 0, 9, 0x14, 7),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_CRZO_D1", 0, 9, 0x14, 8),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1", 0, 9, 0x14, 9),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_VIPI_D1", 0, 9, 0x14, 10),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D5", 0, 9, 0x14, 11),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1", 0, 9, 0x14, 12),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_W0", 0, 9, 0x14, 13),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_R0", 0, 9, 0x14, 14),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1", 0, 9, 0x14, 15),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0", 0, 9, 0x14, 16),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA", 0, 9, 0x14, 17),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0", 0, 9, 0x14, 18),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1", 0, 9, 0x14, 19),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2", 0, 9, 0x14, 20),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3", 0, 9, 0x14, 21),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4", 0, 9, 0x14, 22),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5", 0, 9, 0x14, 23),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0", 0, 9, 0x14, 24),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1", 0, 9, 0x14, 25),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE6", 0, 9, 0x14, 26),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE7", 0, 9, 0x14, 27),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE8", 0, 9, 0x14, 28),
|
|
/*Larb13 -- 12(123) */
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWI", 0, 13, 0x1d, 0),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO0", 0, 13, 0x1d, 1),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO1", 0, 13, 0x1d, 2),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE1", 0, 13, 0x1d, 3),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE2", 0, 13, 0x1d, 4),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE3", 0, 13, 0x1d, 5),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV4", 0, 13, 0x1d, 6),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV5", 0, 13, 0x1d, 7),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV6", 0, 13, 0x1d, 8),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUI", 0, 13, 0x1d, 9),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUO", 0, 13, 0x1d, 10),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_FAKE", 0, 13, 0x1d, 11),
|
|
/*Larb14 -- 6(129) */
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE1", 0, 14, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE2", 0, 14, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE3", 0, 14, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE4", 0, 14, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUI", 0, 14, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUO", 0, 14, 0x19, 5),
|
|
/*Larb16 -- 17(146) */
|
|
MM_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A", 0, 16, 0x1a, 0),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A", 0, 16, 0x1a, 1),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A", 0, 16, 0x1a, 2),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A", 0, 16, 0x1a, 3),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A", 0, 16, 0x1a, 4),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A", 0, 16, 0x1a, 5),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A", 0, 16, 0x1a, 6),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A", 0, 16, 0x1a, 7),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A", 0, 16, 0x1a, 8),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A", 0, 16, 0x1a, 9),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A", 0, 16, 0x1a, 10),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A", 0, 16, 0x1a, 11),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A", 0, 16, 0x1a, 12),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A", 0, 16, 0x1a, 13),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A", 0, 16, 0x1a, 14),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_", 0, 16, 0x1a, 15),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A", 0, 16, 0x1a, 16),
|
|
/*Larb17 -- 17(163) */
|
|
MM_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B", 0, 17, 0x1f, 0),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B", 0, 17, 0x1f, 1),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B", 0, 17, 0x1f, 2),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B", 0, 17, 0x1f, 3),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B", 0, 17, 0x1f, 4),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B", 0, 17, 0x1f, 5),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B", 0, 17, 0x1f, 6),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B", 0, 17, 0x1f, 7),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B", 0, 17, 0x1f, 8),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B", 0, 17, 0x1f, 9),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B", 0, 17, 0x1f, 10),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B", 0, 17, 0x1f, 11),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B", 0, 17, 0x1f, 12),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B", 0, 17, 0x1f, 13),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B", 0, 17, 0x1f, 14),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B", 0, 17, 0x1f, 15),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B", 0, 17, 0x1f, 16),
|
|
/*Larb19 -- 4(184) */
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA", 0, 19, 0x16, 0),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA", 0, 19, 0x16, 1),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA", 0, 19, 0x16, 2),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA", 0, 19, 0x16, 3),
|
|
/*Larb20 -- 6(190) */
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA", 0, 20, 0x17, 0),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB", 0, 20, 0x17, 1),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA", 0, 20, 0x17, 2),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB", 0, 20, 0x17, 3),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0", 0, 20, 0x17, 4),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA", 0, 20, 0x17, 5),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6873[] = {
|
|
/* Larb0 -- 6 */
|
|
MM_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_RDMA0", 0, 0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_WDMA0", 0, 0, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_FAKE0", 0, 0, 0x0, 5),
|
|
/* Larb1 -- 8(14) */
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0, 1, 0x4, 0),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2_HDR", 0, 1, 0x4, 1),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0, 1, 0x4, 2),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2", 0, 1, 0x4, 3),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_MDP_RDMA4", 0, 1, 0x4, 4),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_RDMA4", 0, 1, 0x4, 5),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_UFBC_WDMA0", 0, 1, 0x4, 6),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0, 1, 0x4, 7),
|
|
/* Larb2 --5(19) */
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA0", 0, 2, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA1", 0, 2, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT0", 0, 2, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT1", 0, 2, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_FAKE0", 0, 2, 0x10, 4),
|
|
/* Larb4 -- 11(30) */
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", 0, 4, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", 0, 4, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", 0, 4, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", 0, 4, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", 0, 4, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", 0, 4, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", 0, 4, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", 0, 4, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", 0, 4, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", 0, 4, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT", 0, 4, 0x8, 10),
|
|
/* Larb5 -- 8(38) */
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD_EXT", 0, 5, 0x9, 0),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD2_EXT", 0, 5, 0x9, 1),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_AVC_MV_EXT", 0, 5, 0x9, 2),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_PRED_RD_EXT", 0, 5, 0x9, 3),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_TILE_EXT", 0, 5, 0x9, 4),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_WDMA_EXT", 0, 5, 0x9, 5),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_RG_CTRL_DMA_EXT", 0, 5, 0x9, 6),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_UFO_ENC_EXT", 0, 5, 0x9, 7),
|
|
/* Larb6 --dummy */
|
|
/* Larb7 --15(53) */
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RCPU", 0, 7, 0xc, 0),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REC", 0, 7, 0xc, 1),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_BSDMA", 0, 7, 0xc, 2),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SV_COMV", 0, 7, 0xc, 3),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RD_COMV", 0, 7, 0xc, 4),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA", 0, 7, 0xc, 5),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA", 0, 7, 0xc, 6),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_LUMA", 0, 7, 0xc, 7),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA", 0, 7, 0xc, 8),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA", 0, 7, 0xc, 9),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Q_RDMA", 0, 7, 0xc, 10),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_C_TABLE", 0, 7, 0xc, 11),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA", 0, 7, 0xc, 12),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_R_LUMA", 0, 7, 0xc, 13),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_W_LUMA", 0, 7, 0xc, 14),
|
|
/*Larb9 -- 29(82) */
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGI_D1", 0, 9, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1", 0, 9, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DMGI_D1", 0, 9, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DEPI_D1", 0, 9, 0x14, 3),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_ICE_D1", 0, 9, 0x14, 4),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D1", 0, 9, 0x14, 5),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D2", 0, 9, 0x14, 6),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D1", 0, 9, 0x14, 7),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_CRZO_D1", 0, 9, 0x14, 8),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1", 0, 9, 0x14, 9),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_VIPI_D1", 0, 9, 0x14, 10),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D5", 0, 9, 0x14, 11),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1", 0, 9, 0x14, 12),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_W0", 0, 9, 0x14, 13),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_R0", 0, 9, 0x14, 14),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1", 0, 9, 0x14, 15),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0", 0, 9, 0x14, 16),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA", 0, 9, 0x14, 17),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0", 0, 9, 0x14, 18),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1", 0, 9, 0x14, 19),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2", 0, 9, 0x14, 20),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3", 0, 9, 0x14, 21),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4", 0, 9, 0x14, 22),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5", 0, 9, 0x14, 23),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0", 0, 9, 0x14, 24),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1", 0, 9, 0x14, 25),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE6", 0, 9, 0x14, 26),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE7", 0, 9, 0x14, 27),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE8", 0, 9, 0x14, 28),
|
|
/*Larb11 -- 29(111) */
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGI_D1", 0, 11, 0x15, 0),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1", 0, 11, 0x15, 1),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DMGI_D1", 0, 11, 0x15, 2),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DEPI_D1", 0, 11, 0x15, 3),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_ICE_D1", 0, 11, 0x15, 4),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D1", 0, 11, 0x15, 5),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D2", 0, 11, 0x15, 6),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D1", 0, 11, 0x15, 7),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_CRZO_D1", 0, 11, 0x15, 8),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1", 0, 11, 0x15, 9),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_VIPI_D1", 0, 11, 0x15, 10),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D5", 0, 11, 0x15, 11),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1", 0, 11, 0x15, 12),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_W0", 0, 11, 0x15, 13),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_R0", 0, 11, 0x15, 14),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1", 0, 11, 0x15, 15),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0", 0, 11, 0x15, 16),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA", 0, 11, 0x15, 17),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0", 0, 11, 0x15, 18),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1", 0, 11, 0x15, 19),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2", 0, 11, 0x15, 20),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3", 0, 11, 0x15, 21),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4", 0, 11, 0x15, 22),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5", 0, 11, 0x15, 23),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0", 0, 11, 0x15, 24),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1", 0, 11, 0x15, 25),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE6", 0, 11, 0x15, 26),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE7", 0, 11, 0x15, 27),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE8", 0, 11, 0x15, 28),
|
|
/*Larb13 -- 12(123) */
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWI", 0, 13, 0x1d, 0),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO0", 0, 13, 0x1d, 1),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO1", 0, 13, 0x1d, 2),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV1", 0, 13, 0x1d, 3),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV2", 0, 13, 0x1d, 4),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV3", 0, 13, 0x1d, 5),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV4", 0, 13, 0x1d, 6),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV5", 0, 13, 0x1d, 7),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV6", 0, 13, 0x1d, 8),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUI", 0, 13, 0x1d, 9),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUO", 0, 13, 0x1d, 10),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_FAKE", 0, 13, 0x1d, 11),
|
|
/*Larb14 -- 6(129) */
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE1", 0, 14, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE2", 0, 14, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE3", 0, 14, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CAMSV0", 0, 14, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUI", 0, 14, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUO", 0, 14, 0x19, 5),
|
|
/*Larb16 -- 17(146) */
|
|
MM_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A", 0, 16, 0x1a, 0),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A", 0, 16, 0x1a, 1),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A", 0, 16, 0x1a, 2),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A", 0, 16, 0x1a, 3),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A", 0, 16, 0x1a, 4),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A", 0, 16, 0x1a, 5),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A", 0, 16, 0x1a, 6),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A", 0, 16, 0x1a, 7),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A", 0, 16, 0x1a, 8),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A", 0, 16, 0x1a, 9),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A", 0, 16, 0x1a, 10),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A", 0, 16, 0x1a, 11),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A", 0, 16, 0x1a, 12),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A", 0, 16, 0x1a, 13),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A", 0, 16, 0x1a, 14),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_", 0, 16, 0x1a, 15),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A", 0, 16, 0x1a, 16),
|
|
/*Larb17 -- 17(163) */
|
|
MM_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B", 0, 17, 0x1f, 0),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B", 0, 17, 0x1f, 1),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B", 0, 17, 0x1f, 2),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B", 0, 17, 0x1f, 3),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B", 0, 17, 0x1f, 4),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B", 0, 17, 0x1f, 5),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B", 0, 17, 0x1f, 6),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B", 0, 17, 0x1f, 7),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B", 0, 17, 0x1f, 8),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B", 0, 17, 0x1f, 9),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B", 0, 17, 0x1f, 10),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B", 0, 17, 0x1f, 11),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B", 0, 17, 0x1f, 12),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B", 0, 17, 0x1f, 13),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B", 0, 17, 0x1f, 14),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B", 0, 17, 0x1f, 15),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B", 0, 17, 0x1f, 16),
|
|
/*Larb18 -- 17(180) */
|
|
MM_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C", 0, 18, 0x1e, 0),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C", 0, 18, 0x1e, 1),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C", 0, 18, 0x1e, 2),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C", 0, 18, 0x1e, 3),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C", 0, 18, 0x1e, 4),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C", 0, 18, 0x1e, 5),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C", 0, 18, 0x1e, 6),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C", 0, 18, 0x1e, 7),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C", 0, 18, 0x1e, 8),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C", 0, 18, 0x1e, 9),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C", 0, 18, 0x1e, 10),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C", 0, 18, 0x1e, 11),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C", 0, 18, 0x1e, 12),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C", 0, 18, 0x1e, 13),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C", 0, 18, 0x1e, 14),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C", 0, 18, 0x1e, 15),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C", 0, 18, 0x1e, 16),
|
|
/*Larb19 -- 4(184) */
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA", 0, 19, 0x16, 0),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA", 0, 19, 0x16, 1),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA", 0, 19, 0x16, 2),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA", 0, 19, 0x16, 3),
|
|
/*Larb20 -- 6(190) */
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA", 0, 20, 0x17, 0),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB", 0, 20, 0x17, 1),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA", 0, 20, 0x17, 2),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB", 0, 20, 0x17, 3),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0", 0, 20, 0x17, 4),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA", 0, 20, 0x17, 5),
|
|
/*Larb22 -- 1(191) */
|
|
MM_IOMMU_FAKE_PORT_INIT("L22_CCU0", 0, 22, 0x1c, 0, CCU_FAKE),
|
|
/*Larb23 -- 1(192) */
|
|
MM_IOMMU_FAKE_PORT_INIT("L23_CCU1", 0, 23, 0x18, 0, CCU_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6855[] = {
|
|
/* Larb0 */
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT0", DISP_IOMMU, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT1", DISP_IOMMU, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT2", DISP_IOMMU, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT3", DISP_IOMMU, 0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT4", DISP_IOMMU, 0, 0x0, 4),
|
|
|
|
/* Larb1 */
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT0", DISP_IOMMU, 1, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT1", DISP_IOMMU, 1, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT2", DISP_IOMMU, 1, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT3", DISP_IOMMU, 1, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT4", DISP_IOMMU, 1, 0x8, 4),
|
|
|
|
/* larb2 */
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT0", DISP_IOMMU, 2, 0x12, 0),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT1", DISP_IOMMU, 2, 0x12, 1),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT2", DISP_IOMMU, 2, 0x12, 2),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT3", DISP_IOMMU, 2, 0x12, 3),
|
|
|
|
/* larb4 */
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT0", DISP_IOMMU, 4, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT1", DISP_IOMMU, 4, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT2", DISP_IOMMU, 4, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT3", DISP_IOMMU, 4, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT4", DISP_IOMMU, 4, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT5", DISP_IOMMU, 4, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT6", DISP_IOMMU, 4, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT7", DISP_IOMMU, 4, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT8", DISP_IOMMU, 4, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT9", DISP_IOMMU, 4, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT10", DISP_IOMMU, 4, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT11", DISP_IOMMU, 4, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT12", DISP_IOMMU, 4, 0x28, 12),
|
|
|
|
/* larb7 */
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT0", DISP_IOMMU, 7, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT1", DISP_IOMMU, 7, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT2", DISP_IOMMU, 7, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT3", DISP_IOMMU, 7, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT4", DISP_IOMMU, 7, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT5", DISP_IOMMU, 7, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT6", DISP_IOMMU, 7, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT7", DISP_IOMMU, 7, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT8", DISP_IOMMU, 7, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT9", DISP_IOMMU, 7, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT10", DISP_IOMMU, 7, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT11", DISP_IOMMU, 7, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT12", DISP_IOMMU, 7, 0x20, 12),
|
|
|
|
/* larb9 */
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT0", DISP_IOMMU, 9, 0x1a, 0),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT1", DISP_IOMMU, 9, 0x1a, 1),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT2", DISP_IOMMU, 9, 0x1a, 2),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT3", DISP_IOMMU, 9, 0x1a, 3),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT4", DISP_IOMMU, 9, 0x1a, 4),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT5", DISP_IOMMU, 9, 0x1a, 5),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT6", DISP_IOMMU, 9, 0x1a, 6),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT7", DISP_IOMMU, 9, 0x1a, 7),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT8", DISP_IOMMU, 9, 0x1a, 8),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT9", DISP_IOMMU, 9, 0x1a, 9),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT10", DISP_IOMMU, 9, 0x1a, 10),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT11", DISP_IOMMU, 9, 0x1a, 11),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT12", DISP_IOMMU, 9, 0x1a, 12),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT13", DISP_IOMMU, 9, 0x1a, 13),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT14", DISP_IOMMU, 9, 0x1a, 14),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT15", DISP_IOMMU, 9, 0x1a, 15),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT16", DISP_IOMMU, 9, 0x1a, 16),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT17", DISP_IOMMU, 9, 0x1a, 17),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT18", DISP_IOMMU, 9, 0x1a, 18),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT19", DISP_IOMMU, 9, 0x1a, 19),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT20", DISP_IOMMU, 9, 0x1a, 20),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT21", DISP_IOMMU, 9, 0x1a, 21),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT22", DISP_IOMMU, 9, 0x1a, 22),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT23", DISP_IOMMU, 9, 0x1a, 23),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT24", DISP_IOMMU, 9, 0x1a, 24),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT25", DISP_IOMMU, 9, 0x1a, 25),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT26", DISP_IOMMU, 9, 0x1a, 26),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT27", DISP_IOMMU, 9, 0x1a, 27),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT28", DISP_IOMMU, 9, 0x1a, 28),
|
|
|
|
/* Larb11 */
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT0", DISP_IOMMU, 11, 0x1b, 0),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT1", DISP_IOMMU, 11, 0x1b, 1),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT2", DISP_IOMMU, 11, 0x1b, 2),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT3", DISP_IOMMU, 11, 0x1b, 3),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT4", DISP_IOMMU, 11, 0x1b, 4),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT5", DISP_IOMMU, 11, 0x1b, 5),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT6", DISP_IOMMU, 11, 0x1b, 6),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT7", DISP_IOMMU, 11, 0x1b, 7),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT8", DISP_IOMMU, 11, 0x1b, 8),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT9", DISP_IOMMU, 11, 0x1b, 9),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT10", DISP_IOMMU, 11, 0x1b, 10),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT11", DISP_IOMMU, 11, 0x1b, 11),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT12", DISP_IOMMU, 11, 0x1b, 12),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT13", DISP_IOMMU, 11, 0x1b, 13),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT14", DISP_IOMMU, 11, 0x1b, 14),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT15", DISP_IOMMU, 11, 0x1b, 15),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT16", DISP_IOMMU, 11, 0x1b, 16),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT17", DISP_IOMMU, 11, 0x1b, 17),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT18", DISP_IOMMU, 11, 0x1b, 18),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT19", DISP_IOMMU, 11, 0x1b, 19),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT20", DISP_IOMMU, 11, 0x1b, 20),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT21", DISP_IOMMU, 11, 0x1b, 21),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT22", DISP_IOMMU, 11, 0x1b, 22),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT23", DISP_IOMMU, 11, 0x1b, 23),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT24", DISP_IOMMU, 11, 0x1b, 24),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT25", DISP_IOMMU, 11, 0x1b, 25),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT26", DISP_IOMMU, 11, 0x1b, 26),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT27", DISP_IOMMU, 11, 0x1b, 27),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT28", DISP_IOMMU, 11, 0x1b, 28),
|
|
|
|
/* larb13 */
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT0", DISP_IOMMU, 13, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT1", DISP_IOMMU, 13, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT2", DISP_IOMMU, 13, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT3", DISP_IOMMU, 13, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT4", DISP_IOMMU, 13, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT5", DISP_IOMMU, 13, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT6", DISP_IOMMU, 13, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT7", DISP_IOMMU, 13, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT8", DISP_IOMMU, 13, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT9", DISP_IOMMU, 13, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT10", DISP_IOMMU, 13, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT11", DISP_IOMMU, 13, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT12", DISP_IOMMU, 13, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT13", DISP_IOMMU, 13, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT14", DISP_IOMMU, 13, 0x30, 14),
|
|
|
|
/* larb14 */
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT0", DISP_IOMMU, 14, 0x38, 0),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT1", DISP_IOMMU, 14, 0x38, 1),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT2", DISP_IOMMU, 14, 0x38, 2),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT3", DISP_IOMMU, 14, 0x38, 3),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT4", DISP_IOMMU, 14, 0x38, 4),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT5", DISP_IOMMU, 14, 0x38, 5),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT6", DISP_IOMMU, 14, 0x38, 6),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT7", DISP_IOMMU, 14, 0x38, 7),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT8", DISP_IOMMU, 14, 0x38, 8),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT9", DISP_IOMMU, 14, 0x38, 9),
|
|
|
|
/* larb16 */
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT0", DISP_IOMMU, 16, 0x39, 0),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT1", DISP_IOMMU, 16, 0x39, 1),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT2", DISP_IOMMU, 16, 0x39, 2),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT3", DISP_IOMMU, 16, 0x39, 3),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT4", DISP_IOMMU, 16, 0x39, 4),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT5", DISP_IOMMU, 16, 0x39, 5),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT6", DISP_IOMMU, 16, 0x39, 6),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT7", DISP_IOMMU, 16, 0x39, 7),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT8", DISP_IOMMU, 16, 0x39, 8),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT9", DISP_IOMMU, 16, 0x39, 9),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT10", DISP_IOMMU, 16, 0x39, 10),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT11", DISP_IOMMU, 16, 0x39, 11),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT12", DISP_IOMMU, 16, 0x39, 12),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT13", DISP_IOMMU, 16, 0x39, 13),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT14", DISP_IOMMU, 16, 0x39, 14),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT15", DISP_IOMMU, 16, 0x39, 15),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT16", DISP_IOMMU, 16, 0x39, 16),
|
|
|
|
/* larb17 */
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT0", DISP_IOMMU, 17, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT1", DISP_IOMMU, 17, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT2", DISP_IOMMU, 17, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT3", DISP_IOMMU, 17, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT4", DISP_IOMMU, 17, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT5", DISP_IOMMU, 17, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT6", DISP_IOMMU, 17, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT7", DISP_IOMMU, 17, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT8", DISP_IOMMU, 17, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT9", DISP_IOMMU, 17, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT10", DISP_IOMMU, 17, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT11", DISP_IOMMU, 17, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT12", DISP_IOMMU, 17, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT13", DISP_IOMMU, 17, 0x31, 13),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT14", DISP_IOMMU, 17, 0x31, 14),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT15", DISP_IOMMU, 17, 0x31, 15),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT16", DISP_IOMMU, 17, 0x31, 16),
|
|
|
|
/* larb20 */
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT0", DISP_IOMMU, 20, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT1", DISP_IOMMU, 20, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT2", DISP_IOMMU, 20, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT3", DISP_IOMMU, 20, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT4", DISP_IOMMU, 20, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT5", DISP_IOMMU, 20, 0x19, 5),
|
|
|
|
/* Larb32 -- 3 */
|
|
MM_IOMMU_FAKE_PORT_INIT("VIDEO_uP", DISP_IOMMU, 32, 0x8, 0,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_D_M", DISP_IOMMU, 32, 0x8, 1,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_M_M", DISP_IOMMU, 32, 0x8, 2,
|
|
GCE_VIDEOUP_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6873[] = {
|
|
/* 8 */
|
|
APU_IOMMU_PORT_INIT("APU_VP6_0", 0, 0, 0, 0x0),
|
|
APU_IOMMU_PORT_INIT("APU_VP6_1", 0, 0, 0, 0x1),
|
|
APU_IOMMU_PORT_INIT("APU_UP", 0, 0, 0, 0x2),
|
|
APU_IOMMU_PORT_INIT("APU_RESERVED", 0, 0, 0, 0x3),
|
|
APU_IOMMU_PORT_INIT("APU_XPU", 0, 0, 0, 0x4),
|
|
APU_IOMMU_PORT_INIT("APU_EDMA", 0, 0, 0, 0x5),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0", 0, 0, 0, 0x6),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1", 0, 0, 0, 0x7),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0xf)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6853[] = {
|
|
/* Larb0 -- 6 */
|
|
MM_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_FAKE0", 0, 0, 0x0, 3),
|
|
/* Larb1 -- 8(14) */
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0, 1, 0x4, 0),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0, 1, 0x4, 1),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_RDMA0", 0, 1, 0x4, 2),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_WDMA0", 0, 1, 0x4, 3),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0, 1, 0x4, 4),
|
|
/* Larb2 --5(19) */
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA0", 0, 2, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA1", 0, 2, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT0", 0, 2, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT1", 0, 2, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_DISP_FAKE0", 0, 2, 0x10, 4),
|
|
/* Larb4 -- 11(30) */
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", 0, 4, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", 0, 4, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", 0, 4, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", 0, 4, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", 0, 4, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", 0, 4, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", 0, 4, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", 0, 4, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", 0, 4, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", 0, 4, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT", 0, 4, 0x8, 10),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_ENC_EXT", 0, 4, 0x8, 11),
|
|
/* Larb7 --15(53) */
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RCPU", 0, 7, 0xc, 0),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REC", 0, 7, 0xc, 1),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_BSDMA", 0, 7, 0xc, 2),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SV_COMV", 0, 7, 0xc, 3),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RD_COMV", 0, 7, 0xc, 4),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA", 0, 7, 0xc, 5),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA", 0, 7, 0xc, 6),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_LUMA", 0, 7, 0xc, 7),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA", 0, 7, 0xc, 8),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA", 0, 7, 0xc, 9),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA", 0, 7, 0xc, 10),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE", 0, 7, 0xc, 11),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA", 0, 7, 0xc, 12),
|
|
/*Larb9 -- 29(82) */
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGI_D1", 0, 9, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1", 0, 9, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DMGI_D1", 0, 9, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DEPI_D1", 0, 9, 0x14, 3),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_ICE_D1", 0, 9, 0x14, 4),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D1", 0, 9, 0x14, 5),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D2", 0, 9, 0x14, 6),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D1", 0, 9, 0x14, 7),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_CRZO_D1", 0, 9, 0x14, 8),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1", 0, 9, 0x14, 9),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_VIPI_D1", 0, 9, 0x14, 10),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D5", 0, 9, 0x14, 11),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1", 0, 9, 0x14, 12),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_W0", 0, 9, 0x14, 13),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_R0", 0, 9, 0x14, 14),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1", 0, 9, 0x14, 15),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0", 0, 9, 0x14, 16),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA", 0, 9, 0x14, 17),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0", 0, 9, 0x14, 18),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1", 0, 9, 0x14, 19),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2", 0, 9, 0x14, 20),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3", 0, 9, 0x14, 21),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4", 0, 9, 0x14, 22),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5", 0, 9, 0x14, 23),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0", 0, 9, 0x14, 24),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1", 0, 9, 0x14, 25),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE6", 0, 9, 0x14, 26),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE7", 0, 9, 0x14, 27),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE8", 0, 9, 0x14, 28),
|
|
/*Larb11 -- 29(111) */
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGI_D1", 0, 11, 0x15, 0),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1", 0, 11, 0x15, 1),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DMGI_D1", 0, 11, 0x15, 2),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DEPI_D1", 0, 11, 0x15, 3),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_ICE_D1", 0, 11, 0x15, 4),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D1", 0, 11, 0x15, 5),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D2", 0, 11, 0x15, 6),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D1", 0, 11, 0x15, 7),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_CRZO_D1", 0, 11, 0x15, 8),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1", 0, 11, 0x15, 9),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_VIPI_D1", 0, 11, 0x15, 10),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D5", 0, 11, 0x15, 11),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1", 0, 11, 0x15, 12),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_W0", 0, 11, 0x15, 13),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_R0", 0, 11, 0x15, 14),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1", 0, 11, 0x15, 15),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0", 0, 11, 0x15, 16),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA", 0, 11, 0x15, 17),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0", 0, 11, 0x15, 18),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1", 0, 11, 0x15, 19),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2", 0, 11, 0x15, 20),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3", 0, 11, 0x15, 21),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4", 0, 11, 0x15, 22),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5", 0, 11, 0x15, 23),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0", 0, 11, 0x15, 24),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1", 0, 11, 0x15, 25),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE6", 0, 11, 0x15, 26),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE7", 0, 11, 0x15, 27),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE8", 0, 11, 0x15, 28),
|
|
/*Larb13 -- 12(123) */
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWI", 0, 13, 0x1d, 0),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO0", 0, 13, 0x1d, 1),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO1", 0, 13, 0x1d, 2),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE1", 0, 13, 0x1d, 3),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE2", 0, 13, 0x1d, 4),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_RESERVE3", 0, 13, 0x1d, 5),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV4", 0, 13, 0x1d, 6),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV5", 0, 13, 0x1d, 7),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV6", 0, 13, 0x1d, 8),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUI", 0, 13, 0x1d, 9),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUO", 0, 13, 0x1d, 10),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_FAKE", 0, 13, 0x1d, 11),
|
|
/*Larb14 -- 6(129) */
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE1", 0, 14, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE2", 0, 14, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE3", 0, 14, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_RESERVE4", 0, 14, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUI", 0, 14, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUO", 0, 14, 0x19, 5),
|
|
/*Larb16 -- 17(146) */
|
|
MM_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A", 0, 16, 0x1a, 0),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A", 0, 16, 0x1a, 1),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A", 0, 16, 0x1a, 2),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A", 0, 16, 0x1a, 3),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A", 0, 16, 0x1a, 4),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A", 0, 16, 0x1a, 5),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A", 0, 16, 0x1a, 6),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A", 0, 16, 0x1a, 7),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A", 0, 16, 0x1a, 8),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A", 0, 16, 0x1a, 9),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A", 0, 16, 0x1a, 10),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A", 0, 16, 0x1a, 11),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A", 0, 16, 0x1a, 12),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A", 0, 16, 0x1a, 13),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A", 0, 16, 0x1a, 14),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_", 0, 16, 0x1a, 15),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A", 0, 16, 0x1a, 16),
|
|
/*Larb17 -- 17(163) */
|
|
MM_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B", 0, 17, 0x1f, 0),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B", 0, 17, 0x1f, 1),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B", 0, 17, 0x1f, 2),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B", 0, 17, 0x1f, 3),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B", 0, 17, 0x1f, 4),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B", 0, 17, 0x1f, 5),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B", 0, 17, 0x1f, 6),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B", 0, 17, 0x1f, 7),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B", 0, 17, 0x1f, 8),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B", 0, 17, 0x1f, 9),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B", 0, 17, 0x1f, 10),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B", 0, 17, 0x1f, 11),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B", 0, 17, 0x1f, 12),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B", 0, 17, 0x1f, 13),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B", 0, 17, 0x1f, 14),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B", 0, 17, 0x1f, 15),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B", 0, 17, 0x1f, 16),
|
|
/*Larb18 -- 17(180) */
|
|
MM_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C", 0, 18, 0x1e, 0),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C", 0, 18, 0x1e, 1),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C", 0, 18, 0x1e, 2),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C", 0, 18, 0x1e, 3),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C", 0, 18, 0x1e, 4),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C", 0, 18, 0x1e, 5),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C", 0, 18, 0x1e, 6),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C", 0, 18, 0x1e, 7),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C", 0, 18, 0x1e, 8),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C", 0, 18, 0x1e, 9),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C", 0, 18, 0x1e, 10),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C", 0, 18, 0x1e, 11),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C", 0, 18, 0x1e, 12),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C", 0, 18, 0x1e, 13),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C", 0, 18, 0x1e, 14),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C", 0, 18, 0x1e, 15),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C", 0, 18, 0x1e, 16),
|
|
/*Larb19 -- 4(184) */
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA", 0, 19, 0x16, 0),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA", 0, 19, 0x16, 1),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA", 0, 19, 0x16, 2),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA", 0, 19, 0x16, 3),
|
|
/*Larb20 -- 6(190) */
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA", 0, 20, 0x17, 0),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB", 0, 20, 0x17, 1),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA", 0, 20, 0x17, 2),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB", 0, 20, 0x17, 3),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0", 0, 20, 0x17, 4),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA", 0, 20, 0x17, 5),
|
|
/*Larb22 -- 1(191) */
|
|
MM_IOMMU_FAKE_PORT_INIT("L22_CCU0", 0, 22, 0x1c, 0, CCU_FAKE),
|
|
/*Larb23 -- 1(192) */
|
|
MM_IOMMU_FAKE_PORT_INIT("L23_CCU1", 0, 23, 0x18, 0, CCU_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6853[] = {
|
|
/* 8 */
|
|
APU_IOMMU_PORT_INIT("APU_VP6_0", 0, 0, 0, 0x0),
|
|
APU_IOMMU_PORT_INIT("APU_VP6_1", 0, 0, 0, 0x1),
|
|
APU_IOMMU_PORT_INIT("APU_UP", 0, 0, 0, 0x2),
|
|
APU_IOMMU_PORT_INIT("APU_XPU", 0, 0, 0, 0x3),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0xf)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6893[] = {
|
|
/*Larb0 */
|
|
MM_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0,
|
|
0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L0_MDP_RDMA4", 0,
|
|
0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0,
|
|
0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA1_HDR", 0,
|
|
0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA3_HDR", 0,
|
|
0, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0,
|
|
0, 0x0, 5),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA1", 0,
|
|
0, 0x0, 6),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA3", 0,
|
|
0, 0x0, 7),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_RDMA1_SYSRAM", 0,
|
|
0, 0x0, 8),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA0_SYSRAM ", 0,
|
|
0, 0x0, 9),
|
|
MM_IOMMU_PORT_INIT("L0_OVL_2L_RDMA2_SYSRAM", 0,
|
|
0, 0x0, 10),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_WDMA0", 0,
|
|
0, 0x0, 11),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_RDMA0", 0,
|
|
0, 0x0, 12),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_UFBC_WDMA0", 0,
|
|
0, 0x0, 13),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_FAKE0 ", 0,
|
|
0, 0x0, 14),
|
|
/*Larb1 */
|
|
MM_IOMMU_PORT_INIT("L1_DISP_POSTMASK1", 0,
|
|
1, 0x4, 0),
|
|
MM_IOMMU_PORT_INIT("L1_MDP_RDMA5", 0,
|
|
1, 0x4, 1),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_RDMA1_HDR", 0,
|
|
1, 0x4, 2),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0,
|
|
1, 0x4, 3),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2_HDR", 0,
|
|
1, 0x4, 4),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_RDMA1", 0,
|
|
1, 0x4, 5),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0,
|
|
1, 0x4, 6),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2", 0,
|
|
1, 0x4, 7),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_RDMA0_SYSRAM", 0,
|
|
1, 0x4, 8),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA1_SYSRAM", 0,
|
|
1, 0x4, 9),
|
|
MM_IOMMU_PORT_INIT("L1_OVL_2L_RDMA3_SYSRAM", 0,
|
|
1, 0x4, 10),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_WDMA1", 0,
|
|
1, 0x4, 11),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_RDMA1", 0,
|
|
1, 0x4, 12),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_UFBC_WDMA1", 0,
|
|
1, 0x4, 13),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0,
|
|
1, 0x4, 14),
|
|
/*Larb2 */
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA0", 1,
|
|
2, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA2", 1,
|
|
2, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT0", 1,
|
|
2, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT2", 1,
|
|
2, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_FILMGRAIN0", 1,
|
|
2, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_FAKE0", 1,
|
|
2, 0x0, 5),
|
|
/*Larb3 */
|
|
MM_IOMMU_PORT_INIT("L3_MDP_RDMA1", 1,
|
|
3, 0x4, 0),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_RDMA3", 1,
|
|
3, 0x4, 1),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WROT1", 1,
|
|
3, 0x4, 2),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WROT3", 1,
|
|
3, 0x4, 3),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_FILMGRAIN1", 1,
|
|
3, 0x4, 4),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_FAKE1", 1,
|
|
3, 0x4, 5),
|
|
/*Larb4 */
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_MC_EXT_MDP", 1,
|
|
4, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT_MDP", 1,
|
|
4, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PP_EXT_MDP", 1,
|
|
4, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT_MDP", 1,
|
|
4, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT_MDP", 1,
|
|
4, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT_MDP", 1,
|
|
4, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT_MDP", 1,
|
|
4, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT_MDP", 1,
|
|
4, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT_MDP", 1,
|
|
4, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT_MDP", 1,
|
|
4, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT_MDP", 1,
|
|
4, 0x8, 10),
|
|
/*Larb5 */
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD_EXT_DISP", 0,
|
|
5, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD2_EXT_DISP", 0,
|
|
5, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_AVC_MV_EXT_DISP", 0,
|
|
5, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_PRED_RD_EXT_DISP", 0,
|
|
5, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_TILE_EXT_DISP", 0,
|
|
5, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_WDMA_EXT_DISP", 0,
|
|
5, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP", 0,
|
|
5, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_UFO_ENC_EXT_DISP", 0,
|
|
5, 0x8, 7),
|
|
/*Larb7 */
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RCPU_DISP", 0,
|
|
7, 0xc, 0),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REC_DISP", 0,
|
|
7, 0xc, 1),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_BSDMA_DISP", 0,
|
|
7, 0xc, 2),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SV_COMV_DISP", 0,
|
|
7, 0xc, 3),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RD_COMV_DISP", 0,
|
|
7, 0xc, 4),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_DISP", 0,
|
|
7, 0xc, 5),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_LITE_DISP", 0,
|
|
7, 0xc, 6),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA_DISP", 0,
|
|
7, 0xc, 7),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA_DISP", 0,
|
|
7, 0xc, 8),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE_DISP", 0,
|
|
7, 0xc, 9),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA_DISP", 0,
|
|
7, 0xc, 10),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_WDMA0_DISP", 0,
|
|
7, 0xc, 11),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA0_DISP", 0,
|
|
7, 0xc, 12),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_DISP", 0,
|
|
7, 0xc, 13),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_LITE_DISP", 0,
|
|
7, 0xc, 14),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA_DISP", 0,
|
|
7, 0xc, 15),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA_DISP", 0,
|
|
7, 0xc, 16),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_LUMA_DISP", 0,
|
|
7, 0xc, 17),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA_DISP", 0,
|
|
7, 0xc, 18),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_R_LUMA_DISP", 0,
|
|
7, 0xc, 19),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_W_LUMA_DISP", 0,
|
|
7, 0xc, 20),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_RDMA_DISP", 0,
|
|
7, 0xc, 21),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_WDMA_DISP", 0,
|
|
7, 0xc, 22),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_WDMA1_DISP", 0,
|
|
7, 0xc, 23),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA1_DISP", 0,
|
|
7, 0xc, 24),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_HUFF_OFFSET1_DISP", 0,
|
|
7, 0xc, 25),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_HUFF_OFFSET0_DISP", 0,
|
|
7, 0xc, 26),
|
|
/*Larb8 */
|
|
MM_IOMMU_PORT_INIT("L8_VENC_RCPU_MDP", 1,
|
|
8, 0xc, 0),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REC_MDP", 1,
|
|
8, 0xc, 1),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_BSDMA_MDP", 1,
|
|
8, 0xc, 2),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SV_COMV_MDP", 1,
|
|
8, 0xc, 3),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_RD_COMV_MDP", 1,
|
|
8, 0xc, 4),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_MDP", 1,
|
|
8, 0xc, 5),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_LITE_MDP", 1,
|
|
8, 0xc, 6),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_Y_RDMA_MDP", 1,
|
|
8, 0xc, 7),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_C_RDMA_MDP", 1,
|
|
8, 0xc, 8),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_Q_TABLE_MDP", 1,
|
|
8, 0xc, 9),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_BSDMA_MDP", 1,
|
|
8, 0xc, 10),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_WDMA0_MDP", 1,
|
|
8, 0xc, 11),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_BSDMA0_MDP", 1,
|
|
8, 0xc, 12),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_MDP", 1,
|
|
8, 0xc, 13),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_LITE_MDP", 1,
|
|
8, 0xc, 14),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_CUR_LUMA_MDP", 1,
|
|
8, 0xc, 15),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_CUR_CHROMA_MDP", 1,
|
|
8, 0xc, 16),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REF_LUMA_MDP", 1,
|
|
8, 0xc, 17),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REF_CHROMA_MDP", 1,
|
|
8, 0xc, 18),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SUB_R_LUMA_MDP", 1,
|
|
8, 0xc, 19),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SUB_W_LUMA_MDP", 1,
|
|
8, 0xc, 20),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_RDMA_MDP", 1,
|
|
8, 0xc, 21),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_WDMA_MDP", 1,
|
|
8, 0xc, 22),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_WDMA1_MDP", 1,
|
|
8, 0xc, 23),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_BSDMA1_MDP", 1,
|
|
8, 0xc, 24),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_HUFF_OFFSET1_MDP", 1,
|
|
8, 0xc, 25),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_HUFF_OFFSET0_MDP", 1,
|
|
8, 0xc, 26),
|
|
/*Larb9 */
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGI_D1_MDP", 1,
|
|
9, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1_MDP", 1,
|
|
9, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DMGI_D1_MDP", 1,
|
|
9, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_DEPI_D1_MDP", 1,
|
|
9, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_ICE_D1_MDP", 1,
|
|
9, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D1_MDP", 1,
|
|
9, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D2_MDP", 1,
|
|
9, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTO_D1_MDP", 1,
|
|
9, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_CRZO_D1_MDP", 1,
|
|
9, 0x10, 8),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1_MDP", 1,
|
|
9, 0x10, 9),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_VIPI_D1_MDP", 1,
|
|
9, 0x10, 10),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_SMTI_D5_MDP", 1,
|
|
9, 0x10, 11),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1_MDP", 1,
|
|
9, 0x10, 12),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_W0_MDP", 1,
|
|
9, 0x10, 13),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_UFBC_R0_MDP", 1,
|
|
9, 0x10, 14),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1_MDP", 1,
|
|
9, 0x10, 15),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0_MDP", 1,
|
|
9, 0x10, 16),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA_MDP", 1,
|
|
9, 0x10, 17),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0_MDP", 1,
|
|
9, 0x10, 18),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1_MDP", 1,
|
|
9, 0x10, 19),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2_MDP", 1,
|
|
9, 0x10, 20),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3_MDP", 1,
|
|
9, 0x10, 21),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4_MDP", 1,
|
|
9, 0x10, 22),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5_MDP", 1,
|
|
9, 0x10, 23),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0_MDP", 1,
|
|
9, 0x10, 24),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1_MDP", 1,
|
|
9, 0x10, 25),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE6_MDP", 1,
|
|
9, 0x10, 26),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE7_MDP", 1,
|
|
9, 0x10, 27),
|
|
MM_IOMMU_PORT_INIT("L9_IMG_RESERVE8_MDP", 1,
|
|
9, 0x10, 28),
|
|
/*Larb11 */
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGI_D1_DISP", 0,
|
|
11, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1_DISP", 0,
|
|
11, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DMGI_D1_DISP", 0,
|
|
11, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_DEPI_D1_DISP", 0,
|
|
11, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_ICE_D1_DISP", 0,
|
|
11, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D1_DISP", 0,
|
|
11, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D2_DISP", 0,
|
|
11, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTO_D1_DISP", 0,
|
|
11, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_CRZO_D1_DISP", 0,
|
|
11, 0x10, 8),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1_DISP", 0,
|
|
11, 0x10, 9),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_VIPI_D1_DISP", 0,
|
|
11, 0x10, 10),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_SMTI_D5_DISP", 0,
|
|
11, 0x10, 11),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1_DISP", 0,
|
|
11, 0x10, 12),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_W0_DISP", 0,
|
|
11, 0x10, 13),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_UFBC_R0_DISP", 0,
|
|
11, 0x10, 14),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1_DISP", 0,
|
|
11, 0x10, 15),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0_DISP", 0,
|
|
11, 0x10, 16),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA_DISP", 0,
|
|
11, 0x10, 17),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0_DISP", 0,
|
|
11, 0x10, 18),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1_DISP", 0,
|
|
11, 0x10, 19),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2_DISP", 0,
|
|
11, 0x10, 20),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3_DISP", 0,
|
|
11, 0x10, 21),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4_DISP", 0,
|
|
11, 0x10, 22),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5_DISP", 0,
|
|
11, 0x10, 23),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0_DISP", 0,
|
|
11, 0x10, 24),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1_DISP", 0,
|
|
11, 0x10, 25),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE6_DISP", 0,
|
|
11, 0x10, 26),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE7_DISP", 0,
|
|
11, 0x10, 27),
|
|
MM_IOMMU_PORT_INIT("L11_IMG_RESERVE8_DISP", 0,
|
|
11, 0x10, 28),
|
|
/*Larb13 */
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWI_MDP", 1,
|
|
13, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO0_MDP", 1,
|
|
13, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_MRAWO1_MDP", 1,
|
|
13, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV1_MDP", 1,
|
|
13, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV2_MDP", 1,
|
|
13, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV3_MDP", 1,
|
|
13, 0x19, 5),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV4_MDP", 1,
|
|
13, 0x19, 6),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV5_MDP", 1,
|
|
13, 0x19, 7),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CAMSV6_MDP", 1,
|
|
13, 0x19, 8),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUI_MDP", 1,
|
|
13, 0x19, 9),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_CCUO_MDP", 1,
|
|
13, 0x19, 10),
|
|
MM_IOMMU_PORT_INIT("L13_CAM_FAKE_MDP", 1,
|
|
13, 0x19, 11),
|
|
/*Larb14 */
|
|
MM_IOMMU_PORT_INIT("L14_CAM_MRAWI_DISP", 0,
|
|
14, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_MRAWO0_DISP", 0,
|
|
14, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_MRAWO1_DISP", 0,
|
|
14, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CAMSV0_DISP", 0,
|
|
14, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUI_DISP", 0,
|
|
14, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("L14_CAM_CCUO_DISP", 0,
|
|
14, 0x19, 5),
|
|
/*Larb16 */
|
|
MM_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A_MDP", 1,
|
|
16, 0x1c, 0),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A_MDP", 1,
|
|
16, 0x1c, 1),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A_MDP", 1,
|
|
16, 0x1c, 2),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A_MDP", 1,
|
|
16, 0x1c, 3),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A_MDP", 1,
|
|
16, 0x1c, 4),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A_MDP", 1,
|
|
16, 0x1c, 5),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A_MDP", 1,
|
|
16, 0x1c, 6),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A_MDP", 1,
|
|
16, 0x1c, 7),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A_MDP", 1,
|
|
16, 0x1c, 8),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A_MDP", 1,
|
|
16, 0x1c, 9),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A_MDP", 1,
|
|
16, 0x1c, 10),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A_MDP", 1,
|
|
16, 0x1c, 11),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A_MDP", 1,
|
|
16, 0x1c, 12),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A_MDP", 1,
|
|
16, 0x1c, 13),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A_MDP", 1,
|
|
16, 0x1c, 14),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_MDP", 1,
|
|
16, 0x1c, 15),
|
|
MM_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A_MDP", 1,
|
|
16, 0x1c, 16),
|
|
/*Larb17 */
|
|
MM_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B_DISP", 0,
|
|
17, 0x1c, 0),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B_DISP", 0,
|
|
17, 0x1c, 1),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B_DISP", 0,
|
|
17, 0x1c, 2),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B_DISP", 0,
|
|
17, 0x1c, 3),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B_DISP", 0,
|
|
17, 0x1c, 4),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B_DISP", 0,
|
|
17, 0x1c, 5),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B_DISP", 0,
|
|
17, 0x1c, 6),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B_DISP", 0,
|
|
17, 0x1c, 7),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B_DISP", 0,
|
|
17, 0x1c, 8),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B_DISP", 0,
|
|
17, 0x1c, 9),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B_DISP", 0,
|
|
17, 0x1c, 10),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B_DISP", 0,
|
|
17, 0x1c, 11),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B_DISP", 0,
|
|
17, 0x1c, 12),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B_DISP", 0,
|
|
17, 0x1c, 13),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B_DISP", 0,
|
|
17, 0x1c, 14),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B_DISP", 0,
|
|
17, 0x1c, 15),
|
|
MM_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B_DISP", 0,
|
|
17, 0x1c, 16),
|
|
/*Larb18 */
|
|
MM_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C_MDP", 1,
|
|
18, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C_MDP", 1,
|
|
18, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C_MDP", 1,
|
|
18, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C_MDP", 1,
|
|
18, 0x14, 3),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C_MDP", 1,
|
|
18, 0x14, 4),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C_MDP", 1,
|
|
18, 0x14, 5),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C_MDP", 1,
|
|
18, 0x14, 6),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C_MDP", 1,
|
|
18, 0x14, 7),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C_MDP", 1,
|
|
18, 0x14, 8),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C_MDP", 1,
|
|
18, 0x14, 9),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C_MDP", 1,
|
|
18, 0x14, 10),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C_MDP", 1,
|
|
18, 0x14, 11),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C_MDP", 1,
|
|
18, 0x14, 12),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C_MDP", 1,
|
|
18, 0x14, 13),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C_MDP", 1,
|
|
18, 0x14, 14),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C_MDP", 1,
|
|
18, 0x14, 15),
|
|
MM_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C_MDP", 1,
|
|
18, 0x14, 16),
|
|
/*Larb19 */
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA_DISP", 0,
|
|
19, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA_DISP", 0,
|
|
19, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA_DISP", 0,
|
|
19, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA_DISP", 0,
|
|
19, 0x14, 3),
|
|
/*Larb20 */
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA_DISP", 0,
|
|
20, 0x15, 0),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB_DISP", 0,
|
|
20, 0x15, 1),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA_DISP", 0,
|
|
20, 0x15, 2),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB_DISP", 0,
|
|
20, 0x15, 3),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0_DISP", 0,
|
|
20, 0x15, 4),
|
|
MM_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA_DISP", 0,
|
|
20, 0x15, 5),
|
|
/*Larb22 */
|
|
MM_IOMMU_FAKE_PORT_INIT("L22_CCU_DISP", 0,
|
|
22, 0x18, 0, CCU_FAKE),
|
|
/*Larb23 */
|
|
MM_IOMMU_FAKE_PORT_INIT("L23_CCU_MDP", 1,
|
|
23, 0x18, 0, CCU_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6893[] = {
|
|
/*Larb21 */
|
|
APU_IOMMU_PORT_INIT("L21_APU_FAKE_DATA", 2,
|
|
21, 0x0, 0),
|
|
APU_IOMMU_PORT_INIT("L21_APU_FAKE_VLM", 2,
|
|
21, 0x1, 1),
|
|
APU_IOMMU_PORT_INIT("L21_APU_FAKE_CODE", 2,
|
|
21, 0x2, 2),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0x0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6983[] = {
|
|
/* Larb0 -- 16 */
|
|
MM_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", DISP_IOMMU, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L0_DMDP_RDMA0", DISP_IOMMU, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_HDR", DISP_IOMMU, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_2L_HDR", DISP_IOMMU, 0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL1_2L_HDR", DISP_IOMMU, 0, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_2L_NWCG_HDR", DISP_IOMMU, 0, 0x0, 5),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL1_2L_NWCG_HDR", DISP_IOMMU, 0, 0x0, 6),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_0_DISP", DISP_IOMMU, 0, 0x0, 7),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_2L_0", DISP_IOMMU, 0, 0x0, 8),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL1_2L_0", DISP_IOMMU, 0, 0x0, 9),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL0_2L_NWCG_0", DISP_IOMMU, 0, 0x0, 10),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_OVL1_2L_NWCG_0", DISP_IOMMU, 0, 0x0, 11),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_RDMA0", DISP_IOMMU, 0, 0x0, 12),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_WDMA0", DISP_IOMMU, 0, 0x0, 13),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_UFBC_WDMA0", DISP_IOMMU, 0, 0x0, 14),
|
|
MM_IOMMU_PORT_INIT("L0_DISP_FAKE0", DISP_IOMMU, 0, 0x0, 15),
|
|
|
|
/* Larb1 -- 8() */
|
|
MM_IOMMU_PORT_INIT("L1_DISP_OVL0_1", MDP_IOMMU, 1, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_OVL0_2L_1", MDP_IOMMU, 1, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_OVL1_2L_1", MDP_IOMMU, 1, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_OVL0_2L_NWCG_1", MDP_IOMMU, 1, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_OVL1_2L_NWCG_1", MDP_IOMMU, 1, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_RDMA1", MDP_IOMMU, 1, 0x0, 5),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_WDMA1", MDP_IOMMU, 1, 0x0, 6),
|
|
MM_IOMMU_PORT_INIT("L1_DISP_FAKE1", MDP_IOMMU, 1, 0x0, 7),
|
|
|
|
/* larb2 */
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA0", DISP_IOMMU, 2, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_RDMA2", DISP_IOMMU, 2, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT0", DISP_IOMMU, 2, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WROT2", DISP_IOMMU, 2, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_DISP_FAKE0", DISP_IOMMU, 2, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_FILMGRAIN0", DISP_IOMMU, 2, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_FILMGRAIN2", DISP_IOMMU, 2, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WDMA0", DISP_IOMMU, 2, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("L2_MDP_WDMA2", DISP_IOMMU, 2, 0x10, 8),
|
|
|
|
/* larb3 */
|
|
MM_IOMMU_PORT_INIT("L3_MDP_RDMA1", MDP_IOMMU, 3, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_RDMA3", MDP_IOMMU, 3, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WROT1", MDP_IOMMU, 3, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WROT3", MDP_IOMMU, 3, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_DISP_FAKE1", MDP_IOMMU, 3, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_FILMGRAIN1", MDP_IOMMU, 3, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_FILMGRAIN3", MDP_IOMMU, 3, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WDMA1", MDP_IOMMU, 3, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("L3_MDP_WDMA3", MDP_IOMMU, 3, 0x10, 8),
|
|
|
|
/* larb4 */
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", MDP_IOMMU, 4, 0x18, 0),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", MDP_IOMMU, 4, 0x18, 1),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", MDP_IOMMU, 4, 0x18, 2),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", MDP_IOMMU, 4, 0x18, 3),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", MDP_IOMMU, 4, 0x18, 4),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", MDP_IOMMU, 4, 0x18, 5),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", MDP_IOMMU, 4, 0x18, 6),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", MDP_IOMMU, 4, 0x18, 7),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", MDP_IOMMU, 4, 0x18, 8),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", MDP_IOMMU, 4, 0x18, 9),
|
|
MM_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT_C", MDP_IOMMU, 4, 0x18, 10),
|
|
|
|
/* larb5 */
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD_EXT", DISP_IOMMU, 5, 0x18, 0),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD2_EXT", DISP_IOMMU, 5, 0x18, 1),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_AVC_MV_EXT", DISP_IOMMU, 5, 0x18, 2),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_PRED_RD_EXT", DISP_IOMMU, 5, 0x18, 3),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_TILE_EXT", DISP_IOMMU, 5, 0x18, 4),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_LAT0_WDMA_EXT", DISP_IOMMU, 5, 0x18, 5),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_UFO_ENC_EXT", DISP_IOMMU, 5, 0x18, 6),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_UFO_ENC_EXT_C", DISP_IOMMU, 5, 0x18, 7),
|
|
MM_IOMMU_PORT_INIT("L5_VDEC_MC_EXT_C", DISP_IOMMU, 5, 0x18, 8),
|
|
|
|
/* larb6 */
|
|
MM_IOMMU_PORT_INIT("L6_VDEC_MINI_MDP_R0_EXT", DISP_IOMMU, 6, 0x38, 0),
|
|
MM_IOMMU_PORT_INIT("L6_VDEC_MINI_MDP_W0_EXT", DISP_IOMMU, 6, 0x38, 1),
|
|
MM_IOMMU_PORT_INIT("L6_VDEC_MINI_MDP_R1_EXT", DISP_IOMMU, 6, 0x38, 2),
|
|
MM_IOMMU_PORT_INIT("L6_VDEC_MINI_MDP_W1_EXT", DISP_IOMMU, 6, 0x38, 3),
|
|
|
|
/* larb7 */
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RCPU_DISP", DISP_IOMMU, 7, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REC_DISP", DISP_IOMMU, 7, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_BSDMA_DISP", DISP_IOMMU, 7, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SV_COMV_DISP", DISP_IOMMU, 7, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_RD_COMV_DISP", DISP_IOMMU, 7, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_DISP", DISP_IOMMU, 7, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_LITE_DISP", DISP_IOMMU, 7, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA_DISP", DISP_IOMMU, 7, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA_DISP", DISP_IOMMU, 7, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE_DISP", DISP_IOMMU, 7, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_W_LUMA_DISP", DISP_IOMMU, 7, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_RDMA_DISP", DISP_IOMMU, 7, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_EC_WPP_BSDMA_DISP", DISP_IOMMU, 7, 0x20, 12),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_EC_WPP_RDMA_DISP", DISP_IOMMU, 7, 0x20, 13),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_DB_SYSRAM_WDMA_DISP", DISP_IOMMU, 7, 0x20, 14),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_DB_SYSRAM_RDMA_DISP", DISP_IOMMU, 7, 0x20, 15),
|
|
MM_IOMMU_PORT_INIT("L7_JPGENC_BSDMA_DISP", DISP_IOMMU, 7, 0x20, 16),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_WDMA_0_DISP", DISP_IOMMU, 7, 0x20, 17),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_BSDMA_0_DISP", DISP_IOMMU, 7, 0x20, 18),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_DISP", DISP_IOMMU, 7, 0x20, 19),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_LITE_DISP", DISP_IOMMU, 7, 0x20, 20),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA_DISP", DISP_IOMMU, 7, 0x20, 21),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA_DISP", DISP_IOMMU, 7, 0x20, 22),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_LUMA_DISP", DISP_IOMMU, 7, 0x20, 23),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA_DISP", DISP_IOMMU, 7, 0x20, 24),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_SUB_R_LUMA_DISP", DISP_IOMMU, 7, 0x20, 25),
|
|
MM_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_WDMA_DISP", DISP_IOMMU, 7, 0x20, 26),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_WDMA_1_DISP", DISP_IOMMU, 7, 0x20, 27),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_BSDMA_1_DISP", DISP_IOMMU, 7, 0x20, 28),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_HUFF_OFFSET_1_DISP", DISP_IOMMU, 7, 0x20, 29),
|
|
MM_IOMMU_PORT_INIT("L7_JPGDEC_HUFF_OFFSET_0_DISP", DISP_IOMMU, 7, 0x20, 30),
|
|
|
|
/* larb8 */
|
|
MM_IOMMU_PORT_INIT("L8_VENC_RCPU_MDP", MDP_IOMMU, 8, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REC_MDP", MDP_IOMMU, 8, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_BSDMA_MDP", MDP_IOMMU, 8, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SV_COMV_MDP", MDP_IOMMU, 8, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_RD_COMV_MDP", MDP_IOMMU, 8, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_MDP", MDP_IOMMU, 8, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_LITE_MDP", MDP_IOMMU, 8, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_Y_RDMA_MDP", MDP_IOMMU, 8, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_C_RDMA_MDP", MDP_IOMMU, 8, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_Q_TABLE_MDP", MDP_IOMMU, 8, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SUB_W_LUMA_MDP", MDP_IOMMU, 8, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_RDMA_MDP", MDP_IOMMU, 8, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_EC_WPP_BSDMA_MDP", MDP_IOMMU, 8, 0x20, 12),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_EC_WPP_RDMA_MDP", MDP_IOMMU, 8, 0x20, 13),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_DB_SYSRAM_WDMA_MDP", MDP_IOMMU, 8, 0x20, 14),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_DB_SYSRAM_RDMA_MDP", MDP_IOMMU, 8, 0x20, 15),
|
|
MM_IOMMU_PORT_INIT("L8_JPGENC_BSDMA_MDP", MDP_IOMMU, 8, 0x20, 16),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_WDMA_0_MDP", MDP_IOMMU, 8, 0x20, 17),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_BSDMA_0_MDP", MDP_IOMMU, 8, 0x20, 18),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_MDP", MDP_IOMMU, 8, 0x20, 19),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_LITE_MDP", MDP_IOMMU, 8, 0x20, 20),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_CUR_LUMA_MDP", MDP_IOMMU, 8, 0x20, 21),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_CUR_CHROMA_MDP", MDP_IOMMU, 8, 0x20, 22),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REF_LUMA_MDP", MDP_IOMMU, 8, 0x20, 23),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_REF_CHROMA_MDP", MDP_IOMMU, 8, 0x20, 24),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_SUB_R_LUMA_MDP", MDP_IOMMU, 8, 0x20, 25),
|
|
MM_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_WDMA_MDP", MDP_IOMMU, 8, 0x20, 26),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_WDMA_1_MDP", MDP_IOMMU, 8, 0x20, 27),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_BSDMA_1_MDP", MDP_IOMMU, 8, 0x20, 28),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_HUFF_OFFSET_1_MDP", MDP_IOMMU, 8, 0x20, 29),
|
|
MM_IOMMU_PORT_INIT("L8_JPGDEC_HUFF_OFFSET_0_MDP", MDP_IOMMU, 8, 0x20, 30),
|
|
|
|
/* larb9 */
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGI_T1_A", DISP_IOMMU, 9, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_UFDI_T1_A", DISP_IOMMU, 9, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGBI_T1_A", DISP_IOMMU, 9, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGCI_T1_A", DISP_IOMMU, 9, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTI_T1_A", DISP_IOMMU, 9, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTI_T4_A", DISP_IOMMU, 9, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_TNCSTI_T1_A", DISP_IOMMU, 9, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_TNCSTI_T4_A", DISP_IOMMU, 9, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVO_T1_A", DISP_IOMMU, 9, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVBO_T1_A", DISP_IOMMU, 9, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVCO_T1_A", DISP_IOMMU, 9, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_TIMGO_T1_A", DISP_IOMMU, 9, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVO_T2_A", DISP_IOMMU, 9, 0x28, 12),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVO_T5_A", DISP_IOMMU, 9, 0x28, 13),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGI_T1_B", DISP_IOMMU, 9, 0x28, 14),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGBI_T1_B", DISP_IOMMU, 9, 0x28, 15),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_IMGCI_T1_B", DISP_IOMMU, 9, 0x28, 16),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTI_T4_B", DISP_IOMMU, 9, 0x28, 17),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_TNCSO_T1_A", DISP_IOMMU, 9, 0x28, 18),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTO_T1_A", DISP_IOMMU, 9, 0x28, 19),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTO_T4_A", DISP_IOMMU, 9, 0x28, 20),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_TNCSTO_T1_A", DISP_IOMMU, 9, 0x28, 21),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVO_T2_B", DISP_IOMMU, 9, 0x28, 22),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_YUVO_T5_B", DISP_IOMMU, 9, 0x28, 23),
|
|
MM_IOMMU_PORT_INIT("L9_IMG1_SMTO_T4_B", DISP_IOMMU, 9, 0x28, 24),
|
|
|
|
/* larb10 */
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMGI_D1", DISP_IOMMU, 10, 0x29, 0),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMGBI_D1", DISP_IOMMU, 10, 0x29, 1),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMGCI_D1", DISP_IOMMU, 10, 0x29, 2),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMGDI_D1", DISP_IOMMU, 10, 0x29, 3),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_DEPI_D1", DISP_IOMMU, 10, 0x29, 4),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_DMGI_D1", DISP_IOMMU, 10, 0x29, 5),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_SMTI_D1", DISP_IOMMU, 10, 0x29, 6),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_RECI_D1", DISP_IOMMU, 10, 0x29, 7),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_RECI_D1_N", DISP_IOMMU, 10, 0x29, 8),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_TNRWI_D1", DISP_IOMMU, 10, 0x29, 9),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_TNRCI_D1", DISP_IOMMU, 10, 0x29, 10),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_TNRCI_D1_N", DISP_IOMMU, 10, 0x29, 11),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMG4O_D1", DISP_IOMMU, 10, 0x29, 12),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_IMG4BO_D1", DISP_IOMMU, 10, 0x29, 13),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_SMTI_D8", DISP_IOMMU, 10, 0x29, 14),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_SMTO_D1", DISP_IOMMU, 10, 0x29, 15),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_TNRMO_D1", DISP_IOMMU, 10, 0x29, 16),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_TNRMO_D1_N", DISP_IOMMU, 10, 0x29, 17),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_SMTO_D8", DISP_IOMMU, 10, 0x29, 18),
|
|
MM_IOMMU_PORT_INIT("L10_IMG2_DBGO_D1", DISP_IOMMU, 10, 0x29, 19),
|
|
|
|
/* Larb11 */
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_RDMA0", DISP_IOMMU, 11, 0x2a, 0),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_RDMA1", DISP_IOMMU, 11, 0x2a, 1),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_RDMA_4P0", DISP_IOMMU, 11, 0x2a, 2),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_RDMA_4P1", DISP_IOMMU, 11, 0x2a, 3),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_CQ0", DISP_IOMMU, 11, 0x2a, 4),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_CQ1", DISP_IOMMU, 11, 0x2a, 5),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_PIMGI_P1", DISP_IOMMU, 11, 0x2a, 6),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_PIMGBI_P1", DISP_IOMMU, 11, 0x2a, 7),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_PIMGCI_P1", DISP_IOMMU, 11, 0x2a, 8),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_IMGI_T1_C", DISP_IOMMU, 11, 0x2a, 9),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_IMGBI_T1_C", DISP_IOMMU, 11, 0x2a, 10),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_IMGCI_T1_C", DISP_IOMMU, 11, 0x2a, 11),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTI_T1_C", DISP_IOMMU, 11, 0x2a, 12),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTI_T4_C", DISP_IOMMU, 11, 0x2a, 13),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTI_T6_C", DISP_IOMMU, 11, 0x2a, 14),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_YUVO_T1_C", DISP_IOMMU, 11, 0x2a, 15),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_YUVBO_T1_C", DISP_IOMMU, 11, 0x2a, 16),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_YUVCO_T1_C", DISP_IOMMU, 11, 0x2a, 17),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_WDMA0", DISP_IOMMU, 11, 0x2a, 18),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WPE_WDMA_4P0", DISP_IOMMU, 11, 0x2a, 19),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_WROT_P1", DISP_IOMMU, 11, 0x2a, 20),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_TCCSO_P1", DISP_IOMMU, 11, 0x2a, 21),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_TCCSI_P1", DISP_IOMMU, 11, 0x2a, 22),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_TIMGO_T1_C", DISP_IOMMU, 11, 0x2a, 23),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_YUVO_T2_C", DISP_IOMMU, 11, 0x2a, 24),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_YUVO_T5_C", DISP_IOMMU, 11, 0x2a, 25),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTO_T1_C", DISP_IOMMU, 11, 0x2a, 26),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTO_T4_C", DISP_IOMMU, 11, 0x2a, 27),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_SMTO_T6_C", DISP_IOMMU, 11, 0x2a, 28),
|
|
MM_IOMMU_PORT_INIT("L11_IMG2_DBGO_T1_C", DISP_IOMMU, 11, 0x2a, 29),
|
|
|
|
/* larb12 */
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_RDA0", MDP_IOMMU, 12, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_RDB0", MDP_IOMMU, 12, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_WRA0", MDP_IOMMU, 12, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_WR0B", MDP_IOMMU, 12, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_ME_RDMA", MDP_IOMMU, 12, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_ME_WDMA", MDP_IOMMU, 12, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DVS_RDMA", MDP_IOMMU, 12, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DVS_WDMA", MDP_IOMMU, 12, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DVP_RDMA", MDP_IOMMU, 12, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DVP_WDMA", MDP_IOMMU, 12, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_2ND_RDA0", MDP_IOMMU, 12, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_2ND_RDB0", MDP_IOMMU, 12, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_2ND_WRA0", MDP_IOMMU, 12, 0x28, 12),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_FDVT_2ND_WRB0", MDP_IOMMU, 12, 0x28, 13),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DHZEI_E1", MDP_IOMMU, 12, 0x28, 14),
|
|
MM_IOMMU_PORT_INIT("L12_IPE_DHZEO_E1", MDP_IOMMU, 12, 0x28, 15),
|
|
|
|
/* larb13 */
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_E1", DISP_IOMMU, 13, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_E2", DISP_IOMMU, 13, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_A_IMGO_1", DISP_IOMMU, 13, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_C_IMGO_1", DISP_IOMMU, 13, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_A_IMGO_2", DISP_IOMMU, 13, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_C_IMGO_2", DISP_IOMMU, 13, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_PDAI_A_0", DISP_IOMMU, 13, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_PDAI_A_1", DISP_IOMMU, 13, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_B_E1", DISP_IOMMU, 13, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_B_E2", DISP_IOMMU, 13, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_C_E1", DISP_IOMMU, 13, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_CAMSV_CQI_C_E2", DISP_IOMMU, 13, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_E_IMGO_1", DISP_IOMMU, 13, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_E_IMGO_2", DISP_IOMMU, 13, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_A_UFEO_1", DISP_IOMMU, 13, 0x30, 14),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_C_UFEO_1", DISP_IOMMU, 13, 0x30, 15),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_A_UFEO_2", DISP_IOMMU, 13, 0x30, 16),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_C_UFEO_2", DISP_IOMMU, 13, 0x30, 17),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_E_UFEO_1", DISP_IOMMU, 13, 0x30, 18),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_E_UFEO_2", DISP_IOMMU, 13, 0x30, 19),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_G_IMGO_1", DISP_IOMMU, 13, 0x30, 20),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_GCAMSV_G_IMGO_2", DISP_IOMMU, 13, 0x30, 21),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_PDAO_A", DISP_IOMMU, 13, 0x30, 22),
|
|
MM_IOMMU_PORT_INIT("L13_CAM1_PDAO_C", DISP_IOMMU, 13, 0x30, 23),
|
|
|
|
/* larb14 */
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_B_IMGO_1", MDP_IOMMU, 14, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_B_IMGO_2", MDP_IOMMU, 14, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_SCAMSV_A_IMGO_1", MDP_IOMMU, 14, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_SCAMSV_A_IMGO_2", MDP_IOMMU, 14, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_SCAMSV_B_IMGO_1", MDP_IOMMU, 14, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_SCAMSV_B_IMGO_2", MDP_IOMMU, 14, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_PDAI_B_0", MDP_IOMMU, 14, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_PDAI_B_1", MDP_IOMMU, 14, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_D_IMGO_1", MDP_IOMMU, 14, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_D_IMGO_2", MDP_IOMMU, 14, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_F_IMGO_1", MDP_IOMMU, 14, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_F_IMGO_2", MDP_IOMMU, 14, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_H_IMGO_1", MDP_IOMMU, 14, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_H_IMGO_2", MDP_IOMMU, 14, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_B_UFEO_1", MDP_IOMMU, 14, 0x30, 14),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_B_UFEO_2", MDP_IOMMU, 14, 0x30, 15),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_D_UFEO_1", MDP_IOMMU, 14, 0x30, 16),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_GCAMSV_D_UFEO_2", MDP_IOMMU, 14, 0x30, 17),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_PDAO_B", MDP_IOMMU, 14, 0x30, 18),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_IPUI", MDP_IOMMU, 14, 0x30, 19),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_IPUO", MDP_IOMMU, 14, 0x30, 20),
|
|
MM_IOMMU_PORT_INIT("L14_CAM1_IPU3O", MDP_IOMMU, 14, 0x30, 21),
|
|
|
|
/* Larb15 */
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_VIP1_D1", MDP_IOMMU, 15, 0x29, 0),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_VIPBI_D1", MDP_IOMMU, 15, 0x29, 1),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTI_D6", MDP_IOMMU, 15, 0x29, 2),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCSTI_D1", MDP_IOMMU, 15, 0x29, 3),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCSTI_D4", MDP_IOMMU, 15, 0x29, 4),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTI_D4", MDP_IOMMU, 15, 0x29, 5),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_IMG3O_D1", MDP_IOMMU, 15, 0x29, 6),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_IMG3BO_D1", MDP_IOMMU, 15, 0x29, 7),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_IMG3CO_D1", MDP_IOMMU, 15, 0x29, 8),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_IMG2O_D1", MDP_IOMMU, 15, 0x29, 9),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTI_D9", MDP_IOMMU, 15, 0x29, 10),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTO_D4", MDP_IOMMU, 15, 0x29, 11),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_FEO_D1", MDP_IOMMU, 15, 0x29, 12),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCSO_D1", MDP_IOMMU, 15, 0x29, 13),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCSTO_D1", MDP_IOMMU, 15, 0x29, 14),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTO_D6", MDP_IOMMU, 15, 0x29, 15),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_SMTO_D9", MDP_IOMMU, 15, 0x29, 16),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCO_D1", MDP_IOMMU, 15, 0x29, 17),
|
|
MM_IOMMU_PORT_INIT("L15_IMG2_TNCO_D1_N", MDP_IOMMU, 15, 0x29, 18),
|
|
|
|
/* larb16 */
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_IMGP_R1", MDP_IOMMU, 16, 0x32, 0),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_CQI_R1", MDP_IOMMU, 16, 0x32, 1),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_CQI_R2", MDP_IOMMU, 16, 0x32, 2),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_BPCI_R1", MDP_IOMMU, 16, 0x32, 3),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_LSCI_R1", MDP_IOMMU, 16, 0x32, 4),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_RAWI_R2", MDP_IOMMU, 16, 0x32, 5),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_RAWI_R3", MDP_IOMMU, 16, 0x32, 6),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_UFDI_R2", MDP_IOMMU, 16, 0x32, 7),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_UFDI_R3", MDP_IOMMU, 16, 0x32, 8),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_RAWI_R4", MDP_IOMMU, 16, 0x32, 9),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_RAWI_R5", MDP_IOMMU, 16, 0x32, 10),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_AAI_R1", MDP_IOMMU, 16, 0x32, 11),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_UFDI_R5", MDP_IOMMU, 16, 0x32, 12),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_FHO_R1", MDP_IOMMU, 16, 0x32, 13),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_AAO_R1", MDP_IOMMU, 16, 0x32, 14),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_TSFSO_R1", MDP_IOMMU, 16, 0x32, 15),
|
|
MM_IOMMU_PORT_INIT("L16_CAM2_FLKO_R1", MDP_IOMMU, 16, 0x32, 16),
|
|
|
|
/* larb17 */
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_YUVO_R1", MDP_IOMMU, 17, 0x33, 0),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_YUVO_R3", MDP_IOMMU, 17, 0x33, 1),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_YUVCO_R1", MDP_IOMMU, 17, 0x33, 2),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_YUVO_R2", MDP_IOMMU, 17, 0x33, 3),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_RZH1N2TO_R1", MDP_IOMMU, 17, 0x33, 4),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_DRZS4NO_R1", MDP_IOMMU, 17, 0x33, 5),
|
|
MM_IOMMU_PORT_INIT("L17_CAM3_TNCSO_R1", MDP_IOMMU, 17, 0x33, 6),
|
|
|
|
/* larb18 */
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL0_CQI_E1", MDP_IOMMU, 18, 0x2b, 0),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL0_CQI_E2", MDP_IOMMU, 18, 0x2b, 1),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL0_IPUI_E1", MDP_IOMMU, 18, 0x2b, 2),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL0_IPUO_E1", MDP_IOMMU, 18, 0x2b, 3),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL1_CQI_E1", MDP_IOMMU, 18, 0x2b, 4),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL1_CQI_E2", MDP_IOMMU, 18, 0x2b, 5),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL1_IPUI_E1", MDP_IOMMU, 18, 0x2b, 6),
|
|
MM_IOMMU_PORT_INIT("L18_IMGADL1_IPUO_E1", MDP_IOMMU, 18, 0x2b, 7),
|
|
|
|
/* larb19 */
|
|
MM_IOMMU_PORT_INIT("L19_CAM_CCUI", MDP_IOMMU, 19, 0x35, 0),
|
|
MM_IOMMU_PORT_INIT("L19_CAM_CCUO", MDP_IOMMU, 19, 0x35, 1),
|
|
MM_IOMMU_PORT_INIT("L19_CAM_CCUI2", MDP_IOMMU, 19, 0x35, 2),
|
|
MM_IOMMU_PORT_INIT("L19_CAM_CCUO2", MDP_IOMMU, 19, 0x35, 3),
|
|
|
|
/* larb20 */
|
|
MM_IOMMU_PORT_INIT("L20_DISP_POSTMASK0", MDP_IOMMU, 20, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L20_DMDP_RDMA0", MDP_IOMMU, 20, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_HDR", MDP_IOMMU, 20, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_2L_HDR", MDP_IOMMU, 20, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL1_2L_HDR", MDP_IOMMU, 20, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_2L_NWCG_HDR", MDP_IOMMU, 20, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL1_2L_NWCG_HDR", MDP_IOMMU, 20, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_0", MDP_IOMMU, 20, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_2L_0", MDP_IOMMU, 20, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL1_2L_0", MDP_IOMMU, 20, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL0_2L_NWCG_0", MDP_IOMMU, 20, 0x8, 10),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_OVL1_2L_NWCG_0", MDP_IOMMU, 20, 0x8, 11),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_RDMA0", MDP_IOMMU, 20, 0x8, 12),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_WDMA0", MDP_IOMMU, 20, 0x8, 13),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_UFBC_WDMA0", MDP_IOMMU, 20, 0x8, 14),
|
|
MM_IOMMU_PORT_INIT("L20_DISP_FAKE0", MDP_IOMMU, 20, 0x8, 15),
|
|
|
|
/* larb21 */
|
|
MM_IOMMU_PORT_INIT("L21_DISP_OVL0_1", DISP_IOMMU, 21, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_OVL0_2L_1", DISP_IOMMU, 21, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_OVL1_2L_1", DISP_IOMMU, 21, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_OVL0_2L_NWCG1", DISP_IOMMU, 21, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_OVL1_2L_NWCG1", DISP_IOMMU, 21, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_RDMA1", DISP_IOMMU, 21, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_WDMA1", DISP_IOMMU, 21, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("L21_DISP_FAKE1", DISP_IOMMU, 21, 0x8, 7),
|
|
|
|
/* Larb22 */
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_RDMA0", MDP_IOMMU, 22, 0x2a, 0),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_RDMA1", MDP_IOMMU, 22, 0x2a, 1),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_UFDI_T1_C", MDP_IOMMU, 22, 0x2a, 2),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_RDMA_4P1", MDP_IOMMU, 22, 0x2a, 3),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_CQ0", MDP_IOMMU, 22, 0x2a, 4),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_CQ1", MDP_IOMMU, 22, 0x2a, 5),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_PIMGI_P1", MDP_IOMMU, 22, 0x2a, 6),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_PIMGBI_P1", MDP_IOMMU, 22, 0x2a, 7),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_PIMGCI_P1", MDP_IOMMU, 22, 0x2a, 8),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_IMGI_T1_C", MDP_IOMMU, 22, 0x2a, 9),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_IMGBI_T1_C", MDP_IOMMU, 22, 0x2a, 10),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_IMGCI_T1_C", MDP_IOMMU, 22, 0x2a, 11),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTI_T1_C", MDP_IOMMU, 22, 0x2a, 12),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTI_T4_C", MDP_IOMMU, 22, 0x2a, 13),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTI_T6_C", MDP_IOMMU, 22, 0x2a, 14),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_YUVO_T1_C", MDP_IOMMU, 22, 0x2a, 15),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_YUVBO_T1_C", MDP_IOMMU, 22, 0x2a, 16),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_YUVCO_T1_C", MDP_IOMMU, 22, 0x2a, 17),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_WDMA0", MDP_IOMMU, 22, 0x2a, 18),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WPE_WDMA_4P0", MDP_IOMMU, 22, 0x2a, 19),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_WROT_P1", MDP_IOMMU, 22, 0x2a, 20),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_TCCSO_P1", MDP_IOMMU, 22, 0x2a, 21),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_TCCSI_P1", MDP_IOMMU, 22, 0x2a, 22),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_TIMGO_T1_C", MDP_IOMMU, 22, 0x2a, 23),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_YUVO_T2_C", MDP_IOMMU, 22, 0x2a, 24),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_YUVO_T5_C", MDP_IOMMU, 22, 0x2a, 25),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTO_T1_C", MDP_IOMMU, 22, 0x2a, 26),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTO_T4_C", MDP_IOMMU, 22, 0x2a, 27),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_SMTO_T6_C", MDP_IOMMU, 22, 0x2a, 28),
|
|
MM_IOMMU_PORT_INIT("L22_IMG2_DBGO_T1_C", MDP_IOMMU, 22, 0x2a, 29),
|
|
|
|
/* Larb23 */
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_RDMA0", DISP_IOMMU, 23, 0x2b, 0),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_RDMA1", DISP_IOMMU, 23, 0x2b, 1),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_RDMA_4P0", DISP_IOMMU, 23, 0x2b, 2),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_RDMA_4P1", DISP_IOMMU, 23, 0x2b, 3),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_CQ0", DISP_IOMMU, 23, 0x2b, 4),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_CQ1", DISP_IOMMU, 23, 0x2b, 5),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_PIMGI_P1", DISP_IOMMU, 23, 0x2b, 6),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_PIMGBI_P1", DISP_IOMMU, 23, 0x2b, 7),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_PIMGCI_P1", DISP_IOMMU, 23, 0x2b, 8),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_IMGI_T1_C", DISP_IOMMU, 23, 0x2b, 9),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_IMGBI_T1_C", DISP_IOMMU, 23, 0x2b, 10),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_IMGCI_T1_C", DISP_IOMMU, 23, 0x2b, 11),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTI_T1_C", DISP_IOMMU, 23, 0x2b, 12),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTI_T4_C", DISP_IOMMU, 23, 0x2b, 13),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTI_T6_C", DISP_IOMMU, 23, 0x2b, 14),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_YUVO_T1_C", DISP_IOMMU, 23, 0x2b, 15),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_YUVBO_T1_C", DISP_IOMMU, 23, 0x2b, 16),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_YUVCO_T1_C", DISP_IOMMU, 23, 0x2b, 17),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_WDMA0", DISP_IOMMU, 23, 0x2b, 18),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WPE_WDMA_4P0", DISP_IOMMU, 23, 0x2b, 19),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_WROT_P1", DISP_IOMMU, 23, 0x2b, 20),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_TCCSO_P1", DISP_IOMMU, 23, 0x2b, 21),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_TCCSI_P1", DISP_IOMMU, 23, 0x2b, 22),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_TIMGO_T1_C", DISP_IOMMU, 23, 0x2b, 23),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_YUVO_T2_C", DISP_IOMMU, 23, 0x2b, 24),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_YUVO_T5_C", DISP_IOMMU, 23, 0x2b, 25),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTO_T1_C", DISP_IOMMU, 23, 0x2b, 26),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTO_T4_C", DISP_IOMMU, 23, 0x2b, 27),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_SMTO_T6_C", DISP_IOMMU, 23, 0x2b, 28),
|
|
MM_IOMMU_PORT_INIT("L23_IMG2_DBGO_T1_C", DISP_IOMMU, 23, 0x2b, 29),
|
|
|
|
/* larb25 */
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_LSCI_M1", DISP_IOMMU, 25, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_CQI_M1", DISP_IOMMU, 25, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_CQI_M2", DISP_IOMMU, 25, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_IMGO_M1", DISP_IOMMU, 25, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_IMGBO_M1", DISP_IOMMU, 25, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW2_LSCI_M1", DISP_IOMMU, 25, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW2_CQI_M1", DISP_IOMMU, 25, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW2_CQI_M2", DISP_IOMMU, 25, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW2_IMGO_M1", DISP_IOMMU, 25, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW2_IMGBO_M1", DISP_IOMMU, 25, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_MRAW0_AFO_M1", DISP_IOMMU, 25, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_PDAI_A0", DISP_IOMMU, 25, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_PDAI_A1", DISP_IOMMU, 25, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("L25_CAM_PDAO_A", DISP_IOMMU, 25, 0x31, 13),
|
|
|
|
/* larb26 */
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_LSCI_M1", MDP_IOMMU, 26, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_CQI_M1", MDP_IOMMU, 26, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_CQI_M2", MDP_IOMMU, 26, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_IMGO_M1", MDP_IOMMU, 26, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_IMGBO_M1", MDP_IOMMU, 26, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW3_LSCI_M1", MDP_IOMMU, 26, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW3_CQI_M1", MDP_IOMMU, 26, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW3_CQI_M2", MDP_IOMMU, 26, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW3_IMGO_M1", MDP_IOMMU, 26, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW3_IMGBO_M1", MDP_IOMMU, 26, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_MRAW1_AFO_M1", MDP_IOMMU, 26, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_PDAI_B0", MDP_IOMMU, 26, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_PDAI_B1", MDP_IOMMU, 26, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("L26_CAM_PDAO_B", MDP_IOMMU, 26, 0x31, 13),
|
|
|
|
/* larb27 */
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_IMGP_R1", DISP_IOMMU, 27, 0x32, 0),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_CQI_R1", DISP_IOMMU, 27, 0x32, 1),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_CQI_R2", DISP_IOMMU, 27, 0x32, 2),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_BPCI_R1", DISP_IOMMU, 27, 0x32, 3),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_LSCI_R1", DISP_IOMMU, 27, 0x32, 4),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_RAWI_R2", DISP_IOMMU, 27, 0x32, 5),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_RAWI_R3", DISP_IOMMU, 27, 0x32, 6),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_UFDI_R2", DISP_IOMMU, 27, 0x32, 7),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_UFDI_R3", DISP_IOMMU, 27, 0x32, 8),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_RAWI_R4", DISP_IOMMU, 27, 0x32, 9),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_RAWI_R5", DISP_IOMMU, 27, 0x32, 10),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_AAI_R1", DISP_IOMMU, 27, 0x32, 11),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_UFDI_R5", DISP_IOMMU, 27, 0x32, 12),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_FHO_R1", DISP_IOMMU, 27, 0x32, 13),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_AAO_R1", DISP_IOMMU, 27, 0x32, 14),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_TSFSO_R1", DISP_IOMMU, 27, 0x32, 15),
|
|
MM_IOMMU_PORT_INIT("L27_CAM2_FLKO_R1", DISP_IOMMU, 27, 0x32, 16),
|
|
|
|
/* larb28 */
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_IMGP_R1", MDP_IOMMU, 28, 0x34, 0),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_CQI_R1", MDP_IOMMU, 28, 0x34, 1),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_CQI_R2", MDP_IOMMU, 28, 0x34, 2),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_BPCI_R1", MDP_IOMMU, 28, 0x34, 3),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_LSCI_R1", MDP_IOMMU, 28, 0x34, 4),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_RAWI_R2", MDP_IOMMU, 28, 0x34, 5),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_RAWI_R3", MDP_IOMMU, 28, 0x34, 6),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_UFDI_R2", MDP_IOMMU, 28, 0x34, 7),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_UFDI_R3", MDP_IOMMU, 28, 0x34, 8),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_RAWI_R4", MDP_IOMMU, 28, 0x34, 9),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_RAWI_R5", MDP_IOMMU, 28, 0x34, 10),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_AAI_R1", MDP_IOMMU, 28, 0x34, 11),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_UFDI_R5", MDP_IOMMU, 28, 0x34, 12),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_FHO_R1", MDP_IOMMU, 28, 0x34, 13),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_AAO_R1", MDP_IOMMU, 28, 0x34, 14),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_TSFSO_R1", MDP_IOMMU, 28, 0x34, 15),
|
|
MM_IOMMU_PORT_INIT("L28_CAM2_FLKO_R1", MDP_IOMMU, 28, 0x34, 16),
|
|
|
|
/* larb29 */
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_YUVO_R1", DISP_IOMMU, 29, 0x33, 0),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_YUVO_R3", DISP_IOMMU, 29, 0x33, 1),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_YUVCO_R1", DISP_IOMMU, 29, 0x33, 2),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_YUVO_R2", DISP_IOMMU, 29, 0x33, 3),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_RZH1N2TO_R1", DISP_IOMMU, 29, 0x33, 4),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_DRZS4NO_R1", DISP_IOMMU, 29, 0x33, 5),
|
|
MM_IOMMU_PORT_INIT("L29_CAM3_TNCSO_R1", DISP_IOMMU, 29, 0x33, 6),
|
|
|
|
/* larb30 */
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_YUVO_R1", DISP_IOMMU, 30, 0x34, 0),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_YUVO_R3", DISP_IOMMU, 30, 0x34, 1),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_YUVCO_R1", DISP_IOMMU, 30, 0x34, 2),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_YUVO_R2", DISP_IOMMU, 30, 0x34, 3),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_RZH1N2TO_R1", DISP_IOMMU, 30, 0x34, 4),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_DRZS4NO_R1", DISP_IOMMU, 30, 0x34, 5),
|
|
MM_IOMMU_PORT_INIT("L30_CAM3_TNCSO_R1", DISP_IOMMU, 30, 0x34, 6),
|
|
|
|
/* Larb31 -- 2 */
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU0", MDP_IOMMU, 31, 0x36, 0, CCU_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU1", MDP_IOMMU, 31, 0x37, 1, CCU_FAKE),
|
|
|
|
/* Larb32 -- 2 */
|
|
MM_IOMMU_FAKE_PORT_INIT("VIDEO_uP", MDP_IOMMU, 32, 0x7, 0,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_D_M", MDP_IOMMU, 32, 0x7, 1,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_M_M", MDP_IOMMU, 32, 0x7, 2,
|
|
GCE_VIDEOUP_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6983[] = {
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI0", 0, 0, 0, 0),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI1", 0, 0, 0, 1),
|
|
APU_IOMMU_PORT_INIT("APU_EDMA", 0, 0, 0, 2),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI0", 0, 0, 0, 3),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI1", 0, 0, 0, 4),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI2", 0, 0, 0, 5),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI3", 0, 0, 0, 6),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI0", 0, 0, 0, 7),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI1", 0, 0, 0, 8),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI2", 0, 0, 0, 9),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI3", 0, 0, 0, 10),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI0", 0, 0, 0, 11),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI1", 0, 0, 0, 12),
|
|
APU_IOMMU_PORT_INIT("APU_EDMA", 0, 0, 0, 13),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI0", 0, 0, 0, 14),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI1", 0, 0, 0, 15),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI2", 0, 0, 0, 16),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI3", 0, 0, 0, 17),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI0", 0, 0, 0, 18),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI1", 0, 0, 0, 19),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI2", 0, 0, 0, 20),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI3", 0, 0, 0, 21),
|
|
APU_IOMMU_PORT_INIT("APU_uP", 0, 0, 0, 22),
|
|
APU_IOMMU_PORT_INIT("APU_LOGGER", 0, 0, 0, 23),
|
|
APU_IOMMU_PORT_INIT("APU_APB2AXI", 0, 0, 0, 24),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI0", 1, 0, 0, 0),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI1", 1, 0, 0, 1),
|
|
APU_IOMMU_PORT_INIT("APU_EDMA", 1, 0, 0, 2),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI0", 1, 0, 0, 3),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI1", 1, 0, 0, 4),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI2", 1, 0, 0, 5),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI3", 1, 0, 0, 6),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI0", 1, 0, 0, 7),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI1", 1, 0, 0, 8),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI2", 1, 0, 0, 9),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI3", 1, 0, 0, 10),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI0", 1, 0, 0, 11),
|
|
APU_IOMMU_PORT_INIT("APU_MVPU0_AXI1", 1, 0, 0, 12),
|
|
APU_IOMMU_PORT_INIT("APU_EDMA", 1, 0, 0, 13),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI0", 1, 0, 0, 14),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI1", 1, 0, 0, 15),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI2", 1, 0, 0, 16),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA0_AXI3", 1, 0, 0, 17),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI0", 1, 0, 0, 18),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI1", 1, 0, 0, 19),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI2", 1, 0, 0, 20),
|
|
APU_IOMMU_PORT_INIT("APU_MDLA1_AXI3", 1, 0, 0, 21),
|
|
APU_IOMMU_PORT_INIT("APU_uP", 1, 0, 0, 22),
|
|
APU_IOMMU_PORT_INIT("APU_LOGGER", 1, 0, 0, 23),
|
|
APU_IOMMU_PORT_INIT("APU_APB2AXI", 1, 0, 0, 24),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0x1f)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6879[] = {
|
|
/* Larb0 */
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT0", DISP_IOMMU, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT1", DISP_IOMMU, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT2", DISP_IOMMU, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT3", DISP_IOMMU, 0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT4", DISP_IOMMU, 0, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT5", DISP_IOMMU, 0, 0x0, 5),
|
|
|
|
/* Larb1 */
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT0", DISP_IOMMU, 1, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT1", DISP_IOMMU, 1, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT2", DISP_IOMMU, 1, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT3", DISP_IOMMU, 1, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT4", DISP_IOMMU, 1, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT5", DISP_IOMMU, 1, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT6", DISP_IOMMU, 1, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT7", DISP_IOMMU, 1, 0x8, 7),
|
|
|
|
/* larb2 */
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT0", DISP_IOMMU, 2, 0x14, 0),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT1", DISP_IOMMU, 2, 0x14, 1),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT2", DISP_IOMMU, 2, 0x14, 2),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT3", DISP_IOMMU, 2, 0x14, 3),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT4", DISP_IOMMU, 2, 0x14, 4),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT5", DISP_IOMMU, 2, 0x14, 5),
|
|
|
|
/* larb4 */
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT0", DISP_IOMMU, 4, 0x1c, 0),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT1", DISP_IOMMU, 4, 0x1c, 1),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT2", DISP_IOMMU, 4, 0x1c, 2),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT3", DISP_IOMMU, 4, 0x1c, 3),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT4", DISP_IOMMU, 4, 0x1c, 4),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT5", DISP_IOMMU, 4, 0x1c, 5),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT6", DISP_IOMMU, 4, 0x1c, 6),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT7", DISP_IOMMU, 4, 0x1c, 7),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT8", DISP_IOMMU, 4, 0x1c, 8),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT9", DISP_IOMMU, 4, 0x1c, 9),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT10", DISP_IOMMU, 4, 0x1c, 10),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT11", DISP_IOMMU, 4, 0x1c, 11),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT12", DISP_IOMMU, 4, 0x1c, 12),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT13", DISP_IOMMU, 4, 0x1c, 13),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT14", DISP_IOMMU, 4, 0x1c, 14),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT15", DISP_IOMMU, 4, 0x1c, 15),
|
|
|
|
/* larb7 */
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT0", DISP_IOMMU, 7, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT1", DISP_IOMMU, 7, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT2", DISP_IOMMU, 7, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT3", DISP_IOMMU, 7, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT4", DISP_IOMMU, 7, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT5", DISP_IOMMU, 7, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT6", DISP_IOMMU, 7, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT7", DISP_IOMMU, 7, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT8", DISP_IOMMU, 7, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT9", DISP_IOMMU, 7, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT10", DISP_IOMMU, 7, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT11", DISP_IOMMU, 7, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT12", DISP_IOMMU, 7, 0x20, 12),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT13", DISP_IOMMU, 7, 0x20, 13),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT14", DISP_IOMMU, 7, 0x20, 14),
|
|
|
|
|
|
/* larb9 */
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT0", DISP_IOMMU, 9, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT1", DISP_IOMMU, 9, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT2", DISP_IOMMU, 9, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT3", DISP_IOMMU, 9, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT4", DISP_IOMMU, 9, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT5", DISP_IOMMU, 9, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT6", DISP_IOMMU, 9, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT7", DISP_IOMMU, 9, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT8", DISP_IOMMU, 9, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT9", DISP_IOMMU, 9, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT10", DISP_IOMMU, 9, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT11", DISP_IOMMU, 9, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT12", DISP_IOMMU, 9, 0x28, 12),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT13", DISP_IOMMU, 9, 0x28, 13),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT14", DISP_IOMMU, 9, 0x28, 14),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT15", DISP_IOMMU, 9, 0x28, 15),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT16", DISP_IOMMU, 9, 0x28, 16),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT17", DISP_IOMMU, 9, 0x28, 17),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT18", DISP_IOMMU, 9, 0x28, 18),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT19", DISP_IOMMU, 9, 0x28, 19),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT20", DISP_IOMMU, 9, 0x28, 20),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT21", DISP_IOMMU, 9, 0x28, 21),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT22", DISP_IOMMU, 9, 0x28, 22),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT23", DISP_IOMMU, 9, 0x28, 23),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT24", DISP_IOMMU, 9, 0x28, 24),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT25", DISP_IOMMU, 9, 0x28, 25),
|
|
|
|
/* larb10 */
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT0", DISP_IOMMU, 10, 0x29, 0),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT1", DISP_IOMMU, 10, 0x29, 1),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT2", DISP_IOMMU, 10, 0x29, 2),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT3", DISP_IOMMU, 10, 0x29, 3),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT4", DISP_IOMMU, 10, 0x29, 4),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT5", DISP_IOMMU, 10, 0x29, 5),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT6", DISP_IOMMU, 10, 0x29, 6),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT7", DISP_IOMMU, 10, 0x29, 7),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT8", DISP_IOMMU, 10, 0x29, 8),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT9", DISP_IOMMU, 10, 0x29, 9),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT10", DISP_IOMMU, 10, 0x29, 10),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT11", DISP_IOMMU, 10, 0x29, 11),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT12", DISP_IOMMU, 10, 0x29, 12),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT13", DISP_IOMMU, 10, 0x29, 13),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT14", DISP_IOMMU, 10, 0x29, 14),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT15", DISP_IOMMU, 10, 0x29, 15),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT16", DISP_IOMMU, 10, 0x29, 16),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT17", DISP_IOMMU, 10, 0x29, 17),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT18", DISP_IOMMU, 10, 0x29, 18),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT19", DISP_IOMMU, 10, 0x29, 19),
|
|
|
|
/* Larb11 */
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT0", DISP_IOMMU, 11, 0x2a, 0),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT1", DISP_IOMMU, 11, 0x2a, 1),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT2", DISP_IOMMU, 11, 0x2a, 2),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT3", DISP_IOMMU, 11, 0x2a, 3),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT4", DISP_IOMMU, 11, 0x2a, 4),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT5", DISP_IOMMU, 11, 0x2a, 5),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT6", DISP_IOMMU, 11, 0x2a, 6),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT7", DISP_IOMMU, 11, 0x2a, 7),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT8", DISP_IOMMU, 11, 0x2a, 8),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT9", DISP_IOMMU, 11, 0x2a, 9),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT10", DISP_IOMMU, 11, 0x2a, 10),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT11", DISP_IOMMU, 11, 0x2a, 11),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT12", DISP_IOMMU, 11, 0x2a, 12),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT13", DISP_IOMMU, 11, 0x2a, 13),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT14", DISP_IOMMU, 11, 0x2a, 14),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT15", DISP_IOMMU, 11, 0x2a, 15),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT16", DISP_IOMMU, 11, 0x2a, 16),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT17", DISP_IOMMU, 11, 0x2a, 17),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT18", DISP_IOMMU, 11, 0x2a, 18),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT19", DISP_IOMMU, 11, 0x2a, 19),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT20", DISP_IOMMU, 11, 0x2a, 20),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT21", DISP_IOMMU, 11, 0x2a, 21),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT22", DISP_IOMMU, 11, 0x2a, 22),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT23", DISP_IOMMU, 11, 0x2a, 23),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT24", DISP_IOMMU, 11, 0x2a, 24),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT25", DISP_IOMMU, 11, 0x2a, 25),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT26", DISP_IOMMU, 11, 0x2a, 26),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT27", DISP_IOMMU, 11, 0x2a, 27),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT28", DISP_IOMMU, 11, 0x2a, 28),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT29", DISP_IOMMU, 11, 0x2a, 29),
|
|
|
|
/* larb12 */
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT0", DISP_IOMMU, 12, 0x18, 0),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT1", DISP_IOMMU, 12, 0x18, 1),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT2", DISP_IOMMU, 12, 0x18, 2),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT3", DISP_IOMMU, 12, 0x18, 3),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT4", DISP_IOMMU, 12, 0x18, 4),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT5", DISP_IOMMU, 12, 0x18, 5),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT6", DISP_IOMMU, 12, 0x18, 6),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT7", DISP_IOMMU, 12, 0x18, 7),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT8", DISP_IOMMU, 12, 0x18, 8),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT9", DISP_IOMMU, 12, 0x18, 9),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT10", DISP_IOMMU, 12, 0x18, 10),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT11", DISP_IOMMU, 12, 0x18, 11),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT12", DISP_IOMMU, 12, 0x18, 12),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT13", DISP_IOMMU, 12, 0x18, 13),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT14", DISP_IOMMU, 12, 0x18, 14),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT15", DISP_IOMMU, 12, 0x18, 15),
|
|
|
|
/* larb13 */
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT0", DISP_IOMMU, 13, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT1", DISP_IOMMU, 13, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT2", DISP_IOMMU, 13, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT3", DISP_IOMMU, 13, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT4", DISP_IOMMU, 13, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT5", DISP_IOMMU, 13, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT6", DISP_IOMMU, 13, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT7", DISP_IOMMU, 13, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT8", DISP_IOMMU, 13, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT9", DISP_IOMMU, 13, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT10", DISP_IOMMU, 13, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT11", DISP_IOMMU, 13, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT12", DISP_IOMMU, 13, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT13", DISP_IOMMU, 13, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT14", DISP_IOMMU, 13, 0x30, 14),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT15", DISP_IOMMU, 13, 0x30, 15),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT16", DISP_IOMMU, 13, 0x30, 16),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT17", DISP_IOMMU, 13, 0x30, 17),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT18", DISP_IOMMU, 13, 0x30, 18),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT19", DISP_IOMMU, 13, 0x30, 19),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT20", DISP_IOMMU, 13, 0x30, 20),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT21", DISP_IOMMU, 13, 0x30, 21),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT22", DISP_IOMMU, 13, 0x30, 22),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT23", DISP_IOMMU, 13, 0x30, 23),
|
|
|
|
/* larb14 */
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT0", DISP_IOMMU, 14, 0x38, 0),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT1", DISP_IOMMU, 14, 0x38, 1),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT2", DISP_IOMMU, 14, 0x38, 2),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT3", DISP_IOMMU, 14, 0x38, 3),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT4", DISP_IOMMU, 14, 0x38, 4),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT5", DISP_IOMMU, 14, 0x38, 5),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT6", DISP_IOMMU, 14, 0x38, 6),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT7", DISP_IOMMU, 14, 0x38, 7),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT8", DISP_IOMMU, 14, 0x38, 8),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT9", DISP_IOMMU, 14, 0x38, 9),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT10", DISP_IOMMU, 14, 0x38, 10),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT11", DISP_IOMMU, 14, 0x38, 11),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT12", DISP_IOMMU, 14, 0x38, 12),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT13", DISP_IOMMU, 14, 0x38, 13),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT14", DISP_IOMMU, 14, 0x38, 14),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT15", DISP_IOMMU, 14, 0x38, 15),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT16", DISP_IOMMU, 14, 0x38, 16),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT17", DISP_IOMMU, 14, 0x38, 17),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT18", DISP_IOMMU, 14, 0x38, 18),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT19", DISP_IOMMU, 14, 0x38, 19),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT20", DISP_IOMMU, 14, 0x38, 20),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT21", DISP_IOMMU, 14, 0x38, 21),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT22", DISP_IOMMU, 14, 0x38, 22),
|
|
|
|
/* Larb15 */
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT0", DISP_IOMMU, 15, 0x19, 0),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT1", DISP_IOMMU, 15, 0x19, 1),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT2", DISP_IOMMU, 15, 0x19, 2),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT3", DISP_IOMMU, 15, 0x19, 3),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT4", DISP_IOMMU, 15, 0x19, 4),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT5", DISP_IOMMU, 15, 0x19, 5),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT6", DISP_IOMMU, 15, 0x19, 6),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT7", DISP_IOMMU, 15, 0x19, 7),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT8", DISP_IOMMU, 15, 0x19, 8),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT9", DISP_IOMMU, 15, 0x19, 9),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT10", DISP_IOMMU, 15, 0x19, 10),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT11", DISP_IOMMU, 15, 0x19, 11),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT12", DISP_IOMMU, 15, 0x19, 12),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT13", DISP_IOMMU, 15, 0x19, 13),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT14", DISP_IOMMU, 15, 0x19, 14),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT15", DISP_IOMMU, 15, 0x19, 15),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT16", DISP_IOMMU, 15, 0x19, 16),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT17", DISP_IOMMU, 15, 0x19, 17),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT18", DISP_IOMMU, 15, 0x19, 18),
|
|
|
|
/* larb16 */
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT0", DISP_IOMMU, 16, 0x3a, 0),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT1", DISP_IOMMU, 16, 0x3a, 1),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT2", DISP_IOMMU, 16, 0x3a, 2),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT3", DISP_IOMMU, 16, 0x3a, 3),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT4", DISP_IOMMU, 16, 0x3a, 4),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT5", DISP_IOMMU, 16, 0x3a, 5),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT6", DISP_IOMMU, 16, 0x3a, 6),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT7", DISP_IOMMU, 16, 0x3a, 7),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT8", DISP_IOMMU, 16, 0x3a, 8),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT9", DISP_IOMMU, 16, 0x3a, 9),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT10", DISP_IOMMU, 16, 0x3a, 10),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT11", DISP_IOMMU, 16, 0x3a, 11),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT12", DISP_IOMMU, 16, 0x3a, 12),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT13", DISP_IOMMU, 16, 0x3a, 13),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT14", DISP_IOMMU, 16, 0x3a, 14),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT15", DISP_IOMMU, 16, 0x3a, 15),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT16", DISP_IOMMU, 16, 0x3a, 16),
|
|
|
|
/* larb17 */
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT0", DISP_IOMMU, 17, 0x3b, 0),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT1", DISP_IOMMU, 17, 0x3b, 1),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT2", DISP_IOMMU, 17, 0x3b, 2),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT3", DISP_IOMMU, 17, 0x3b, 3),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT4", DISP_IOMMU, 17, 0x3b, 4),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT5", DISP_IOMMU, 17, 0x3b, 5),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT6", DISP_IOMMU, 17, 0x3b, 6),
|
|
|
|
/* larb19 */
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT0", DISP_IOMMU, 19, 0x3d, 0),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT1", DISP_IOMMU, 19, 0x3d, 1),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT2", DISP_IOMMU, 19, 0x3d, 2),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT3", DISP_IOMMU, 19, 0x3d, 3),
|
|
|
|
/* Larb22 */
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT0", DISP_IOMMU, 22, 0x1a, 0),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT1", DISP_IOMMU, 22, 0x1a, 1),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT2", DISP_IOMMU, 22, 0x1a, 2),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT3", DISP_IOMMU, 22, 0x1a, 3),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT4", DISP_IOMMU, 22, 0x1a, 4),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT5", DISP_IOMMU, 22, 0x1a, 5),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT6", DISP_IOMMU, 22, 0x1a, 6),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT7", DISP_IOMMU, 22, 0x1a, 7),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT8", DISP_IOMMU, 22, 0x1a, 8),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT9", DISP_IOMMU, 22, 0x1a, 9),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT10", DISP_IOMMU, 22, 0x1a, 10),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT11", DISP_IOMMU, 22, 0x1a, 11),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT12", DISP_IOMMU, 22, 0x1a, 12),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT13", DISP_IOMMU, 22, 0x1a, 13),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT14", DISP_IOMMU, 22, 0x1a, 14),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT15", DISP_IOMMU, 22, 0x1a, 15),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT16", DISP_IOMMU, 22, 0x1a, 16),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT17", DISP_IOMMU, 22, 0x1a, 17),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT18", DISP_IOMMU, 22, 0x1a, 18),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT19", DISP_IOMMU, 22, 0x1a, 19),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT20", DISP_IOMMU, 22, 0x1a, 20),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT21", DISP_IOMMU, 22, 0x1a, 21),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT22", DISP_IOMMU, 22, 0x1a, 22),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT23", DISP_IOMMU, 22, 0x1a, 23),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT24", DISP_IOMMU, 22, 0x1a, 24),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT25", DISP_IOMMU, 22, 0x1a, 25),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT26", DISP_IOMMU, 22, 0x1a, 26),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT27", DISP_IOMMU, 22, 0x1a, 27),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT28", DISP_IOMMU, 22, 0x1a, 28),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT29", DISP_IOMMU, 22, 0x1a, 29),
|
|
|
|
/* Larb23 */
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT0", DISP_IOMMU, 23, 0x2b, 0),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT1", DISP_IOMMU, 23, 0x2b, 1),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT2", DISP_IOMMU, 23, 0x2b, 2),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT3", DISP_IOMMU, 23, 0x2b, 3),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT4", DISP_IOMMU, 23, 0x2b, 4),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT5", DISP_IOMMU, 23, 0x2b, 5),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT6", DISP_IOMMU, 23, 0x2b, 6),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT7", DISP_IOMMU, 23, 0x2b, 7),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT8", DISP_IOMMU, 23, 0x2b, 8),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT9", DISP_IOMMU, 23, 0x2b, 9),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT10", DISP_IOMMU, 23, 0x2b, 10),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT11", DISP_IOMMU, 23, 0x2b, 11),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT12", DISP_IOMMU, 23, 0x2b, 12),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT13", DISP_IOMMU, 23, 0x2b, 13),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT14", DISP_IOMMU, 23, 0x2b, 14),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT15", DISP_IOMMU, 23, 0x2b, 15),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT16", DISP_IOMMU, 23, 0x2b, 16),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT17", DISP_IOMMU, 23, 0x2b, 17),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT18", DISP_IOMMU, 23, 0x2b, 18),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT19", DISP_IOMMU, 23, 0x2b, 19),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT20", DISP_IOMMU, 23, 0x2b, 20),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT21", DISP_IOMMU, 23, 0x2b, 21),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT22", DISP_IOMMU, 23, 0x2b, 22),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT23", DISP_IOMMU, 23, 0x2b, 23),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT24", DISP_IOMMU, 23, 0x2b, 24),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT25", DISP_IOMMU, 23, 0x2b, 25),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT26", DISP_IOMMU, 23, 0x2b, 26),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT27", DISP_IOMMU, 23, 0x2b, 27),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT28", DISP_IOMMU, 23, 0x2b, 28),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT29", DISP_IOMMU, 23, 0x2b, 29),
|
|
|
|
/* larb25 */
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT0", DISP_IOMMU, 25, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT1", DISP_IOMMU, 25, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT2", DISP_IOMMU, 25, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT3", DISP_IOMMU, 25, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT4", DISP_IOMMU, 25, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT5", DISP_IOMMU, 25, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT6", DISP_IOMMU, 25, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT7", DISP_IOMMU, 25, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT8", DISP_IOMMU, 25, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT9", DISP_IOMMU, 25, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT10", DISP_IOMMU, 25, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT11", DISP_IOMMU, 25, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT12", DISP_IOMMU, 25, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT13", DISP_IOMMU, 25, 0x31, 13),
|
|
|
|
/* larb26 */
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT0", DISP_IOMMU, 26, 0x39, 0),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT1", DISP_IOMMU, 26, 0x39, 1),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT2", DISP_IOMMU, 26, 0x39, 2),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT3", DISP_IOMMU, 26, 0x39, 3),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT4", DISP_IOMMU, 26, 0x39, 4),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT5", DISP_IOMMU, 26, 0x39, 5),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT6", DISP_IOMMU, 26, 0x39, 6),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT7", DISP_IOMMU, 26, 0x39, 7),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT8", DISP_IOMMU, 26, 0x39, 8),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT9", DISP_IOMMU, 26, 0x39, 9),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT10", DISP_IOMMU, 26, 0x39, 10),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT11", DISP_IOMMU, 26, 0x39, 11),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT12", DISP_IOMMU, 26, 0x39, 12),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT13", DISP_IOMMU, 26, 0x39, 13),
|
|
|
|
/* larb27 */
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT0", DISP_IOMMU, 27, 0x32, 0),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT1", DISP_IOMMU, 27, 0x32, 1),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT2", DISP_IOMMU, 27, 0x32, 2),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT3", DISP_IOMMU, 27, 0x32, 3),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT4", DISP_IOMMU, 27, 0x32, 4),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT5", DISP_IOMMU, 27, 0x32, 5),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT6", DISP_IOMMU, 27, 0x32, 6),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT7", DISP_IOMMU, 27, 0x32, 7),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT8", DISP_IOMMU, 27, 0x32, 8),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT9", DISP_IOMMU, 27, 0x32, 9),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT10", DISP_IOMMU, 27, 0x32, 10),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT11", DISP_IOMMU, 27, 0x32, 11),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT12", DISP_IOMMU, 27, 0x32, 12),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT13", DISP_IOMMU, 27, 0x32, 13),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT14", DISP_IOMMU, 27, 0x32, 14),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT15", DISP_IOMMU, 27, 0x32, 15),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT16", DISP_IOMMU, 27, 0x32, 16),
|
|
|
|
/* larb28 */
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT0", DISP_IOMMU, 28, 0x3c, 0),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT1", DISP_IOMMU, 28, 0x3c, 1),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT2", DISP_IOMMU, 28, 0x3c, 2),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT3", DISP_IOMMU, 28, 0x3c, 3),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT4", DISP_IOMMU, 28, 0x3c, 4),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT5", DISP_IOMMU, 28, 0x3c, 5),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT6", DISP_IOMMU, 28, 0x3c, 6),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT7", DISP_IOMMU, 28, 0x3c, 7),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT8", DISP_IOMMU, 28, 0x3c, 8),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT9", DISP_IOMMU, 28, 0x3c, 9),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT10", DISP_IOMMU, 28, 0x3c, 10),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT11", DISP_IOMMU, 28, 0x3c, 11),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT12", DISP_IOMMU, 28, 0x3c, 12),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT13", DISP_IOMMU, 28, 0x3c, 13),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT14", DISP_IOMMU, 28, 0x3c, 14),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT15", DISP_IOMMU, 28, 0x3c, 15),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT16", DISP_IOMMU, 28, 0x3c, 16),
|
|
|
|
/* larb29 */
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT0", DISP_IOMMU, 29, 0x33, 0),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT1", DISP_IOMMU, 29, 0x33, 1),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT2", DISP_IOMMU, 29, 0x33, 2),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT3", DISP_IOMMU, 29, 0x33, 3),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT4", DISP_IOMMU, 29, 0x33, 4),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT5", DISP_IOMMU, 29, 0x33, 5),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT6", DISP_IOMMU, 29, 0x33, 6),
|
|
|
|
/* larb30 */
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT0", DISP_IOMMU, 30, 0x34, 0),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT1", DISP_IOMMU, 30, 0x34, 1),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT2", DISP_IOMMU, 30, 0x34, 2),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT3", DISP_IOMMU, 30, 0x34, 3),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT4", DISP_IOMMU, 30, 0x34, 4),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT5", DISP_IOMMU, 30, 0x34, 5),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT6", DISP_IOMMU, 30, 0x34, 6),
|
|
|
|
/* Larb31 -- 2 */
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU0", DISP_IOMMU, 31, 0x3e, 0, CCU_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU1", DISP_IOMMU, 31, 0x3f, 1, CCU_FAKE),
|
|
|
|
/* Larb32 -- 3 */
|
|
MM_IOMMU_FAKE_PORT_INIT("VIDEO_uP", DISP_IOMMU, 32, 0x4, 0,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_D_M", DISP_IOMMU, 32, 0x4, 1,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_M_M", DISP_IOMMU, 32, 0x4, 2,
|
|
GCE_VIDEOUP_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6879[] = {
|
|
APU_IOMMU_PORT_INIT("APU_PORT0", 0, 0, 0, 0),
|
|
APU_IOMMU_PORT_INIT("APU_PORT1", 0, 0, 0, 1),
|
|
APU_IOMMU_PORT_INIT("APU_PORT2", 0, 0, 0, 2),
|
|
APU_IOMMU_PORT_INIT("APU_PORT3", 0, 0, 0, 3),
|
|
APU_IOMMU_PORT_INIT("APU_PORT4", 0, 0, 0, 4),
|
|
APU_IOMMU_PORT_INIT("APU_PORT5", 0, 0, 0, 5),
|
|
APU_IOMMU_PORT_INIT("APU_PORT6", 0, 0, 0, 6),
|
|
APU_IOMMU_PORT_INIT("APU_PORT9", 0, 0, 0, 9),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0xf)
|
|
};
|
|
|
|
static const struct mtk_iommu_port peri_port_mt6879[] = {
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT0", 0, 0, 0, 0),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT1", 0, 0, 0, 1),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT2", 0, 0, 0, 2),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT3", 0, 0, 0, 3),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT4", 0, 0, 0, 4),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT5", 1, 0, 0, 5),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT6", 2, 0, 0, 6),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT7", 2, 0, 0, 7),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT8", 2, 0, 0, 8),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT9", 2, 0, 0, 9),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT10", 2, 0, 0, 10),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT11", 2, 0, 0, 11),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT12", 2, 0, 0, 12),
|
|
PERI_IOMMU_PORT_INIT("PERI_PORT13", 2, 0, 0, 13),
|
|
|
|
PERI_IOMMU_PORT_INIT("PERI_UNKNOWN", 0, 0, 0, 0xf)
|
|
};
|
|
|
|
static const struct mtk_iommu_port mm_port_mt6895[] = {
|
|
/* larb0 */
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT0", DISP_IOMMU, 0, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT1", DISP_IOMMU, 0, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT2", DISP_IOMMU, 0, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT3", DISP_IOMMU, 0, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT4", DISP_IOMMU, 0, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT5", DISP_IOMMU, 0, 0x0, 5),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT6", DISP_IOMMU, 0, 0x0, 6),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT7", DISP_IOMMU, 0, 0x0, 7),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT8", DISP_IOMMU, 0, 0x0, 8),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT9", DISP_IOMMU, 0, 0x0, 9),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT10", DISP_IOMMU, 0, 0x0, 10),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT11", DISP_IOMMU, 0, 0x0, 11),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT12", DISP_IOMMU, 0, 0x0, 12),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT13", DISP_IOMMU, 0, 0x0, 13),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT14", DISP_IOMMU, 0, 0x0, 14),
|
|
MM_IOMMU_PORT_INIT("LARB0_PORT15", DISP_IOMMU, 0, 0x0, 15),
|
|
|
|
/* larb1 */
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT0", MDP_IOMMU, 1, 0x0, 0),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT1", MDP_IOMMU, 1, 0x0, 1),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT2", MDP_IOMMU, 1, 0x0, 2),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT3", MDP_IOMMU, 1, 0x0, 3),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT4", MDP_IOMMU, 1, 0x0, 4),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT5", MDP_IOMMU, 1, 0x0, 5),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT6", MDP_IOMMU, 1, 0x0, 6),
|
|
MM_IOMMU_PORT_INIT("LARB1_PORT7", MDP_IOMMU, 1, 0x0, 7),
|
|
|
|
/* larb2 */
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT0", DISP_IOMMU, 2, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT1", DISP_IOMMU, 2, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT2", DISP_IOMMU, 2, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT3", DISP_IOMMU, 2, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT4", DISP_IOMMU, 2, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT5", DISP_IOMMU, 2, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT6", DISP_IOMMU, 2, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT7", DISP_IOMMU, 2, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("LARB2_PORT8", DISP_IOMMU, 2, 0x10, 8),
|
|
|
|
/* larb3 */
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT0", MDP_IOMMU, 3, 0x10, 0),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT1", MDP_IOMMU, 3, 0x10, 1),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT2", MDP_IOMMU, 3, 0x10, 2),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT3", MDP_IOMMU, 3, 0x10, 3),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT4", MDP_IOMMU, 3, 0x10, 4),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT5", MDP_IOMMU, 3, 0x10, 5),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT6", MDP_IOMMU, 3, 0x10, 6),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT7", MDP_IOMMU, 3, 0x10, 7),
|
|
MM_IOMMU_PORT_INIT("LARB3_PORT8", MDP_IOMMU, 3, 0x10, 8),
|
|
|
|
/* larb4 */
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT0", MDP_IOMMU, 4, 0x18, 0),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT1", MDP_IOMMU, 4, 0x18, 1),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT2", MDP_IOMMU, 4, 0x18, 2),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT3", MDP_IOMMU, 4, 0x18, 3),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT4", MDP_IOMMU, 4, 0x18, 4),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT5", MDP_IOMMU, 4, 0x18, 5),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT6", MDP_IOMMU, 4, 0x18, 6),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT7", MDP_IOMMU, 4, 0x18, 7),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT8", MDP_IOMMU, 4, 0x18, 8),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT9", MDP_IOMMU, 4, 0x18, 9),
|
|
MM_IOMMU_PORT_INIT("LARB4_PORT10", MDP_IOMMU, 4, 0x18, 10),
|
|
|
|
/* larb5 */
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT0", DISP_IOMMU, 5, 0x18, 0),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT1", DISP_IOMMU, 5, 0x18, 1),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT2", DISP_IOMMU, 5, 0x18, 2),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT3", DISP_IOMMU, 5, 0x18, 3),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT4", DISP_IOMMU, 5, 0x18, 4),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT5", DISP_IOMMU, 5, 0x18, 5),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT6", DISP_IOMMU, 5, 0x18, 6),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT7", DISP_IOMMU, 5, 0x18, 7),
|
|
MM_IOMMU_PORT_INIT("LARB5_PORT8", DISP_IOMMU, 5, 0x18, 8),
|
|
|
|
/* larb6 */
|
|
MM_IOMMU_PORT_INIT("LARB6_PORT0", DISP_IOMMU, 6, 0x38, 0),
|
|
MM_IOMMU_PORT_INIT("LARB6_PORT1", DISP_IOMMU, 6, 0x38, 1),
|
|
MM_IOMMU_PORT_INIT("LARB6_PORT2", DISP_IOMMU, 6, 0x38, 2),
|
|
MM_IOMMU_PORT_INIT("LARB6_PORT3", DISP_IOMMU, 6, 0x38, 3),
|
|
|
|
/* larb7 */
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT0", DISP_IOMMU, 7, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT1", DISP_IOMMU, 7, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT2", DISP_IOMMU, 7, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT3", DISP_IOMMU, 7, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT4", DISP_IOMMU, 7, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT5", DISP_IOMMU, 7, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT6", DISP_IOMMU, 7, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT7", DISP_IOMMU, 7, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT8", DISP_IOMMU, 7, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT9", DISP_IOMMU, 7, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT10", DISP_IOMMU, 7, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT11", DISP_IOMMU, 7, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT12", DISP_IOMMU, 7, 0x20, 12),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT13", DISP_IOMMU, 7, 0x20, 13),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT14", DISP_IOMMU, 7, 0x20, 14),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT15", DISP_IOMMU, 7, 0x20, 15),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT16", DISP_IOMMU, 7, 0x20, 16),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT17", DISP_IOMMU, 7, 0x20, 17),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT18", DISP_IOMMU, 7, 0x20, 18),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT19", DISP_IOMMU, 7, 0x20, 19),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT20", DISP_IOMMU, 7, 0x20, 20),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT21", DISP_IOMMU, 7, 0x20, 21),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT22", DISP_IOMMU, 7, 0x20, 22),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT23", DISP_IOMMU, 7, 0x20, 23),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT24", DISP_IOMMU, 7, 0x20, 24),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT25", DISP_IOMMU, 7, 0x20, 25),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT26", DISP_IOMMU, 7, 0x20, 26),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT27", DISP_IOMMU, 7, 0x20, 27),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT28", DISP_IOMMU, 7, 0x20, 28),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT29", DISP_IOMMU, 7, 0x20, 29),
|
|
MM_IOMMU_PORT_INIT("LARB7_PORT30", DISP_IOMMU, 7, 0x20, 30),
|
|
|
|
/* larb8 */
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT0", MDP_IOMMU, 8, 0x20, 0),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT1", MDP_IOMMU, 8, 0x20, 1),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT2", MDP_IOMMU, 8, 0x20, 2),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT3", MDP_IOMMU, 8, 0x20, 3),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT4", MDP_IOMMU, 8, 0x20, 4),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT5", MDP_IOMMU, 8, 0x20, 5),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT6", MDP_IOMMU, 8, 0x20, 6),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT7", MDP_IOMMU, 8, 0x20, 7),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT8", MDP_IOMMU, 8, 0x20, 8),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT9", MDP_IOMMU, 8, 0x20, 9),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT10", MDP_IOMMU, 8, 0x20, 10),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT11", MDP_IOMMU, 8, 0x20, 11),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT12", MDP_IOMMU, 8, 0x20, 12),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT13", MDP_IOMMU, 8, 0x20, 13),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT14", MDP_IOMMU, 8, 0x20, 14),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT15", MDP_IOMMU, 8, 0x20, 15),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT16", MDP_IOMMU, 8, 0x20, 16),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT17", MDP_IOMMU, 8, 0x20, 17),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT18", MDP_IOMMU, 8, 0x20, 18),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT19", MDP_IOMMU, 8, 0x20, 19),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT20", MDP_IOMMU, 8, 0x20, 20),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT21", MDP_IOMMU, 8, 0x20, 21),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT22", MDP_IOMMU, 8, 0x20, 22),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT23", MDP_IOMMU, 8, 0x20, 23),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT24", MDP_IOMMU, 8, 0x20, 24),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT25", MDP_IOMMU, 8, 0x20, 25),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT26", MDP_IOMMU, 8, 0x20, 26),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT27", MDP_IOMMU, 8, 0x20, 27),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT28", MDP_IOMMU, 8, 0x20, 28),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT29", MDP_IOMMU, 8, 0x20, 29),
|
|
MM_IOMMU_PORT_INIT("LARB8_PORT30", MDP_IOMMU, 8, 0x20, 30),
|
|
|
|
/* larb9 */
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT0", DISP_IOMMU, 9, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT1", DISP_IOMMU, 9, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT2", DISP_IOMMU, 9, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT3", DISP_IOMMU, 9, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT4", DISP_IOMMU, 9, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT5", DISP_IOMMU, 9, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT6", DISP_IOMMU, 9, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT7", DISP_IOMMU, 9, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT8", DISP_IOMMU, 9, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT9", DISP_IOMMU, 9, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT10", DISP_IOMMU, 9, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT11", DISP_IOMMU, 9, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT12", DISP_IOMMU, 9, 0x28, 12),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT13", DISP_IOMMU, 9, 0x28, 13),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT14", DISP_IOMMU, 9, 0x28, 14),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT15", DISP_IOMMU, 9, 0x28, 15),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT16", DISP_IOMMU, 9, 0x28, 16),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT17", DISP_IOMMU, 9, 0x28, 17),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT18", DISP_IOMMU, 9, 0x28, 18),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT19", DISP_IOMMU, 9, 0x28, 19),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT20", DISP_IOMMU, 9, 0x28, 20),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT21", DISP_IOMMU, 9, 0x28, 21),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT22", DISP_IOMMU, 9, 0x28, 22),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT23", DISP_IOMMU, 9, 0x28, 23),
|
|
MM_IOMMU_PORT_INIT("LARB9_PORT24", DISP_IOMMU, 9, 0x28, 24),
|
|
|
|
/* larb10 */
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT0", DISP_IOMMU, 10, 0x29, 0),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT1", DISP_IOMMU, 10, 0x29, 1),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT2", DISP_IOMMU, 10, 0x29, 2),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT3", DISP_IOMMU, 10, 0x29, 3),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT4", DISP_IOMMU, 10, 0x29, 4),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT5", DISP_IOMMU, 10, 0x29, 5),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT6", DISP_IOMMU, 10, 0x29, 6),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT7", DISP_IOMMU, 10, 0x29, 7),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT8", DISP_IOMMU, 10, 0x29, 8),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT9", DISP_IOMMU, 10, 0x29, 9),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT10", DISP_IOMMU, 10, 0x29, 10),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT11", DISP_IOMMU, 10, 0x29, 11),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT12", DISP_IOMMU, 10, 0x29, 12),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT13", DISP_IOMMU, 10, 0x29, 13),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT14", DISP_IOMMU, 10, 0x29, 14),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT15", DISP_IOMMU, 10, 0x29, 15),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT16", DISP_IOMMU, 10, 0x29, 16),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT17", DISP_IOMMU, 10, 0x29, 17),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT18", DISP_IOMMU, 10, 0x29, 18),
|
|
MM_IOMMU_PORT_INIT("LARB10_PORT19", DISP_IOMMU, 10, 0x29, 19),
|
|
|
|
/* larb11--Larb11A */
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT0", DISP_IOMMU, 11, 0x2A, 0),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT1", DISP_IOMMU, 11, 0x2A, 1),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT2", DISP_IOMMU, 11, 0x2A, 2),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT3", DISP_IOMMU, 11, 0x2A, 3),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT4", DISP_IOMMU, 11, 0x2A, 4),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT5", DISP_IOMMU, 11, 0x2A, 5),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT6", DISP_IOMMU, 11, 0x2A, 6),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT7", DISP_IOMMU, 11, 0x2A, 7),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT8", DISP_IOMMU, 11, 0x2A, 8),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT9", DISP_IOMMU, 11, 0x2A, 9),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT10", DISP_IOMMU, 11, 0x2A, 10),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT11", DISP_IOMMU, 11, 0x2A, 11),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT12", DISP_IOMMU, 11, 0x2A, 12),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT13", DISP_IOMMU, 11, 0x2A, 13),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT14", DISP_IOMMU, 11, 0x2A, 14),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT15", DISP_IOMMU, 11, 0x2A, 15),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT16", DISP_IOMMU, 11, 0x2A, 16),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT17", DISP_IOMMU, 11, 0x2A, 17),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT18", DISP_IOMMU, 11, 0x2A, 18),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT19", DISP_IOMMU, 11, 0x2A, 19),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT20", DISP_IOMMU, 11, 0x2A, 20),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT21", DISP_IOMMU, 11, 0x2A, 21),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT22", DISP_IOMMU, 11, 0x2A, 22),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT23", DISP_IOMMU, 11, 0x2A, 23),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT24", DISP_IOMMU, 11, 0x2A, 24),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT25", DISP_IOMMU, 11, 0x2A, 25),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT26", DISP_IOMMU, 11, 0x2A, 26),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT27", DISP_IOMMU, 11, 0x2A, 27),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT28", DISP_IOMMU, 11, 0x2A, 28),
|
|
MM_IOMMU_PORT_INIT("LARB11_PORT29", DISP_IOMMU, 11, 0x2A, 29),
|
|
|
|
/* larb12 */
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT0", MDP_IOMMU, 12, 0x28, 0),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT1", MDP_IOMMU, 12, 0x28, 1),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT2", MDP_IOMMU, 12, 0x28, 2),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT3", MDP_IOMMU, 12, 0x28, 3),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT4", MDP_IOMMU, 12, 0x28, 4),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT5", MDP_IOMMU, 12, 0x28, 5),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT6", MDP_IOMMU, 12, 0x28, 6),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT7", MDP_IOMMU, 12, 0x28, 7),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT8", MDP_IOMMU, 12, 0x28, 8),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT9", MDP_IOMMU, 12, 0x28, 9),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT10", MDP_IOMMU, 12, 0x28, 10),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT11", MDP_IOMMU, 12, 0x28, 11),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT12", MDP_IOMMU, 12, 0x28, 12),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT13", MDP_IOMMU, 12, 0x28, 13),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT14", MDP_IOMMU, 12, 0x28, 14),
|
|
MM_IOMMU_PORT_INIT("LARB12_PORT15", MDP_IOMMU, 12, 0x28, 15),
|
|
|
|
/* larb13 */
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT0", DISP_IOMMU, 13, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT1", DISP_IOMMU, 13, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT2", DISP_IOMMU, 13, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT3", DISP_IOMMU, 13, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT4", DISP_IOMMU, 13, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT5", DISP_IOMMU, 13, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT6", DISP_IOMMU, 13, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT7", DISP_IOMMU, 13, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT8", DISP_IOMMU, 13, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT9", DISP_IOMMU, 13, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT10", DISP_IOMMU, 13, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT11", DISP_IOMMU, 13, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT12", DISP_IOMMU, 13, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT13", DISP_IOMMU, 13, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT14", DISP_IOMMU, 13, 0x30, 14),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT15", DISP_IOMMU, 13, 0x30, 15),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT16", DISP_IOMMU, 13, 0x30, 16),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT17", DISP_IOMMU, 13, 0x30, 17),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT18", DISP_IOMMU, 13, 0x30, 18),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT19", DISP_IOMMU, 13, 0x30, 19),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT20", DISP_IOMMU, 13, 0x30, 20),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT21", DISP_IOMMU, 13, 0x30, 21),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT22", DISP_IOMMU, 13, 0x30, 22),
|
|
MM_IOMMU_PORT_INIT("LARB13_PORT23", DISP_IOMMU, 13, 0x30, 23),
|
|
|
|
/* larb14 */
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT0", MDP_IOMMU, 14, 0x30, 0),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT1", MDP_IOMMU, 14, 0x30, 1),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT2", MDP_IOMMU, 14, 0x30, 2),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT3", MDP_IOMMU, 14, 0x30, 3),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT4", MDP_IOMMU, 14, 0x30, 4),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT5", MDP_IOMMU, 14, 0x30, 5),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT6", MDP_IOMMU, 14, 0x30, 6),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT7", MDP_IOMMU, 14, 0x30, 7),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT8", MDP_IOMMU, 14, 0x30, 8),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT9", MDP_IOMMU, 14, 0x30, 9),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT10", MDP_IOMMU, 14, 0x30, 10),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT11", MDP_IOMMU, 14, 0x30, 11),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT12", MDP_IOMMU, 14, 0x30, 12),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT13", MDP_IOMMU, 14, 0x30, 13),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT14", MDP_IOMMU, 14, 0x30, 14),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT15", MDP_IOMMU, 14, 0x30, 15),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT16", MDP_IOMMU, 14, 0x30, 16),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT17", MDP_IOMMU, 14, 0x30, 17),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT18", MDP_IOMMU, 14, 0x30, 18),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT19", MDP_IOMMU, 14, 0x30, 19),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT20", MDP_IOMMU, 14, 0x30, 20),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT21", MDP_IOMMU, 14, 0x30, 21),
|
|
MM_IOMMU_PORT_INIT("LARB14_PORT22", MDP_IOMMU, 14, 0x30, 22),
|
|
|
|
/* larb15 */
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT0", MDP_IOMMU, 15, 0x29, 0),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT1", MDP_IOMMU, 15, 0x29, 1),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT2", MDP_IOMMU, 15, 0x29, 2),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT3", MDP_IOMMU, 15, 0x29, 3),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT4", MDP_IOMMU, 15, 0x29, 4),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT5", MDP_IOMMU, 15, 0x29, 5),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT6", MDP_IOMMU, 15, 0x29, 6),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT7", MDP_IOMMU, 15, 0x29, 7),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT8", MDP_IOMMU, 15, 0x29, 8),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT9", MDP_IOMMU, 15, 0x29, 9),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT10", MDP_IOMMU, 15, 0x29, 10),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT11", MDP_IOMMU, 15, 0x29, 11),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT12", MDP_IOMMU, 15, 0x29, 12),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT13", MDP_IOMMU, 15, 0x29, 13),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT14", MDP_IOMMU, 15, 0x29, 14),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT15", MDP_IOMMU, 15, 0x29, 15),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT16", MDP_IOMMU, 15, 0x29, 16),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT17", MDP_IOMMU, 15, 0x29, 17),
|
|
MM_IOMMU_PORT_INIT("LARB15_PORT18", MDP_IOMMU, 15, 0x29, 18),
|
|
|
|
/* larb16--larb16A */
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT0", MDP_IOMMU, 16, 0x32, 0),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT1", MDP_IOMMU, 16, 0x32, 1),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT2", MDP_IOMMU, 16, 0x32, 2),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT3", MDP_IOMMU, 16, 0x32, 3),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT4", MDP_IOMMU, 16, 0x32, 4),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT5", MDP_IOMMU, 16, 0x32, 5),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT6", MDP_IOMMU, 16, 0x32, 6),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT7", MDP_IOMMU, 16, 0x32, 7),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT8", MDP_IOMMU, 16, 0x32, 8),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT9", MDP_IOMMU, 16, 0x32, 9),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT10", MDP_IOMMU, 16, 0x32, 10),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT11", MDP_IOMMU, 16, 0x32, 11),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT12", MDP_IOMMU, 16, 0x32, 12),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT13", MDP_IOMMU, 16, 0x32, 13),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT14", MDP_IOMMU, 16, 0x32, 14),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT15", MDP_IOMMU, 16, 0x32, 15),
|
|
MM_IOMMU_PORT_INIT("LARB16_PORT16", MDP_IOMMU, 16, 0x32, 16),
|
|
|
|
/* larb17--larb17A */
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT0", MDP_IOMMU, 17, 0x33, 0),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT1", MDP_IOMMU, 17, 0x33, 1),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT2", MDP_IOMMU, 17, 0x33, 2),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT3", MDP_IOMMU, 17, 0x33, 3),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT4", MDP_IOMMU, 17, 0x33, 4),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT5", MDP_IOMMU, 17, 0x33, 5),
|
|
MM_IOMMU_PORT_INIT("LARB17_PORT6", MDP_IOMMU, 17, 0x33, 6),
|
|
|
|
/* larb18 */
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT0", MDP_IOMMU, 18, 0x2B, 0),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT1", MDP_IOMMU, 18, 0x2B, 1),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT2", MDP_IOMMU, 18, 0x2B, 2),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT3", MDP_IOMMU, 18, 0x2B, 3),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT4", MDP_IOMMU, 18, 0x2B, 4),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT5", MDP_IOMMU, 18, 0x2B, 5),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT6", MDP_IOMMU, 18, 0x2B, 6),
|
|
MM_IOMMU_PORT_INIT("LARB18_PORT7", MDP_IOMMU, 18, 0x2B, 7),
|
|
|
|
/* larb19 */
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT0", MDP_IOMMU, 19, 0x35, 0),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT1", MDP_IOMMU, 19, 0x35, 1),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT2", MDP_IOMMU, 19, 0x35, 2),
|
|
MM_IOMMU_PORT_INIT("LARB19_PORT3", MDP_IOMMU, 19, 0x35, 3),
|
|
|
|
/* larb20 */
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT0", MDP_IOMMU, 20, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT1", MDP_IOMMU, 20, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT2", MDP_IOMMU, 20, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT3", MDP_IOMMU, 20, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT4", MDP_IOMMU, 20, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT5", MDP_IOMMU, 20, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT6", MDP_IOMMU, 20, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT7", MDP_IOMMU, 20, 0x8, 7),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT8", MDP_IOMMU, 20, 0x8, 8),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT9", MDP_IOMMU, 20, 0x8, 9),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT10", MDP_IOMMU, 20, 0x8, 10),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT11", MDP_IOMMU, 20, 0x8, 11),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT12", MDP_IOMMU, 20, 0x8, 12),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT13", MDP_IOMMU, 20, 0x8, 13),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT14", MDP_IOMMU, 20, 0x8, 14),
|
|
MM_IOMMU_PORT_INIT("LARB20_PORT15", MDP_IOMMU, 20, 0x8, 15),
|
|
|
|
/* larb21 */
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT0", DISP_IOMMU, 21, 0x8, 0),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT1", DISP_IOMMU, 21, 0x8, 1),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT2", DISP_IOMMU, 21, 0x8, 2),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT3", DISP_IOMMU, 21, 0x8, 3),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT4", DISP_IOMMU, 21, 0x8, 4),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT5", DISP_IOMMU, 21, 0x8, 5),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT6", DISP_IOMMU, 21, 0x8, 6),
|
|
MM_IOMMU_PORT_INIT("LARB21_PORT7", DISP_IOMMU, 21, 0x8, 7),
|
|
|
|
/* larb22--Larb11B */
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT0", MDP_IOMMU, 22, 0x2A, 0),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT1", MDP_IOMMU, 22, 0x2A, 1),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT2", MDP_IOMMU, 22, 0x2A, 2),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT3", MDP_IOMMU, 22, 0x2A, 3),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT4", MDP_IOMMU, 22, 0x2A, 4),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT5", MDP_IOMMU, 22, 0x2A, 5),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT6", MDP_IOMMU, 22, 0x2A, 6),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT7", MDP_IOMMU, 22, 0x2A, 7),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT8", MDP_IOMMU, 22, 0x2A, 8),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT9", MDP_IOMMU, 22, 0x2A, 9),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT10", MDP_IOMMU, 22, 0x2A, 10),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT11", MDP_IOMMU, 22, 0x2A, 11),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT12", MDP_IOMMU, 22, 0x2A, 12),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT13", MDP_IOMMU, 22, 0x2A, 13),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT14", MDP_IOMMU, 22, 0x2A, 14),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT15", MDP_IOMMU, 22, 0x2A, 15),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT16", MDP_IOMMU, 22, 0x2A, 16),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT17", MDP_IOMMU, 22, 0x2A, 17),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT18", MDP_IOMMU, 22, 0x2A, 18),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT19", MDP_IOMMU, 22, 0x2A, 19),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT20", MDP_IOMMU, 22, 0x2A, 20),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT21", MDP_IOMMU, 22, 0x2A, 21),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT22", MDP_IOMMU, 22, 0x2A, 22),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT23", MDP_IOMMU, 22, 0x2A, 23),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT24", MDP_IOMMU, 22, 0x2A, 24),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT25", MDP_IOMMU, 22, 0x2A, 25),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT26", MDP_IOMMU, 22, 0x2A, 26),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT27", MDP_IOMMU, 22, 0x2A, 27),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT28", MDP_IOMMU, 22, 0x2A, 28),
|
|
MM_IOMMU_PORT_INIT("LARB22_PORT29", MDP_IOMMU, 22, 0x2A, 29),
|
|
|
|
/* larb23--Larb11C */
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT0", DISP_IOMMU, 23, 0x2B, 0),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT1", DISP_IOMMU, 23, 0x2B, 1),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT2", DISP_IOMMU, 23, 0x2B, 2),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT3", DISP_IOMMU, 23, 0x2B, 3),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT4", DISP_IOMMU, 23, 0x2B, 4),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT5", DISP_IOMMU, 23, 0x2B, 5),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT6", DISP_IOMMU, 23, 0x2B, 6),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT7", DISP_IOMMU, 23, 0x2B, 7),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT8", DISP_IOMMU, 23, 0x2B, 8),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT9", DISP_IOMMU, 23, 0x2B, 9),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT10", DISP_IOMMU, 23, 0x2B, 10),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT11", DISP_IOMMU, 23, 0x2B, 11),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT12", DISP_IOMMU, 23, 0x2B, 12),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT13", DISP_IOMMU, 23, 0x2B, 13),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT14", DISP_IOMMU, 23, 0x2B, 14),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT15", DISP_IOMMU, 23, 0x2B, 15),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT16", DISP_IOMMU, 23, 0x2B, 16),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT17", DISP_IOMMU, 23, 0x2B, 17),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT18", DISP_IOMMU, 23, 0x2B, 18),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT19", DISP_IOMMU, 23, 0x2B, 19),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT20", DISP_IOMMU, 23, 0x2B, 20),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT21", DISP_IOMMU, 23, 0x2B, 21),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT22", DISP_IOMMU, 23, 0x2B, 22),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT23", DISP_IOMMU, 23, 0x2B, 23),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT24", DISP_IOMMU, 23, 0x2B, 24),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT25", DISP_IOMMU, 23, 0x2B, 25),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT26", DISP_IOMMU, 23, 0x2B, 26),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT27", DISP_IOMMU, 23, 0x2B, 27),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT28", DISP_IOMMU, 23, 0x2B, 28),
|
|
MM_IOMMU_PORT_INIT("LARB23_PORT29", DISP_IOMMU, 23, 0x2B, 29),
|
|
|
|
/* larb24--dummy */
|
|
|
|
/* larb25 */
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT0", DISP_IOMMU, 25, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT1", DISP_IOMMU, 25, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT2", DISP_IOMMU, 25, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT3", DISP_IOMMU, 25, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT4", DISP_IOMMU, 25, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT5", DISP_IOMMU, 25, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT6", DISP_IOMMU, 25, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT7", DISP_IOMMU, 25, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT8", DISP_IOMMU, 25, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT9", DISP_IOMMU, 25, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT10", DISP_IOMMU, 25, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT11", DISP_IOMMU, 25, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT12", DISP_IOMMU, 25, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("LARB25_PORT13", DISP_IOMMU, 25, 0x31, 13),
|
|
|
|
/* larb26 */
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT0", MDP_IOMMU, 26, 0x31, 0),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT1", MDP_IOMMU, 26, 0x31, 1),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT2", MDP_IOMMU, 26, 0x31, 2),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT3", MDP_IOMMU, 26, 0x31, 3),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT4", MDP_IOMMU, 26, 0x31, 4),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT5", MDP_IOMMU, 26, 0x31, 5),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT6", MDP_IOMMU, 26, 0x31, 6),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT7", MDP_IOMMU, 26, 0x31, 7),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT8", MDP_IOMMU, 26, 0x31, 8),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT9", MDP_IOMMU, 26, 0x31, 9),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT10", MDP_IOMMU, 26, 0x31, 10),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT11", MDP_IOMMU, 26, 0x31, 11),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT12", MDP_IOMMU, 26, 0x31, 12),
|
|
MM_IOMMU_PORT_INIT("LARB26_PORT13", MDP_IOMMU, 26, 0x31, 13),
|
|
|
|
/* larb27--larb16B */
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT0", DISP_IOMMU, 27, 0x32, 0),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT1", DISP_IOMMU, 27, 0x32, 1),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT2", DISP_IOMMU, 27, 0x32, 2),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT3", DISP_IOMMU, 27, 0x32, 3),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT4", DISP_IOMMU, 27, 0x32, 4),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT5", DISP_IOMMU, 27, 0x32, 5),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT6", DISP_IOMMU, 27, 0x32, 6),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT7", DISP_IOMMU, 27, 0x32, 7),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT8", DISP_IOMMU, 27, 0x32, 8),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT9", DISP_IOMMU, 27, 0x32, 9),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT10", DISP_IOMMU, 27, 0x32, 10),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT11", DISP_IOMMU, 27, 0x32, 11),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT12", DISP_IOMMU, 27, 0x32, 12),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT13", DISP_IOMMU, 27, 0x32, 13),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT14", DISP_IOMMU, 27, 0x32, 14),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT15", DISP_IOMMU, 27, 0x32, 15),
|
|
MM_IOMMU_PORT_INIT("LARB27_PORT16", DISP_IOMMU, 27, 0x32, 16),
|
|
|
|
/* larb28--larb16C */
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT0", MDP_IOMMU, 28, 0x34, 0),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT1", MDP_IOMMU, 28, 0x34, 1),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT2", MDP_IOMMU, 28, 0x34, 2),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT3", MDP_IOMMU, 28, 0x34, 3),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT4", MDP_IOMMU, 28, 0x34, 4),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT5", MDP_IOMMU, 28, 0x34, 5),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT6", MDP_IOMMU, 28, 0x34, 6),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT7", MDP_IOMMU, 28, 0x34, 7),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT8", MDP_IOMMU, 28, 0x34, 8),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT9", MDP_IOMMU, 28, 0x34, 9),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT10", MDP_IOMMU, 28, 0x34, 10),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT11", MDP_IOMMU, 28, 0x34, 11),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT12", MDP_IOMMU, 28, 0x34, 12),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT13", MDP_IOMMU, 28, 0x34, 13),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT14", MDP_IOMMU, 28, 0x34, 14),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT15", MDP_IOMMU, 28, 0x34, 15),
|
|
MM_IOMMU_PORT_INIT("LARB28_PORT16", MDP_IOMMU, 28, 0x34, 16),
|
|
|
|
/* larb29--larb17B */
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT0", DISP_IOMMU, 29, 0x33, 0),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT1", DISP_IOMMU, 29, 0x33, 1),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT2", DISP_IOMMU, 29, 0x33, 2),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT3", DISP_IOMMU, 29, 0x33, 3),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT4", DISP_IOMMU, 29, 0x33, 4),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT5", DISP_IOMMU, 29, 0x33, 5),
|
|
MM_IOMMU_PORT_INIT("LARB29_PORT6", DISP_IOMMU, 29, 0x33, 6),
|
|
|
|
/* larb30--larb17C */
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT0", DISP_IOMMU, 30, 0x34, 0),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT1", DISP_IOMMU, 30, 0x34, 1),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT2", DISP_IOMMU, 30, 0x34, 2),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT3", DISP_IOMMU, 30, 0x34, 3),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT4", DISP_IOMMU, 30, 0x34, 4),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT5", DISP_IOMMU, 30, 0x34, 5),
|
|
MM_IOMMU_PORT_INIT("LARB30_PORT6", DISP_IOMMU, 30, 0x34, 6),
|
|
|
|
/* larb31--fake */
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU0", MDP_IOMMU, 31, 0x36, 0, CCU_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("CCU1", MDP_IOMMU, 31, 0x37, 1, CCU_FAKE),
|
|
|
|
/* larb32--fake */
|
|
MM_IOMMU_FAKE_PORT_INIT("VIDEO_uP", MDP_IOMMU, 32, 0x7, 0,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_D_M", MDP_IOMMU, 32, 0x7, 1,
|
|
GCE_VIDEOUP_FAKE),
|
|
MM_IOMMU_FAKE_PORT_INIT("GCE_M_M", MDP_IOMMU, 32, 0x7, 2,
|
|
GCE_VIDEOUP_FAKE),
|
|
|
|
MM_IOMMU_PORT_INIT("MM_UNKNOWN", 0, 0, 0, 0)
|
|
};
|
|
|
|
static const struct mtk_iommu_port apu_port_mt6895[] = {
|
|
/* APU0 */
|
|
APU_IOMMU_PORT_INIT("APU0_PORT0", APU_IOMMU0, 0, 0, 0),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT1", APU_IOMMU0, 0, 0, 1),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT2", APU_IOMMU0, 0, 0, 2),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT3", APU_IOMMU0, 0, 0, 3),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT4", APU_IOMMU0, 0, 0, 4),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT5", APU_IOMMU0, 0, 0, 5),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT6", APU_IOMMU0, 0, 0, 6),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT7", APU_IOMMU0, 0, 0, 7),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT8", APU_IOMMU0, 0, 0, 8),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT9", APU_IOMMU0, 0, 0, 9),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT10", APU_IOMMU0, 0, 0, 10),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT11", APU_IOMMU0, 0, 0, 11),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT12", APU_IOMMU0, 0, 0, 12),
|
|
APU_IOMMU_PORT_INIT("APU0_PORT13", APU_IOMMU0, 0, 0, 13),
|
|
|
|
/* APU1 */
|
|
APU_IOMMU_PORT_INIT("APU1_PORT0", APU_IOMMU1, 1, 0, 0),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT1", APU_IOMMU1, 1, 0, 1),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT2", APU_IOMMU1, 1, 0, 2),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT3", APU_IOMMU1, 1, 0, 3),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT4", APU_IOMMU1, 1, 0, 4),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT5", APU_IOMMU1, 1, 0, 5),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT6", APU_IOMMU1, 1, 0, 6),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT7", APU_IOMMU1, 1, 0, 7),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT8", APU_IOMMU1, 1, 0, 8),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT9", APU_IOMMU1, 1, 0, 9),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT10", APU_IOMMU1, 1, 0, 10),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT11", APU_IOMMU1, 1, 0, 11),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT12", APU_IOMMU1, 1, 0, 12),
|
|
APU_IOMMU_PORT_INIT("APU1_PORT13", APU_IOMMU1, 1, 0, 13),
|
|
|
|
APU_IOMMU_PORT_INIT("APU_UNKNOWN", 0, 0, 0, 0x1f)
|
|
};
|
|
|
|
static const struct mau_config_info mau_config_default[] = {
|
|
/* Monitor each IOMMU input IOVA<4K and output PA=0 */
|
|
MAU_CONFIG_INIT(0, 0, 0, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 0, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 0, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 0, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 1, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 1, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 1, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 0, 1, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
|
|
MAU_CONFIG_INIT(0, 1, 0, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 0, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 0, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 0, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 1, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 1, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 1, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(0, 1, 1, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
|
|
MAU_CONFIG_INIT(1, 0, 0, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 0, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 0, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 0, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 1, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 1, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 1, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 0, 1, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
|
|
MAU_CONFIG_INIT(1, 1, 0, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 0, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 0, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 0, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 1, 0, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x0, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 1, 1, 0x0, (SZ_4K - 1),
|
|
0xffffffff, 0xffffffff, 0x1, 0x1, 0x0, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 1, 2, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x0, 0x0, 0x1, 0x0, 0x0),
|
|
MAU_CONFIG_INIT(1, 1, 1, 3, 0x0, 0x1,
|
|
0xffffffff, 0xffffffff, 0x1, 0x0, 0x1, 0x0, 0x0),
|
|
};
|
|
|
|
/**********iommu trace**********/
|
|
#define IOMMU_MAX_EVENT_COUNT 8000
|
|
|
|
#define iommu_dump(file, fmt, args...) \
|
|
do {\
|
|
if (file)\
|
|
seq_printf(file, fmt, ##args);\
|
|
else\
|
|
pr_info(fmt, ##args);\
|
|
} while (0)
|
|
|
|
enum IOMMU_PROFILE_TYPE {
|
|
IOMMU_ALLOC = 0,
|
|
IOMMU_FREE,
|
|
IOMMU_MAP,
|
|
IOMMU_UNMAP,
|
|
IOMMU_SYNC,
|
|
IOMMU_UNSYNC,
|
|
IOMMU_SUSPEND,
|
|
IOMMU_RESUME,
|
|
IOMMU_EVENT_MAX,
|
|
};
|
|
|
|
struct iommu_event_mgr_t {
|
|
char name[11];
|
|
unsigned int dump_trace;
|
|
unsigned int dump_log;
|
|
};
|
|
|
|
static struct iommu_event_mgr_t event_mgr[IOMMU_EVENT_MAX];
|
|
|
|
struct iommu_event_t {
|
|
unsigned int event_id;
|
|
unsigned int time_low;
|
|
unsigned int time_high;
|
|
unsigned long data1;
|
|
unsigned long data2;
|
|
unsigned long data3;
|
|
struct device *dev;
|
|
};
|
|
|
|
struct iommu_global_t {
|
|
unsigned int enable;
|
|
unsigned int dump_enable;
|
|
unsigned int start;
|
|
unsigned int write_pointer;
|
|
spinlock_t lock;
|
|
struct iommu_event_t *record;
|
|
};
|
|
|
|
static struct iommu_global_t iommu_globals;
|
|
|
|
#define IOVA_DUMP_TOP_MAX (10)
|
|
|
|
struct iova_count_info {
|
|
u32 tab_id;
|
|
u32 dom_id;
|
|
struct device *dev;
|
|
u64 size;
|
|
u32 count;
|
|
struct list_head list_node;
|
|
};
|
|
|
|
struct iova_count_list {
|
|
spinlock_t lock;
|
|
struct list_head head;
|
|
};
|
|
|
|
static struct iova_count_list count_list = {};
|
|
|
|
static void mtk_iommu_iova_trace(int event, dma_addr_t iova, size_t size,
|
|
u32 tab_id, struct device *dev);
|
|
static void mtk_iommu_iova_alloc_dump_top(struct seq_file *s,
|
|
struct device *dev);
|
|
static void mtk_iommu_iova_alloc_dump(struct seq_file *s, struct device *dev);
|
|
static void mtk_iommu_iova_map_dump(struct seq_file *s, u64 iova, u32 tab_id);
|
|
|
|
struct iova_map_info {
|
|
int tab_id;
|
|
u64 iova;
|
|
u64 time_high;
|
|
u64 time_low;
|
|
size_t size;
|
|
struct list_head list_node;
|
|
};
|
|
|
|
struct iova_map_list {
|
|
atomic_t init_flag;
|
|
spinlock_t lock;
|
|
struct list_head head[MTK_IOVA_SPACE_NUM];
|
|
};
|
|
|
|
static struct iova_map_list map_list = {.init_flag = ATOMIC_INIT(0)};
|
|
|
|
void mtk_iova_map(int tab_id, u64 iova, size_t size)
|
|
{
|
|
u32 id = (iova >> 32);
|
|
unsigned long flags;
|
|
struct iova_map_info *iova_buf;
|
|
|
|
if (id >= MTK_IOVA_SPACE_NUM) {
|
|
pr_err("out of iova space: 0x%llx\n", iova);
|
|
return;
|
|
}
|
|
|
|
iova_buf = kzalloc(sizeof(*iova_buf), GFP_ATOMIC);
|
|
if (!iova_buf)
|
|
return;
|
|
|
|
iova_buf->time_high = sched_clock();
|
|
do_div(iova_buf->time_high, 1000);
|
|
iova_buf->time_low = do_div(iova_buf->time_high, 1000000);
|
|
iova_buf->tab_id = tab_id;
|
|
iova_buf->iova = iova;
|
|
iova_buf->size = size;
|
|
spin_lock_irqsave(&map_list.lock, flags);
|
|
list_add(&iova_buf->list_node, &map_list.head[id]);
|
|
spin_unlock_irqrestore(&map_list.lock, flags);
|
|
|
|
mtk_iommu_iova_trace(IOMMU_MAP, iova, size, tab_id, NULL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iova_map);
|
|
|
|
void mtk_iova_unmap(int tab_id, u64 iova, size_t size)
|
|
{
|
|
u32 id = (iova >> 32);
|
|
u64 start_t, end_t;
|
|
size_t total = 0;
|
|
unsigned long flags;
|
|
struct iova_map_info *plist;
|
|
struct iova_map_info *tmp_plist;
|
|
|
|
if (id >= MTK_IOVA_SPACE_NUM) {
|
|
pr_err("out of iova space: 0x%llx\n", iova);
|
|
return;
|
|
}
|
|
|
|
spin_lock_irqsave(&map_list.lock, flags);
|
|
start_t = sched_clock();
|
|
list_for_each_entry_safe(plist, tmp_plist,
|
|
&map_list.head[id], list_node) {
|
|
if (plist->iova >= iova &&
|
|
(plist->iova + plist->size) <= (iova + size) &&
|
|
plist->tab_id == tab_id) {
|
|
total += plist->size;
|
|
list_del(&plist->list_node);
|
|
kfree(plist);
|
|
if (total == size)
|
|
break;
|
|
}
|
|
}
|
|
end_t = sched_clock();
|
|
if ((end_t - start_t) > 5000000) //5ms
|
|
pr_info("%s time:%llu\n", __func__, (end_t - start_t));
|
|
spin_unlock_irqrestore(&map_list.lock, flags);
|
|
|
|
mtk_iommu_iova_trace(IOMMU_UNMAP, iova, size, tab_id, NULL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iova_unmap);
|
|
|
|
void mtk_iova_map_dump(u64 iova, u32 tab_id)
|
|
{
|
|
mtk_iommu_iova_map_dump(NULL, iova, tab_id);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iova_map_dump);
|
|
|
|
static void mtk_iommu_iova_map_dump(struct seq_file *s, u64 iova, u32 tab_id)
|
|
{
|
|
u32 i, id = (iova >> 32);
|
|
unsigned long flags;
|
|
struct iova_map_info *plist = NULL;
|
|
struct iova_map_info *n = NULL;
|
|
|
|
if (id >= MTK_IOVA_SPACE_NUM) {
|
|
pr_err("out of iova space: 0x%llx\n", iova);
|
|
return;
|
|
}
|
|
|
|
iommu_dump(s, "iommu iova map dump:\n");
|
|
iommu_dump(s, "%-6s %-14s %-10s %-18s\n",
|
|
"tab_id", "start_iova", "size", "time");
|
|
|
|
spin_lock_irqsave(&map_list.lock, flags);
|
|
if (!iova) {
|
|
for (i = 0; i < MTK_IOVA_SPACE_NUM; i++) {
|
|
list_for_each_entry_safe(plist, n, &map_list.head[i], list_node)
|
|
if (plist->tab_id == tab_id)
|
|
iommu_dump(s, "%-6u 0x%-12llx 0x%-8zx %llu.%06u\n",
|
|
plist->tab_id,
|
|
plist->iova,
|
|
plist->size,
|
|
plist->time_high,
|
|
(unsigned int)plist->time_low);
|
|
}
|
|
spin_unlock_irqrestore(&map_list.lock, flags);
|
|
return;
|
|
}
|
|
|
|
list_for_each_entry_safe(plist, n, &map_list.head[id], list_node)
|
|
if (plist->tab_id == tab_id && iova <= (plist->iova + SZ_4M) &&
|
|
iova >= (plist->iova - SZ_4M))
|
|
iommu_dump(s, "%-6u 0x%-12llx 0x%-8zx %llu.%06u\n",
|
|
plist->tab_id,
|
|
plist->iova,
|
|
plist->size,
|
|
plist->time_high,
|
|
(unsigned int)plist->time_low);
|
|
spin_unlock_irqrestore(&map_list.lock, flags);
|
|
}
|
|
|
|
static void mtk_iommu_trace_dump(struct seq_file *s)
|
|
{
|
|
int event_id;
|
|
int i = 0;
|
|
|
|
if (iommu_globals.dump_enable == 0)
|
|
return;
|
|
|
|
iommu_dump(s, "iommu trace dump:\n");
|
|
iommu_dump(s, "%-8s %-4s %-14s %-12s %-14s %-18s %-18s\n",
|
|
"action", "tab_id", "iova_start", "size", "iova_end", "time", "dev");
|
|
for (i = 0; i < IOMMU_MAX_EVENT_COUNT; i++) {
|
|
unsigned long end_iova = 0;
|
|
|
|
if ((iommu_globals.record[i].time_low == 0) &&
|
|
(iommu_globals.record[i].time_high == 0))
|
|
break;
|
|
event_id = iommu_globals.record[i].event_id;
|
|
if (event_id < 0 || event_id >= IOMMU_EVENT_MAX)
|
|
continue;
|
|
|
|
if (event_id <= IOMMU_UNSYNC)
|
|
end_iova = iommu_globals.record[i].data1 +
|
|
iommu_globals.record[i].data2 - 1;
|
|
|
|
iommu_dump(s,
|
|
"%-8s %-6lu 0x%-12lx 0x%-10zx 0x%-12lx %u.%06u %s\n",
|
|
event_mgr[event_id].name,
|
|
iommu_globals.record[i].data3,
|
|
iommu_globals.record[i].data1,
|
|
iommu_globals.record[i].data2,
|
|
end_iova,
|
|
iommu_globals.record[i].time_high,
|
|
iommu_globals.record[i].time_low,
|
|
(iommu_globals.record[i].dev != NULL ?
|
|
dev_name(iommu_globals.record[i].dev) : ""));
|
|
}
|
|
}
|
|
|
|
void mtk_iommu_debug_reset(void)
|
|
{
|
|
iommu_globals.enable = 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_debug_reset);
|
|
|
|
static struct mtk_m4u_data *m4u_data;
|
|
static int mtk_iommu_get_tf_port_idx(int tf_id, enum mtk_iommu_type type, int id)
|
|
{
|
|
int i;
|
|
u32 vld_id, port_nr;
|
|
const struct mtk_iommu_port *port_list;
|
|
int (*mm_tf_is_gce_videoup)(u32 port_tf, u32 vld_tf);
|
|
|
|
if (type < MM_IOMMU || type >= TYPE_NUM) {
|
|
pr_info("%s fail, invalid type %d\n", __func__, type);
|
|
return m4u_data->plat_data->port_nr[MM_IOMMU];
|
|
}
|
|
|
|
if (type == APU_IOMMU)
|
|
vld_id = F_APU_MMU_INT_TF_MSK(tf_id);
|
|
else
|
|
vld_id = tf_id & F_MMU_INT_TF_MSK;
|
|
|
|
pr_info("get vld tf_id:0x%x\n", vld_id);
|
|
port_nr = m4u_data->plat_data->port_nr[type];
|
|
port_list = m4u_data->plat_data->port_list[type];
|
|
/* check (larb | port) for smi_larb or apu_bus */
|
|
for (i = 0; i < port_nr; i++) {
|
|
if (port_list[i].port_type == NORMAL &&
|
|
port_list[i].tf_id == vld_id &&
|
|
port_list[i].m4u_id == id)
|
|
return i;
|
|
}
|
|
/* check larb for smi_common */
|
|
if (type == MM_IOMMU && m4u_data->plat_data->mm_tf_ccu_support) {
|
|
for (i = 0; i < port_nr; i++) {
|
|
if (port_list[i].port_type == CCU_FAKE &&
|
|
(port_list[i].tf_id & F_MMU_INT_TF_CCU_MSK) ==
|
|
(vld_id & F_MMU_INT_TF_CCU_MSK) &&
|
|
port_list[i].m4u_id == id)
|
|
return i;
|
|
}
|
|
}
|
|
|
|
/* check gce/video_uP */
|
|
mm_tf_is_gce_videoup = m4u_data->plat_data->mm_tf_is_gce_videoup;
|
|
if (type == MM_IOMMU && mm_tf_is_gce_videoup) {
|
|
for (i = 0; i < port_nr; i++) {
|
|
if (port_list[i].port_type == GCE_VIDEOUP_FAKE &&
|
|
mm_tf_is_gce_videoup(port_list[i].tf_id, tf_id) &&
|
|
port_list[i].m4u_id == id)
|
|
return i;
|
|
}
|
|
}
|
|
|
|
return port_nr;
|
|
}
|
|
|
|
static int mtk_iommu_port_idx(int id, enum mtk_iommu_type type)
|
|
{
|
|
int i;
|
|
u32 port_nr = m4u_data->plat_data->port_nr[type];
|
|
const struct mtk_iommu_port *port_list;
|
|
|
|
if (type < MM_IOMMU || type >= TYPE_NUM) {
|
|
pr_info("%s fail, invalid type %d\n", __func__, type);
|
|
return m4u_data->plat_data->port_nr[MM_IOMMU];
|
|
}
|
|
|
|
port_list = m4u_data->plat_data->port_list[type];
|
|
for (i = 0; i < port_nr; i++) {
|
|
if ((port_list[i].larb_id == MTK_M4U_TO_LARB(id)) &&
|
|
(port_list[i].port_id == MTK_M4U_TO_PORT(id)))
|
|
return i;
|
|
}
|
|
return port_nr;
|
|
}
|
|
|
|
void report_custom_iommu_fault(
|
|
u64 fault_iova, u64 fault_pa,
|
|
u32 fault_id, enum mtk_iommu_type type,
|
|
int id)
|
|
{
|
|
int idx;
|
|
u32 port_nr;
|
|
const struct mtk_iommu_port *port_list;
|
|
|
|
if (type < MM_IOMMU || type >= TYPE_NUM) {
|
|
pr_info("%s fail, invalid type %d\n", __func__, type);
|
|
return;
|
|
}
|
|
|
|
pr_info("error, tf report start fault_id:0x%x\n", fault_id);
|
|
port_nr = m4u_data->plat_data->port_nr[type];
|
|
port_list = m4u_data->plat_data->port_list[type];
|
|
idx = mtk_iommu_get_tf_port_idx(fault_id, type, id);
|
|
if (idx >= port_nr) {
|
|
pr_warn("fail,iova:0x%llx, port:0x%x\n",
|
|
fault_iova, fault_id);
|
|
return;
|
|
}
|
|
|
|
/* Only MM_IOMMU support fault callback */
|
|
if (type == MM_IOMMU) {
|
|
pr_info("error, tf report larb-port:(%u--%u), idx:%d\n",
|
|
port_list[idx].larb_id,
|
|
port_list[idx].port_id, idx);
|
|
|
|
if (port_list[idx].enable_tf &&
|
|
m4u_data->m4u_cb[idx].fault_fn)
|
|
m4u_data->m4u_cb[idx].fault_fn(m4u_data->m4u_cb[idx].port,
|
|
fault_iova, m4u_data->m4u_cb[idx].fault_data);
|
|
}
|
|
|
|
m4u_aee_print(mmu_translation_log_format,
|
|
port_list[idx].name,
|
|
port_list[idx].name, fault_iova,
|
|
fault_pa);
|
|
}
|
|
EXPORT_SYMBOL_GPL(report_custom_iommu_fault);
|
|
|
|
void report_iommu_mau_fault(
|
|
u32 assert_id, u32 falut_id, char *port_name,
|
|
u32 assert_addr, u32 assert_b32)
|
|
{
|
|
m4u_aee_print(mau_assert_log_format,
|
|
assert_id, falut_id, port_name, assert_addr, assert_b32);
|
|
}
|
|
EXPORT_SYMBOL_GPL(report_iommu_mau_fault);
|
|
|
|
int mtk_iommu_register_fault_callback(int port,
|
|
mtk_iommu_fault_callback_t fn,
|
|
void *cb_data, bool is_vpu)
|
|
{
|
|
enum mtk_iommu_type type = is_vpu ? APU_IOMMU : MM_IOMMU;
|
|
int idx = mtk_iommu_port_idx(port, type);
|
|
|
|
if (idx >= m4u_data->plat_data->port_nr[type]) {
|
|
pr_info("%s fail, port=%d\n", __func__, port);
|
|
return -1;
|
|
}
|
|
if (is_vpu)
|
|
idx += m4u_data->plat_data->port_nr[type];
|
|
m4u_data->m4u_cb[idx].port = port;
|
|
m4u_data->m4u_cb[idx].fault_fn = fn;
|
|
m4u_data->m4u_cb[idx].fault_data = cb_data;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_register_fault_callback);
|
|
|
|
int mtk_iommu_unregister_fault_callback(int port, bool is_vpu)
|
|
{
|
|
enum mtk_iommu_type type = is_vpu ? APU_IOMMU : MM_IOMMU;
|
|
int idx = mtk_iommu_port_idx(port, type);
|
|
|
|
if (idx >= m4u_data->plat_data->port_nr[type]) {
|
|
pr_info("%s fail, port=%d\n", __func__, port);
|
|
return -1;
|
|
}
|
|
if (is_vpu)
|
|
idx += m4u_data->plat_data->port_nr[type];
|
|
m4u_data->m4u_cb[idx].port = -1;
|
|
m4u_data->m4u_cb[idx].fault_fn = NULL;
|
|
m4u_data->m4u_cb[idx].fault_data = NULL;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_unregister_fault_callback);
|
|
|
|
char *mtk_iommu_get_port_name(enum mtk_iommu_type type, int id, int tf_id)
|
|
{
|
|
const struct mtk_iommu_port *port_list;
|
|
u32 port_nr;
|
|
int idx;
|
|
|
|
if (type < MM_IOMMU || type >= TYPE_NUM) {
|
|
pr_notice("%s fail, invalid type %d\n", __func__, type);
|
|
return "m4u_port_unknown";
|
|
}
|
|
|
|
if (type == PERI_IOMMU)
|
|
return peri_tf_analyse(id, tf_id);
|
|
|
|
port_nr = m4u_data->plat_data->port_nr[type];
|
|
port_list = m4u_data->plat_data->port_list[type];
|
|
idx = mtk_iommu_get_tf_port_idx(tf_id, type, id);
|
|
if (idx >= port_nr) {
|
|
pr_notice("%s err, iommu(%d,%d) tf_id:0x%x\n",
|
|
__func__, type, id, tf_id);
|
|
return "m4u_port_unknown";
|
|
}
|
|
|
|
return port_list[idx].name;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_get_port_name);
|
|
|
|
const struct mau_config_info *mtk_iommu_get_mau_config(
|
|
enum mtk_iommu_type type, int id,
|
|
unsigned int slave, unsigned int mau)
|
|
{
|
|
const struct mau_config_info *mau_config;
|
|
int i;
|
|
|
|
for (i = 0; i < m4u_data->plat_data->mau_config_nr; i++) {
|
|
mau_config = &m4u_data->plat_data->mau_config[i];
|
|
if (mau_config->iommu_type == type &&
|
|
mau_config->iommu_id == id &&
|
|
mau_config->slave == slave &&
|
|
mau_config->mau == mau)
|
|
return mau_config;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_get_mau_config);
|
|
|
|
static int mtk_iommu_debug_help(struct seq_file *s)
|
|
{
|
|
iommu_dump(s, "iommu debug file:\n");
|
|
iommu_dump(s, "help: description debug file and command\n");
|
|
iommu_dump(s, "debug: iommu main debug file, receive debug command\n");
|
|
iommu_dump(s, "iommu_dump: iova trace dump file\n");
|
|
iommu_dump(s, "iova_alloc: iova alloc list dump file\n");
|
|
iommu_dump(s, "iova_map: iova map list dump file\n\n");
|
|
|
|
iommu_dump(s, "iommu debug command:\n");
|
|
iommu_dump(s, "echo 1 > /proc/iommu_debug/debug: iommu debug help\n");
|
|
iommu_dump(s, "echo 2 > /proc/iommu_debug/debug: mm translation fault test\n");
|
|
iommu_dump(s, "echo 3 > /proc/iommu_debug/debug: apu translation fault test\n");
|
|
iommu_dump(s, "echo 4 > /proc/iommu_debug/debug: peri translation fault test\n");
|
|
iommu_dump(s, "echo 5 > /proc/iommu_debug/debug: dump bank base address\n");
|
|
iommu_dump(s, "echo 6 > /proc/iommu_debug/debug: secure bank0 value\n");
|
|
iommu_dump(s, "echo 7 > /proc/iommu_debug/debug: secure bank init\n");
|
|
iommu_dump(s, "echo 8 > /proc/iommu_debug/debug: secure bank irq enable\n");
|
|
iommu_dump(s, "echo 9 > /proc/iommu_debug/debug: secure bank backup\n");
|
|
iommu_dump(s, "echo 10 > /proc/iommu_debug/debug: secure bank restore\n");
|
|
iommu_dump(s, "echo 11 > /proc/iommu_debug/debug: secure switch enable\n");
|
|
iommu_dump(s, "echo 12 > /proc/iommu_debug/debug: secure switch disable\n");
|
|
iommu_dump(s, "echo 13 > /proc/iommu_debug/debug: enable trace log\n");
|
|
iommu_dump(s, "echo 14 > /proc/iommu_debug/debug: disable trace log\n");
|
|
iommu_dump(s, "echo 15 > /proc/iommu_debug/debug: enable trace dump\n");
|
|
iommu_dump(s, "echo 16 > /proc/iommu_debug/debug: disable trace dump\n");
|
|
iommu_dump(s, "echo 17 > /proc/iommu_debug/debug: reset to default trace log & dump\n");
|
|
iommu_dump(s, "echo 18 > /proc/iommu_debug/debug: dump iova trace\n");
|
|
iommu_dump(s, "echo 19 > /proc/iommu_debug/debug: dump iova alloc list\n");
|
|
iommu_dump(s, "echo 20 > /proc/iommu_debug/debug: dump iova map list\n");
|
|
return 0;
|
|
}
|
|
|
|
static char *mt6983_peri_m7_id(u32 id)
|
|
{
|
|
u32 id1_0 = id & GENMASK(1, 0);
|
|
u32 id4_2 = FIELD_GET(GENMASK(4, 2), id);
|
|
|
|
if (id1_0 == 0)
|
|
return "MCU_AP_M";
|
|
else if (id1_0 == 1)
|
|
return "DEBUG_TRACE_LOG";
|
|
else if (id1_0 == 2)
|
|
return "PERI2INFRA1_M";
|
|
|
|
switch (id4_2) {
|
|
case 0:
|
|
return "CQ_DMA";
|
|
case 1:
|
|
return "DEBUGTOP";
|
|
case 2:
|
|
return "GPU_EB";
|
|
case 3:
|
|
return "CPUM_M";
|
|
case 4:
|
|
return "DXCC_M";
|
|
default:
|
|
return "UNKNOWN";
|
|
}
|
|
}
|
|
|
|
static char *mt6983_peri_m6_id(u32 id)
|
|
{
|
|
return "PERI2INFRA0_M";
|
|
}
|
|
|
|
static char *mt6983_peri_m4_id(u32 id)
|
|
{
|
|
u32 id0 = id & 0x1;
|
|
u32 id1_0 = id & GENMASK(1, 0);
|
|
u32 id3_2 = FIELD_GET(GENMASK(3, 2), id);
|
|
|
|
if (id0 == 0)
|
|
return "DFD_M";
|
|
else if (id1_0 == 1)
|
|
return "DPMAIF_M";
|
|
|
|
switch (id3_2) {
|
|
case 0:
|
|
return "ADSPSYS_M0_M";
|
|
case 1:
|
|
return "VLPSYS_M";
|
|
case 2:
|
|
return "CONN_M";
|
|
default:
|
|
return "UNKNOWN";
|
|
}
|
|
}
|
|
|
|
static char *mt6983_peri_tf(enum peri_iommu id, u32 fault_id)
|
|
{
|
|
switch (id) {
|
|
case PERI_IOMMU_M4:
|
|
return mt6983_peri_m4_id(fault_id);
|
|
case PERI_IOMMU_M6:
|
|
return mt6983_peri_m6_id(fault_id);
|
|
case PERI_IOMMU_M7:
|
|
return mt6983_peri_m7_id(fault_id);
|
|
default:
|
|
return "UNKNOWN";
|
|
}
|
|
}
|
|
|
|
enum peri_iommu get_peri_iommu_id(u32 bus_id)
|
|
{
|
|
int i;
|
|
|
|
for (i = PERI_IOMMU_M4; i < PERI_IOMMU_NUM; i++) {
|
|
if (bus_id == m4u_data->plat_data->peri_data[i].bus_id)
|
|
return i;
|
|
}
|
|
|
|
return PERI_IOMMU_NUM;
|
|
};
|
|
EXPORT_SYMBOL_GPL(get_peri_iommu_id);
|
|
|
|
char *peri_tf_analyse(enum peri_iommu iommu_id, u32 fault_id)
|
|
{
|
|
if (m4u_data->plat_data->peri_tf_analyse)
|
|
return m4u_data->plat_data->peri_tf_analyse(iommu_id, fault_id);
|
|
|
|
pr_info("%s is not support\n", __func__);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(peri_tf_analyse);
|
|
|
|
static int m4u_debug_set(void *data, u64 val)
|
|
{
|
|
int ret = 0;
|
|
|
|
pr_info("%s:val=%llu\n", __func__, val);
|
|
|
|
switch (val) {
|
|
case 1: /* show help info */
|
|
ret = mtk_iommu_debug_help(NULL);
|
|
break;
|
|
case 2: /* mm translation fault test */
|
|
report_custom_iommu_fault(0, 0, 0x500000f, MM_IOMMU, 0);
|
|
break;
|
|
case 3: /* apu translation fault test */
|
|
report_custom_iommu_fault(0, 0, 0x102, APU_IOMMU, 0);
|
|
break;
|
|
case 4: /* peri translation fault test */
|
|
report_custom_iommu_fault(0, 0, 0x102, PERI_IOMMU, 0);
|
|
break;
|
|
case 5:
|
|
ret = mtk_iommu_sec_bk_init_by_atf(MM_IOMMU, DISP_IOMMU);
|
|
break;
|
|
case 6:
|
|
ret = mtk_iommu_sec_bk_irq_en_by_atf(MM_IOMMU, DISP_IOMMU, 1);
|
|
break;
|
|
case 7:
|
|
ret = mtk_iommu_secure_bk_backup_by_atf(MM_IOMMU, DISP_IOMMU);
|
|
break;
|
|
case 8:
|
|
ret = mtk_iommu_secure_bk_restore_by_atf(MM_IOMMU, DISP_IOMMU);
|
|
break;
|
|
case 9:
|
|
ret = ao_secure_dbg_switch_by_atf(MM_IOMMU, DISP_IOMMU, 1);
|
|
break;
|
|
case 10:
|
|
ret = ao_secure_dbg_switch_by_atf(MM_IOMMU, DISP_IOMMU, 0);
|
|
break;
|
|
case 11: /* enable trace log */
|
|
event_mgr[IOMMU_ALLOC].dump_log = 1;
|
|
event_mgr[IOMMU_FREE].dump_log = 1;
|
|
event_mgr[IOMMU_MAP].dump_log = 1;
|
|
event_mgr[IOMMU_UNMAP].dump_log = 1;
|
|
break;
|
|
case 12: /* disable trace log */
|
|
event_mgr[IOMMU_ALLOC].dump_log = 0;
|
|
event_mgr[IOMMU_FREE].dump_log = 0;
|
|
event_mgr[IOMMU_MAP].dump_log = 0;
|
|
event_mgr[IOMMU_UNMAP].dump_log = 0;
|
|
break;
|
|
case 13: /* enable trace dump */
|
|
event_mgr[IOMMU_ALLOC].dump_trace = 1;
|
|
event_mgr[IOMMU_FREE].dump_trace = 1;
|
|
event_mgr[IOMMU_MAP].dump_trace = 1;
|
|
event_mgr[IOMMU_UNMAP].dump_trace = 1;
|
|
event_mgr[IOMMU_SYNC].dump_trace = 1;
|
|
event_mgr[IOMMU_UNSYNC].dump_trace = 1;
|
|
break;
|
|
case 14: /* disable trace dump */
|
|
event_mgr[IOMMU_ALLOC].dump_trace = 0;
|
|
event_mgr[IOMMU_FREE].dump_trace = 0;
|
|
event_mgr[IOMMU_MAP].dump_trace = 0;
|
|
event_mgr[IOMMU_UNMAP].dump_trace = 0;
|
|
event_mgr[IOMMU_SYNC].dump_trace = 0;
|
|
event_mgr[IOMMU_UNSYNC].dump_trace = 0;
|
|
break;
|
|
case 15: /* reset to default trace log & dump */
|
|
event_mgr[IOMMU_ALLOC].dump_trace = 1;
|
|
event_mgr[IOMMU_FREE].dump_trace = 1;
|
|
event_mgr[IOMMU_SYNC].dump_trace = 1;
|
|
event_mgr[IOMMU_UNSYNC].dump_trace = 1;
|
|
event_mgr[IOMMU_MAP].dump_trace = 0;
|
|
event_mgr[IOMMU_UNMAP].dump_trace = 0;
|
|
event_mgr[IOMMU_ALLOC].dump_log = 0;
|
|
event_mgr[IOMMU_FREE].dump_log = 0;
|
|
event_mgr[IOMMU_MAP].dump_log = 0;
|
|
event_mgr[IOMMU_UNMAP].dump_log = 0;
|
|
break;
|
|
case 16: /* dump iova trace */
|
|
mtk_iommu_trace_dump(NULL);
|
|
break;
|
|
case 17: /* dump iova alloc list */
|
|
mtk_iommu_iova_alloc_dump_top(NULL, NULL);
|
|
mtk_iommu_iova_alloc_dump(NULL, NULL);
|
|
break;
|
|
case 18: /* dump iova map list */
|
|
mtk_iommu_iova_map_dump(NULL, 0, MM_TABLE);
|
|
mtk_iommu_iova_map_dump(NULL, 0, APU_TABLE);
|
|
break;
|
|
#if IS_ENABLED(CONFIG_MTK_IOMMU_DEBUG)
|
|
case 19:
|
|
mtk_iommu_dump_bank_base();
|
|
break;
|
|
case 20:
|
|
ret = mtk_iommu_dump_bk0_val(MM_IOMMU, DISP_IOMMU);
|
|
break;
|
|
case 21: /* dump DISP_IOMMU bank1 pagetable */
|
|
ret = mtk_iommu_sec_bk_pgtable_dump(MM_IOMMU, DISP_IOMMU,
|
|
IOMMU_BK1, 0);
|
|
break;
|
|
#endif
|
|
default:
|
|
pr_err("%s error,val=%llu\n", __func__, val);
|
|
break;
|
|
}
|
|
|
|
if (ret)
|
|
pr_info("%s failed:val=%llu, ret=%d\n", __func__, val, ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m4u_debug_get(void *data, u64 *val)
|
|
{
|
|
*val = 0;
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_PROC_ATTRIBUTE(m4u_debug_fops, m4u_debug_get, m4u_debug_set, "%llu\n");
|
|
|
|
#if IS_ENABLED(CONFIG_PROC_FS)
|
|
/* Define proc_ops: *_proc_show function will be called when file is opened */
|
|
#define DEFINE_PROC_FOPS_RO(name) \
|
|
static int name ## _proc_open(struct inode *inode, \
|
|
struct file *file) \
|
|
{ \
|
|
return single_open(file, name ## _proc_show, \
|
|
PDE_DATA(inode)); \
|
|
} \
|
|
static const struct proc_ops name = { \
|
|
.proc_open = name ## _proc_open, \
|
|
.proc_read = seq_read, \
|
|
.proc_lseek = seq_lseek, \
|
|
.proc_release = single_release, \
|
|
}
|
|
|
|
static int mtk_iommu_help_fops_proc_show(struct seq_file *s, void *unused)
|
|
{
|
|
mtk_iommu_debug_help(s);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_iommu_dump_fops_proc_show(struct seq_file *s, void *unused)
|
|
{
|
|
mtk_iommu_trace_dump(s);
|
|
mtk_iommu_iova_alloc_dump(s, NULL);
|
|
mtk_iommu_iova_alloc_dump_top(s, NULL);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_iommu_iova_alloc_fops_proc_show(struct seq_file *s, void *unused)
|
|
{
|
|
mtk_iommu_iova_alloc_dump_top(s, NULL);
|
|
mtk_iommu_iova_alloc_dump(s, NULL);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_iommu_iova_map_fops_proc_show(struct seq_file *s, void *unused)
|
|
{
|
|
mtk_iommu_iova_map_dump(s, 0, MM_TABLE);
|
|
mtk_iommu_iova_map_dump(s, 0, APU_TABLE);
|
|
return 0;
|
|
}
|
|
|
|
/* adb shell cat /proc/iommu_debug/help */
|
|
DEFINE_PROC_FOPS_RO(mtk_iommu_help_fops);
|
|
/* adb shell cat /proc/iommu_debug/iommu_dump */
|
|
DEFINE_PROC_FOPS_RO(mtk_iommu_dump_fops);
|
|
/* adb shell cat /proc/iommu_debug/iova_alloc */
|
|
DEFINE_PROC_FOPS_RO(mtk_iommu_iova_alloc_fops);
|
|
/* adb shell cat /proc/iommu_debug/iova_map */
|
|
DEFINE_PROC_FOPS_RO(mtk_iommu_iova_map_fops);
|
|
#endif
|
|
|
|
static void mtk_iommu_trace_init(struct mtk_m4u_data *data)
|
|
{
|
|
int total_size = IOMMU_MAX_EVENT_COUNT * sizeof(struct iommu_event_t);
|
|
|
|
strncpy(event_mgr[IOMMU_ALLOC].name, "alloc", 10);
|
|
strncpy(event_mgr[IOMMU_FREE].name, "free", 10);
|
|
strncpy(event_mgr[IOMMU_MAP].name, "map", 10);
|
|
strncpy(event_mgr[IOMMU_UNMAP].name, "unmap", 10);
|
|
strncpy(event_mgr[IOMMU_SYNC].name, "sync", 10);
|
|
strncpy(event_mgr[IOMMU_UNSYNC].name, "unsync", 10);
|
|
strncpy(event_mgr[IOMMU_SUSPEND].name, "suspend", 10);
|
|
strncpy(event_mgr[IOMMU_RESUME].name, "resume", 10);
|
|
event_mgr[IOMMU_ALLOC].dump_trace = 1;
|
|
event_mgr[IOMMU_FREE].dump_trace = 1;
|
|
event_mgr[IOMMU_SYNC].dump_trace = 1;
|
|
event_mgr[IOMMU_UNSYNC].dump_trace = 1;
|
|
event_mgr[IOMMU_SUSPEND].dump_trace = 1;
|
|
event_mgr[IOMMU_RESUME].dump_trace = 1;
|
|
|
|
iommu_globals.record = vmalloc(total_size);
|
|
if (!iommu_globals.record) {
|
|
iommu_globals.enable = 0;
|
|
return;
|
|
}
|
|
|
|
memset(iommu_globals.record, 0, total_size);
|
|
iommu_globals.enable = 1;
|
|
iommu_globals.dump_enable = 1;
|
|
iommu_globals.write_pointer = 0;
|
|
|
|
spin_lock_init(&iommu_globals.lock);
|
|
}
|
|
|
|
static void mtk_iommu_system_time(unsigned int *low, unsigned int *high)
|
|
{
|
|
unsigned long long temp;
|
|
|
|
temp = sched_clock();
|
|
do_div(temp, 1000);
|
|
*low = do_div(temp, 1000000);
|
|
*high = (unsigned int)temp;
|
|
}
|
|
|
|
static void mtk_iommu_trace_rec_write(int event,
|
|
unsigned long data1,
|
|
unsigned long data2,
|
|
unsigned long data3,
|
|
struct device *dev)
|
|
{
|
|
unsigned int index;
|
|
struct iommu_event_t *p_event = NULL;
|
|
unsigned long flags;
|
|
|
|
if (iommu_globals.enable == 0)
|
|
return;
|
|
if ((event >= IOMMU_EVENT_MAX) ||
|
|
(event < 0))
|
|
return;
|
|
|
|
if (event_mgr[event].dump_log)
|
|
pr_info("[trace] %5s |0x%-9lx |%9zx |0x%lx |%s\n",
|
|
event_mgr[event].name,
|
|
data1, data2, data3,
|
|
(dev != NULL ? dev_name(dev) : ""));
|
|
|
|
if (event_mgr[event].dump_trace == 0)
|
|
return;
|
|
|
|
index = (atomic_inc_return((atomic_t *)
|
|
&(iommu_globals.write_pointer)) - 1)
|
|
% IOMMU_MAX_EVENT_COUNT;
|
|
|
|
spin_lock_irqsave(&iommu_globals.lock, flags);
|
|
|
|
p_event = (struct iommu_event_t *)
|
|
&(iommu_globals.record[index]);
|
|
mtk_iommu_system_time(&(p_event->time_low), &(p_event->time_high));
|
|
p_event->event_id = event;
|
|
p_event->data1 = data1;
|
|
p_event->data2 = data2;
|
|
p_event->data3 = data3;
|
|
p_event->dev = dev;
|
|
|
|
spin_unlock_irqrestore(&iommu_globals.lock, flags);
|
|
}
|
|
|
|
static void mtk_iommu_iova_trace(int event, dma_addr_t iova, size_t size,
|
|
u32 tab_id, struct device *dev)
|
|
{
|
|
u32 id = (iova >> 32);
|
|
|
|
if (id >= MTK_IOVA_SPACE_NUM) {
|
|
pr_err("out of iova space: 0x%llx\n", iova);
|
|
return;
|
|
}
|
|
|
|
mtk_iommu_trace_rec_write(event, (unsigned long) iova, size, tab_id, dev);
|
|
}
|
|
|
|
void mtk_iommu_tlb_sync_trace(u64 iova, size_t size, int iommu_ids)
|
|
{
|
|
mtk_iommu_trace_rec_write(IOMMU_SYNC, (unsigned long) iova, size,
|
|
(unsigned long) iommu_ids, NULL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_tlb_sync_trace);
|
|
|
|
void mtk_iommu_pm_trace(struct device *dev, bool resume)
|
|
{
|
|
int event;
|
|
|
|
if (resume)
|
|
event = IOMMU_RESUME;
|
|
else
|
|
event = IOMMU_SUSPEND;
|
|
|
|
mtk_iommu_trace_rec_write(event, 0x0, 0x0, 0x0, dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_iommu_pm_trace);
|
|
|
|
static int m4u_debug_init(struct mtk_m4u_data *data)
|
|
{
|
|
struct proc_dir_entry *debug_file;
|
|
|
|
if (IS_ENABLED(CONFIG_PROC_FS)) {
|
|
data->debug_root = proc_mkdir("iommu_debug", NULL);
|
|
|
|
if (IS_ERR_OR_NULL(data->debug_root))
|
|
pr_err("failed to create debug dir\n");
|
|
|
|
debug_file = proc_create_data("debug",
|
|
S_IFREG | 0644, data->debug_root, &m4u_debug_fops, NULL);
|
|
|
|
if (IS_ERR_OR_NULL(debug_file))
|
|
pr_err("failed to create debug file\n");
|
|
|
|
debug_file = proc_create_data("help",
|
|
S_IFREG | 0644, data->debug_root, &mtk_iommu_help_fops, NULL);
|
|
if (IS_ERR_OR_NULL(debug_file))
|
|
pr_err("failed to proc_create help file\n");
|
|
|
|
debug_file = proc_create_data("iommu_dump",
|
|
S_IFREG | 0644, data->debug_root, &mtk_iommu_dump_fops, NULL);
|
|
if (IS_ERR_OR_NULL(debug_file))
|
|
pr_err("failed to proc_create iommu_dump file\n");
|
|
|
|
debug_file = proc_create_data("iova_alloc",
|
|
S_IFREG | 0644, data->debug_root, &mtk_iommu_iova_alloc_fops, NULL);
|
|
if (IS_ERR_OR_NULL(debug_file))
|
|
pr_err("failed to proc_create iova_alloc file\n");
|
|
|
|
debug_file = proc_create_data("iova_map",
|
|
S_IFREG | 0644, data->debug_root, &mtk_iommu_iova_map_fops, NULL);
|
|
if (IS_ERR_OR_NULL(debug_file))
|
|
pr_err("failed to proc_create iova_map file\n");
|
|
}
|
|
|
|
mtk_iommu_trace_init(data);
|
|
|
|
if (!atomic_cmpxchg(&iova_list.init_flag, 0, 1)) {
|
|
spin_lock_init(&iova_list.lock);
|
|
INIT_LIST_HEAD(&iova_list.head);
|
|
}
|
|
|
|
if (!atomic_cmpxchg(&map_list.init_flag, 0, 1)) {
|
|
spin_lock_init(&map_list.lock);
|
|
INIT_LIST_HEAD(&map_list.head[MTK_IOVA_SPACE0]);
|
|
INIT_LIST_HEAD(&map_list.head[MTK_IOVA_SPACE1]);
|
|
INIT_LIST_HEAD(&map_list.head[MTK_IOVA_SPACE2]);
|
|
INIT_LIST_HEAD(&map_list.head[MTK_IOVA_SPACE3]);
|
|
}
|
|
|
|
spin_lock_init(&count_list.lock);
|
|
INIT_LIST_HEAD(&count_list.head);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iova_size_cmp(void *priv, struct list_head *a, struct list_head *b)
|
|
{
|
|
struct iova_count_info *ia, *ib;
|
|
|
|
ia = list_entry(a, struct iova_count_info, list_node);
|
|
ib = list_entry(b, struct iova_count_info, list_node);
|
|
|
|
if (ia->size < ib->size)
|
|
return 1;
|
|
if (ia->size > ib->size)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_iommu_clear_iova_size(void)
|
|
{
|
|
struct iova_count_info *plist;
|
|
struct iova_count_info *tmp_plist;
|
|
|
|
list_for_each_entry_safe(plist, tmp_plist, &count_list.head, list_node) {
|
|
list_del(&plist->list_node);
|
|
kfree(plist);
|
|
}
|
|
}
|
|
|
|
static void mtk_iommu_count_iova_size(struct device *dev,
|
|
dma_addr_t iova, size_t size)
|
|
{
|
|
struct iommu_fwspec *fwspec = NULL;
|
|
struct iova_count_info *plist = NULL;
|
|
struct iova_count_info *n = NULL;
|
|
struct iova_count_info *new_info;
|
|
|
|
fwspec = dev_iommu_fwspec_get(dev);
|
|
if (fwspec == NULL) {
|
|
pr_notice("%s fail! dev:%s, fwspec is NULL\n",
|
|
__func__, dev_name(dev));
|
|
return;
|
|
}
|
|
|
|
/* Add to iova_count_info if exist */
|
|
spin_lock(&count_list.lock);
|
|
list_for_each_entry_safe(plist, n, &count_list.head, list_node) {
|
|
if (plist->dev == dev) {
|
|
plist->count++;
|
|
plist->size += (unsigned long) (size / 1024);
|
|
spin_unlock(&count_list.lock);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Create new iova_count_info if no exist */
|
|
new_info = kzalloc(sizeof(*new_info), GFP_ATOMIC);
|
|
if (!new_info) {
|
|
spin_unlock(&count_list.lock);
|
|
pr_notice("%s, alloc iova_count_info fail! dev:%s\n",
|
|
__func__, dev_name(dev));
|
|
return;
|
|
}
|
|
|
|
new_info->tab_id = MTK_M4U_TO_TAB(fwspec->ids[0]);
|
|
new_info->dom_id = MTK_M4U_TO_DOM(fwspec->ids[0]);
|
|
new_info->dev = dev;
|
|
new_info->size = (unsigned long) (size / 1024);
|
|
new_info->count = 1;
|
|
list_add_tail(&new_info->list_node, &count_list.head);
|
|
spin_unlock(&count_list.lock);
|
|
}
|
|
|
|
static void mtk_iommu_iova_alloc_dump_top(struct seq_file *s,
|
|
struct device *dev)
|
|
{
|
|
struct iommu_fwspec *fwspec = NULL;
|
|
struct iova_info *plist = NULL;
|
|
struct iova_info *n = NULL;
|
|
struct iova_count_info *p_count_list = NULL;
|
|
struct iova_count_info *n_count = NULL;
|
|
int total_cnt = 0, dom_count = 0, tab_id = -1, dom_id = -1, i = 0;
|
|
u64 size = 0, total_size = 0, dom_size = 0;
|
|
|
|
/* check fwspec by device */
|
|
if (dev != NULL) {
|
|
fwspec = dev_iommu_fwspec_get(dev);
|
|
if (fwspec == NULL) {
|
|
pr_notice("%s fail! dev:%s, fwspec is NULL\n",
|
|
__func__, dev_name(dev));
|
|
return;
|
|
}
|
|
dom_id = MTK_M4U_TO_DOM(fwspec->ids[0]);
|
|
tab_id = MTK_M4U_TO_TAB(fwspec->ids[0]);
|
|
}
|
|
|
|
/* count iova size by device */
|
|
spin_lock(&iova_list.lock);
|
|
list_for_each_entry_safe(plist, n, &iova_list.head, list_node) {
|
|
size = (unsigned long) (plist->size / 1024);
|
|
if (dev == NULL || (plist->dom_id == dom_id && plist->tab_id == tab_id)) {
|
|
mtk_iommu_count_iova_size(plist->dev, plist->iova, plist->size);
|
|
dom_size += size;
|
|
dom_count++;
|
|
}
|
|
total_size += size;
|
|
total_cnt++;
|
|
}
|
|
spin_unlock(&iova_list.lock);
|
|
|
|
spin_lock(&count_list.lock);
|
|
/* sort count iova size by device */
|
|
list_sort(NULL, &count_list.head, iova_size_cmp);
|
|
|
|
/* dump top max user */
|
|
iommu_dump(s, "iommu iova alloc total:(%d/%lluKB), dom:(%d/%lluKB,%d,%d) top %d user:\n",
|
|
total_cnt, total_size, dom_count, dom_size, tab_id, dom_id, IOVA_DUMP_TOP_MAX);
|
|
iommu_dump(s, "%6s %6s %8s %10s %3s\n", "tab_id", "dom_id", "count", "size", "dev");
|
|
list_for_each_entry_safe(p_count_list, n_count, &count_list.head, list_node) {
|
|
iommu_dump(s, "%6u %6u %8u %8lluKB %s\n",
|
|
p_count_list->tab_id,
|
|
p_count_list->dom_id,
|
|
p_count_list->count,
|
|
p_count_list->size,
|
|
dev_name(p_count_list->dev));
|
|
i++;
|
|
if (i >= IOVA_DUMP_TOP_MAX)
|
|
break;
|
|
}
|
|
|
|
/* clear count iova size */
|
|
mtk_iommu_clear_iova_size();
|
|
|
|
spin_unlock(&count_list.lock);
|
|
}
|
|
|
|
static void mtk_iommu_iova_alloc_dump(struct seq_file *s, struct device *dev)
|
|
{
|
|
struct iommu_fwspec *fwspec = NULL;
|
|
struct iova_info *plist = NULL;
|
|
struct iova_info *n = NULL;
|
|
|
|
if (dev != NULL) {
|
|
fwspec = dev_iommu_fwspec_get(dev);
|
|
if (fwspec == NULL) {
|
|
pr_info("%s fail! dev:%s, fwspec is NULL\n",
|
|
__func__, dev_name(dev));
|
|
return;
|
|
}
|
|
}
|
|
|
|
iommu_dump(s, "iommu iova alloc dump:\n");
|
|
iommu_dump(s, "%6s %6s %18s %8s %3s\n", "tab_id", "dom_id", "iova", "size", "dev");
|
|
|
|
spin_lock(&iova_list.lock);
|
|
list_for_each_entry_safe(plist, n, &iova_list.head, list_node)
|
|
if (dev == NULL || (plist->dom_id == MTK_M4U_TO_DOM(fwspec->ids[0]) &&
|
|
plist->tab_id == MTK_M4U_TO_TAB(fwspec->ids[0])))
|
|
iommu_dump(s, "%6u %6u %18pa %8zx %s\n",
|
|
plist->tab_id,
|
|
plist->dom_id,
|
|
&plist->iova,
|
|
plist->size,
|
|
dev_name(plist->dev));
|
|
spin_unlock(&iova_list.lock);
|
|
}
|
|
|
|
static void mtk_iova_dbg_alloc(struct device *dev, struct iova_domain *iovad,
|
|
dma_addr_t iova, size_t size)
|
|
{
|
|
u32 tab_id;
|
|
struct iova_info *iova_buf;
|
|
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
|
|
|
|
if (!fwspec) {
|
|
pr_info("%s fail, dev(%s) is not iommu-dev\n",
|
|
__func__, dev_name(dev));
|
|
return;
|
|
}
|
|
|
|
tab_id = MTK_M4U_TO_TAB(fwspec->ids[0]);
|
|
|
|
if (!iova) {
|
|
pr_info("%s fail! dev:%s, size:0x%zx\n",
|
|
__func__, dev_name(dev), size);
|
|
|
|
if (tab_id == APU_TABLE)
|
|
mtk_iommu_iova_alloc_dump(NULL, dev);
|
|
|
|
return mtk_iommu_iova_alloc_dump_top(NULL, dev);
|
|
}
|
|
|
|
iova_buf = kzalloc(sizeof(*iova_buf), GFP_ATOMIC);
|
|
if (!iova_buf)
|
|
return;
|
|
|
|
iova_buf->tab_id = tab_id;
|
|
iova_buf->dom_id = MTK_M4U_TO_DOM(fwspec->ids[0]);
|
|
iova_buf->dev = dev;
|
|
iova_buf->iovad = iovad;
|
|
iova_buf->iova = iova;
|
|
iova_buf->size = size;
|
|
spin_lock(&iova_list.lock);
|
|
list_add(&iova_buf->list_node, &iova_list.head);
|
|
spin_unlock(&iova_list.lock);
|
|
|
|
mtk_iommu_iova_trace(IOMMU_ALLOC, iova, size, tab_id, dev);
|
|
}
|
|
|
|
static void mtk_iova_dbg_free(struct iova_domain *iovad, dma_addr_t iova, size_t size)
|
|
{
|
|
struct iova_info *plist;
|
|
struct iova_info *tmp_plist;
|
|
struct device *dev = NULL;
|
|
u32 tab_id = PGTBALE_NUM;
|
|
|
|
spin_lock(&iova_list.lock);
|
|
list_for_each_entry_safe(plist, tmp_plist,
|
|
&iova_list.head, list_node) {
|
|
if (plist->iova == iova && plist->size == size && plist->iovad == iovad) {
|
|
tab_id = plist->tab_id;
|
|
dev = plist->dev;
|
|
list_del(&plist->list_node);
|
|
kfree(plist);
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&iova_list.lock);
|
|
if (tab_id == PGTBALE_NUM)
|
|
pr_warn("%s warnning, iova is not find, iova:0x%lx\n",
|
|
__func__, (unsigned long)iova);
|
|
|
|
mtk_iommu_iova_trace(IOMMU_FREE, iova, size, tab_id, dev);
|
|
}
|
|
|
|
/* all code inside alloc_iova_hook can't be scheduled! */
|
|
static void alloc_iova_hook(void *data, struct device *dev, struct iova_domain *iovad,
|
|
dma_addr_t iova, size_t size)
|
|
{
|
|
return mtk_iova_dbg_alloc(dev, iovad, iova, size);
|
|
}
|
|
|
|
/* all code inside free_iova_hook can't be scheduled! */
|
|
static void free_iova_hook(void *data, struct iova_domain *iovad,
|
|
dma_addr_t iova, size_t size)
|
|
{
|
|
return mtk_iova_dbg_free(iovad, iova, size);
|
|
}
|
|
|
|
static int mtk_m4u_dbg_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
u32 total_port;
|
|
int ret = 0;
|
|
|
|
pr_info("%s start\n", __func__);
|
|
m4u_data = devm_kzalloc(dev, sizeof(struct mtk_m4u_data), GFP_KERNEL);
|
|
if (!m4u_data)
|
|
return -ENOMEM;
|
|
|
|
m4u_data->dev = dev;
|
|
m4u_data->plat_data = of_device_get_match_data(dev);
|
|
total_port = m4u_data->plat_data->port_nr[MM_IOMMU] +
|
|
m4u_data->plat_data->port_nr[APU_IOMMU] +
|
|
m4u_data->plat_data->port_nr[PERI_IOMMU];
|
|
m4u_data->m4u_cb = devm_kzalloc(dev, total_port *
|
|
sizeof(struct mtk_iommu_cb), GFP_KERNEL);
|
|
if (!m4u_data->m4u_cb)
|
|
return -ENOMEM;
|
|
|
|
m4u_debug_init(m4u_data);
|
|
|
|
ret = register_trace_android_vh_iommu_iovad_alloc_iova(alloc_iova_hook,
|
|
"mtk_m4u_dbg_probe");
|
|
pr_debug("add alloc iova hook %s\n", ret ? "fail": "pass");
|
|
ret = register_trace_android_vh_iommu_iovad_free_iova(free_iova_hook,
|
|
"mtk_m4u_dbg_probe");
|
|
pr_debug("add free iova hook %s\n", ret ? "fail": "pass");
|
|
|
|
pr_info("%s done\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static int mt6855_tf_is_gce_videoup(u32 port_tf, u32 vld_tf)
|
|
{
|
|
return F_MMU_INT_TF_LARB(port_tf) ==
|
|
FIELD_GET(GENMASK(12, 8), vld_tf) &&
|
|
F_MMU_INT_TF_PORT(port_tf) ==
|
|
FIELD_GET(GENMASK(1, 0), vld_tf);
|
|
}
|
|
|
|
static int mt6879_tf_is_gce_videoup(u32 port_tf, u32 vld_tf)
|
|
{
|
|
return F_MMU_INT_TF_LARB(port_tf) ==
|
|
FIELD_GET(GENMASK(12, 9), vld_tf) &&
|
|
F_MMU_INT_TF_PORT(port_tf) ==
|
|
FIELD_GET(GENMASK(1, 0), vld_tf);
|
|
}
|
|
|
|
static int mt6983_tf_is_gce_videoup(u32 port_tf, u32 vld_tf)
|
|
{
|
|
return F_MMU_INT_TF_LARB(port_tf) ==
|
|
FIELD_GET(GENMASK(12, 10), vld_tf) &&
|
|
F_MMU_INT_TF_PORT(port_tf) ==
|
|
FIELD_GET(GENMASK(1, 0), vld_tf);
|
|
|
|
}
|
|
|
|
static const struct mtk_m4u_plat_data mt6779_data = {
|
|
.port_list[MM_IOMMU] = iommu_port_mt6779,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(iommu_port_mt6779),
|
|
.mm_tf_ccu_support = 1,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6789_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6789,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6789),
|
|
.mm_tf_ccu_support = 0,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6833_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6853,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6853),
|
|
.mm_tf_ccu_support = 1,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6873_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6873,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6873),
|
|
.port_list[APU_IOMMU] = apu_port_mt6873,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6873),
|
|
.mm_tf_ccu_support = 1,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6853_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6853,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6853),
|
|
.port_list[APU_IOMMU] = apu_port_mt6853,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6853),
|
|
.mm_tf_ccu_support = 1,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6855_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6855,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6855),
|
|
.mm_tf_is_gce_videoup = mt6855_tf_is_gce_videoup,
|
|
.mm_tf_ccu_support = 0,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6893_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6893,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6893),
|
|
.port_list[APU_IOMMU] = apu_port_mt6893,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6893),
|
|
.mm_tf_ccu_support = 1,
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6983_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6983,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6983),
|
|
.port_list[APU_IOMMU] = apu_port_mt6983,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6983),
|
|
.mm_tf_ccu_support = 1,
|
|
.mm_tf_is_gce_videoup = mt6983_tf_is_gce_videoup,
|
|
.peri_data = mt6983_peri_iommu_data,
|
|
.peri_tf_analyse = mt6983_peri_tf,
|
|
.mau_config = mau_config_default,
|
|
.mau_config_nr = ARRAY_SIZE(mau_config_default),
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6879_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6879,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6879),
|
|
.port_list[APU_IOMMU] = apu_port_mt6879,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6879),
|
|
.port_list[PERI_IOMMU] = peri_port_mt6879,
|
|
.port_nr[PERI_IOMMU] = ARRAY_SIZE(peri_port_mt6879),
|
|
.mm_tf_ccu_support = 1,
|
|
.mm_tf_is_gce_videoup = mt6879_tf_is_gce_videoup,
|
|
.mau_config = mau_config_default,
|
|
.mau_config_nr = ARRAY_SIZE(mau_config_default),
|
|
};
|
|
|
|
static const struct mtk_m4u_plat_data mt6895_data = {
|
|
.port_list[MM_IOMMU] = mm_port_mt6895,
|
|
.port_nr[MM_IOMMU] = ARRAY_SIZE(mm_port_mt6895),
|
|
.port_list[APU_IOMMU] = apu_port_mt6895,
|
|
.port_nr[APU_IOMMU] = ARRAY_SIZE(apu_port_mt6895),
|
|
.mm_tf_ccu_support = 1,
|
|
.mm_tf_is_gce_videoup = mt6983_tf_is_gce_videoup,
|
|
.peri_data = mt6983_peri_iommu_data,
|
|
.peri_tf_analyse = mt6983_peri_tf,
|
|
.mau_config = mau_config_default,
|
|
.mau_config_nr = ARRAY_SIZE(mau_config_default),
|
|
};
|
|
|
|
static const struct of_device_id mtk_m4u_dbg_of_ids[] = {
|
|
{ .compatible = "mediatek,mt6779-iommu-debug", .data = &mt6779_data},
|
|
{ .compatible = "mediatek,mt6789-iommu-debug", .data = &mt6789_data},
|
|
{ .compatible = "mediatek,mt6833-iommu-debug", .data = &mt6833_data},
|
|
{ .compatible = "mediatek,mt6853-iommu-debug", .data = &mt6853_data},
|
|
{ .compatible = "mediatek,mt6855-iommu-debug", .data = &mt6855_data},
|
|
{ .compatible = "mediatek,mt6873-iommu-debug", .data = &mt6873_data},
|
|
{ .compatible = "mediatek,mt6879-iommu-debug", .data = &mt6879_data},
|
|
{ .compatible = "mediatek,mt6893-iommu-debug", .data = &mt6893_data},
|
|
{ .compatible = "mediatek,mt6895-iommu-debug", .data = &mt6895_data},
|
|
{ .compatible = "mediatek,mt6983-iommu-debug", .data = &mt6983_data},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver mtk_m4u_dbg_drv = {
|
|
.probe = mtk_m4u_dbg_probe,
|
|
.driver = {
|
|
.name = "mtk-m4u-debug",
|
|
.of_match_table = of_match_ptr(mtk_m4u_dbg_of_ids),
|
|
}
|
|
};
|
|
|
|
module_platform_driver(mtk_m4u_dbg_drv);
|
|
MODULE_LICENSE("GPL v2");
|