mirror of
https://github.com/physwizz/a155-U-u1.git
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174 lines
3.0 KiB
C
174 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_PWM_HAL_H__
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#define __MT_PWM_HAL_H__
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#include <linux/types.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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/*
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* Define macros.
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*/
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#define mt_reg_sync_writel(v, a) \
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do { \
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__raw_writel((v), (void __force __iomem *)((a))); \
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mb(); /*make sure register access in order */ \
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} while (0)
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/**********************************
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* Global enum data
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*/
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/******************* Register Manipulations*****************/
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#define INREG32(reg) __raw_readl((void *)reg)
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#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
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#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
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#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
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#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
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#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
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enum PWN_NO {
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PWM_MIN,
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PWM1 = PWM_MIN,
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PWM2,
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PWM3,
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PWM4,
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PWM5,
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PWM6,
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PWM_NUM,
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PWM_MAX = PWM_NUM
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};
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enum TEST_SEL_BIT {
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TEST_SEL_FALSE,
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TEST_SEL_TRUE
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};
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enum PWM_CON_MODE_BIT {
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PERIOD,
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RAND
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};
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enum PWM_CON_SRCSEL_BIT {
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PWM_FIFO,
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MEMORY
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};
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enum PWM_CON_IDLE_BIT {
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IDLE_FALSE,
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IDLE_TRUE,
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IDLE_MAX
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};
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enum PWM_CON_GUARD_BIT {
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GUARD_FALSE,
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GUARD_TRUE,
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GUARD_MAX
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};
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enum OLD_MODE_BIT {
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OLDMODE_DISABLE,
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OLDMODE_ENABLE
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};
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enum PWM_BUF_VALID_BIT {
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BUF0_VALID,
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BUF0_EN_VALID,
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BUF1_VALID,
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BUF1_EN_VALID,
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BUF_EN_MAX
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};
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enum CLOCK_SRC {
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CLK_BLOCK,
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CLK_BLOCK_BY_1625_OR_32K
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};
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enum PWM_CLK_DIV {
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CLK_DIV_MIN,
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CLK_DIV1 = CLK_DIV_MIN,
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CLK_DIV2,
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CLK_DIV4,
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CLK_DIV8,
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CLK_DIV16,
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CLK_DIV32,
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CLK_DIV64,
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CLK_DIV128,
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CLK_DIV_MAX
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};
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enum PWM_INT_ENABLE_BITS {
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PWM1_INT_FINISH_EN,
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PWM1_INT_UNDERFLOW_EN,
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PWM2_INT_FINISH_EN,
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PWM2_INT_UNDERFLOW_EN,
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PWM3_INT_FINISH_EN,
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PWM3_INT_UNDERFLOW_EN,
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PWM4_INT_FINISH_EN,
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PWM4_INT_UNDERFLOW_EN,
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PWM_INT_ENABLE_BITS_MAX,
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};
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enum PWM_INT_STATUS_BITS {
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PWM1_INT_FINISH_ST,
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PWM1_INT_UNDERFLOW_ST,
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PWM2_INT_FINISH_ST,
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PWM2_INT_UNDERFLOW_ST,
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PWM3_INT_FINISH_ST,
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PWM3_INT_UNDERFLOW_ST,
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PWM4_INT_FINISH_ST,
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PWM4_INT_UNDERFLOW_ST,
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PWM_INT_STATUS_BITS_MAX,
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};
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enum PWM_INT_ACK_BITS {
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PWM1_INT_FINISH_ACK,
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PWM1_INT_UNDERFLOW_ACK,
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PWM2_INT_FINISH_ACK,
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PWM2_INT_UNDERFLOW_ACK,
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PWM3_INT_FINISH_ACK,
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PWM3_INT_UNDERFLOW_ACK,
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PWM4_INT_FINISH_ACK,
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PWM4_INT_UNDERFLOW_ACK,
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PWM_INT_ACK_BITS_MAX,
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};
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enum PWM_CLOCK_SRC_ENUM {
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PWM_CLK_SRC_MIN,
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PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
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PWM_CLK_OLD_MODE_32K,
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PWM_CLK_NEW_MODE_BLOCK,
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PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
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PWM_CLK_SRC_NUM,
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PWM_CLK_SRC_INVALID,
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};
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enum PWM_MODE_ENUM {
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PWM_MODE_MIN,
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PWM_MODE_OLD = PWM_MODE_MIN,
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PWM_MODE_FIFO,
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PWM_MODE_MEMORY,
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PWM_MODE_RANDOM,
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PWM_MODE_DELAY,
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PWM_MODE_INVALID,
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};
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enum INFRA_CLK_SRC_CTRL {
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CLK_32K = 0x00,
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CLK_26M = 0x01,
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CLK_78M = 0x2,
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CLK_SEL_TOPCKGEN = 0x3,
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};
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#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
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void mt_set_pwm_3dlcm_enable_hal(u8 enable);
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void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
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void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
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void mt_pwm_26M_clk_enable_hal(u32 enable);
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#endif
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