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https://github.com/physwizz/a155-U-u1.git
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65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DVFSRC_EXP_H
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#define __DVFSRC_EXP_H
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#define MTK_DVFSRC_NUM_DVFS_OPP 0
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#define MTK_DVFSRC_NUM_DRAM_OPP 1
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#define MTK_DVFSRC_NUM_VCORE_OPP 2
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#define MTK_DVFSRC_CURR_DVFS_OPP 3
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#define MTK_DVFSRC_CURR_DRAM_OPP 4
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#define MTK_DVFSRC_CURR_VCORE_OPP 5
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#define MTK_DVFSRC_CURR_DVFS_LEVEL 6
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#define MTK_DVFSRC_CURR_DRAM_KHZ 7
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#define MTK_DVFSRC_CURR_VCORE_UV 8
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#define MTK_DVFSRC_SW_REQ_VCORE_OPP 9
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#if IS_ENABLED(CONFIG_MTK_DVFSRC)
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extern u32 dvfsrc_get_required_opp_peak_bw(struct device_node *np,
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int index);
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#else
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static inline u32 dvfsrc_get_required_opp_peak_bw(struct device_node *np,
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int index)
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{ return 0; }
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#endif /* CONFIG_MTK_DVFSRC */
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#if IS_ENABLED(CONFIG_MTK_DVFSRC_HELPER)
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extern int mtk_dvfsrc_query_opp_info(u32 id);
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extern int mtk_dvfsrc_vcore_uv_table(u32 opp);
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#else
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static inline int mtk_dvfsrc_query_opp_info(u32 id)
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{ return 0; }
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static inline int mtk_dvfsrc_vcore_uv_table(u32 opp)
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{ return 0; }
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#endif /* CONFIG_MTK_DVFSRC_HELPER */
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#if IS_ENABLED(CONFIG_MTK_DVFSRC_MET)
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/* for MET */
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extern int vcorefs_get_num_opp(void);
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extern int vcorefs_get_opp_info_num(void);
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extern int vcorefs_get_src_req_num(void);
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extern char **vcorefs_get_opp_info_name(void);
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extern unsigned int *vcorefs_get_opp_info(void);
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extern char **vcorefs_get_src_req_name(void);
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extern unsigned int *vcorefs_get_src_req(void);
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#else
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/* for MET */
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static inline int vcorefs_get_num_opp(void)
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{ return 0; }
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static inline int vcorefs_get_opp_info_num(void)
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{ return 0; }
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static inline int vcorefs_get_src_req_num(void)
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{ return 0; }
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static inline char **vcorefs_get_opp_info_name(void)
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{ return NULL; }
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static inline unsigned int *vcorefs_get_opp_info(void)
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{ return NULL; }
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static inline char **vcorefs_get_src_req_name(void)
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{ return NULL; }
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static inline unsigned int *vcorefs_get_src_req(void)
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{ return NULL; }
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#endif /* CONFIG_MTK_DVFSRC_MET */
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#endif
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