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238 lines
4.1 KiB
C
238 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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/**
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* @file mtk_eemg_internal.c
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* @brief Driver for EEM
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*
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*/
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#define __MTK_EEMG_INTERNAL_C__
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#include "mtk_eemgpu_config.h"
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#include "mtk_eemgpu.h"
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#include "mtk_eemgpu_internal_ap.h"
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#include "mtk_eemgpu_internal.h"
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/**
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* EEM controllers
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*/
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struct eemg_ctrl eemg_ctrls[NR_EEMG_CTRL] = {
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[EEMG_CTRL_GPU] = {
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.name = __stringify(EEMG_CTRL_GPU),
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.det_id = EEMG_DET_GPU,
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},
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[EEMG_CTRL_GPU_HI] = {
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.name = __stringify(EEMG_CTRL_GPU_HI),
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.det_id = EEMG_DET_GPU_HI,
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},
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};
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#define BASE_OP(fn) .fn = base_ops_ ## fn
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struct eemg_det_ops eemg_det_base_ops = {
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BASE_OP(enable_gpu),
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BASE_OP(disable_gpu),
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BASE_OP(disable_locked_gpu),
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BASE_OP(switch_bank_gpu),
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BASE_OP(init01_gpu),
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BASE_OP(init02_gpu),
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BASE_OP(mon_mode_gpu),
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BASE_OP(get_status_gpu),
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BASE_OP(dump_status_gpu),
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BASE_OP(set_phase_gpu),
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BASE_OP(get_temp_gpu),
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BASE_OP(get_volt_gpu),
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BASE_OP(set_volt_gpu),
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BASE_OP(restore_default_volt_gpu),
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BASE_OP(get_freq_table_gpu),
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BASE_OP(get_orig_volt_table_gpu),
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/* platform independent code */
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BASE_OP(volt_2_pmic_gpu),
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BASE_OP(volt_2_eemg),
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BASE_OP(pmic_2_volt_gpu),
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BASE_OP(eemg_2_pmic),
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};
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struct eemg_det eemg_detectors[NR_EEMG_DET] = {
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[EEMG_DET_GPU] = {
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.name = __stringify(EEMG_DET_GPU),
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.ops = &gpu_det_ops,
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.ctrl_id = EEMG_CTRL_GPU,
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.features = FEA_INIT02,
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.VMAX = VMAX_VAL_GPU,
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.VBOOT = VBOOT_VAL, /* 10uV */
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.VMIN = VMIN_VAL_GPU,
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.eemg_v_base = EEMG_V_BASE,
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.eemg_step = EEMG_STEP,
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.pmic_base = GPU_PMIC_BASE,
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.pmic_step = GPU_PMIC_STEP,
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.DETWINDOW = DETWINDOW_VAL,
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.DTHI = DTHI_VAL,
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.DTLO = DTLO_VAL,
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.DETMAX = DETMAX_VAL,
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.AGECONFIG = AGECONFIG_VAL,
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.AGEM = AGEM_VAL,
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.loo_role = LOW_BANK,
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.loo_couple = EEMG_CTRL_GPU_HI,
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.loo_mutex = &gpu_mutex_g,
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.DVTFIXED = DVTFIXED_VAL_GL,
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.turn_pt = BANK_GPU_TURN_PT,
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.VCO = VCO_VAL_GL,
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.DCCONFIG = DCCONFIG_VAL,
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.EEMCTL0 = EEMG_CTL0_GPU,
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.low_temp_off = LOW_TEMP_OFF_GPU,
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.high_temp_off = HIGH_TEMP_OFF_GPU,
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.volt_policy = 1,
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},
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[EEMG_DET_GPU_HI] = {
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.name = __stringify(EEMG_DET_GPU_HI),
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.ops = &gpu_det_ops,
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.ctrl_id = EEMG_CTRL_GPU_HI,
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.features = FEA_INIT02 | FEA_MON,
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.VBOOT = VBOOT_VAL, /* 10uV */
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.VMAX = VMAX_VAL_GH,
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.VMIN = VMIN_VAL_GH,
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.eemg_v_base = EEMG_V_BASE,
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.eemg_step = EEMG_STEP,
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.pmic_base = CPU_PMIC_BASE_6359,
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.pmic_step = CPU_PMIC_STEP,
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.DETWINDOW = DETWINDOW_VAL,
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.DTHI = DTHI_VAL,
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.DTLO = DTLO_VAL,
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.DETMAX = DETMAX_VAL,
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.AGECONFIG = AGECONFIG_VAL,
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.AGEM = AGEM_VAL,
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.DVTFIXED = DVTFIXED_VAL_GPU,
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.loo_role = HIGH_BANK,
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.loo_couple = EEMG_CTRL_GPU,
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.loo_mutex = &gpu_mutex_g,
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.turn_pt = BANK_GPU_TURN_PT,
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.VCO = VCO_VAL_GH,
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.DCCONFIG = DCCONFIG_VAL,
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.EEMCTL0 = EEMG_CTL0_GPU,
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.low_temp_off = LOW_TEMP_OFF_GPU,
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.high_temp_off = HIGH_TEMP_OFF_GPU,
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.volt_policy = 1,
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},
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};
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#if DUMP_DATA_TO_DE
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const unsigned int reg_gpu_addr_off[DUMP_LEN] = {
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0x0000,
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0x0004,
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0x0008,
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0x000C,
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0x0010,
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0x0014,
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0x0018,
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0x001c,
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0x0024,
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0x0028,
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0x002c,
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0x0030,
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0x0034,
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0x0038,
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0x003c,
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0x0040,
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0x0044,
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0x0048,
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0x004c,
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0x0050,
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0x0054,
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0x0058,
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0x005c,
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0x0060,
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0x0064,
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0x0068,
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0x006c,
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0x0070,
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0x0074,
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0x0078,
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0x007c,
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0x0080,
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0x0084,
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0x0088,
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0x008c,
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0x0090,
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0x0094,
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0x0098,
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0x00a0,
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0x00a4,
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0x00a8,
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0x00B0,
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0x00B4,
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0x00B8,
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0x00BC,
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0x00C0,
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0x00C4,
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0x00C8,
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0x00CC,
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0x00F0,
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0x00F4,
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0x00F8,
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0x00FC,
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0x0190, /* dump this for gpu thermal */
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0x0194, /* dump this for gpu thermal */
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0x0198, /* dump this for gpu thermal */
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0x01B8, /* dump this for gpu thermal */
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0x0C00,
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0x0C04,
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0x0C08,
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0x0C0C,
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0x0C10,
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0x0C14,
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0x0C18,
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0x0C1C,
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0x0C20,
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0x0C24,
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0x0C28,
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0x0C2C,
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0x0C30,
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0x0C34,
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0x0C38,
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0x0C3C,
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0x0C40,
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0x0C44,
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0x0C48,
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0x0C4C,
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0x0C50,
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0x0C54,
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0x0C58,
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0x0C5C,
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0x0C60,
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0x0C64,
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0x0C68,
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0x0C6C,
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0x0C70,
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0x0C74,
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0x0C78,
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0x0C7C,
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0x0C80,
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0x0C84,
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0x0C88, /* dump thermal sensor */
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0x0F00,
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0x0F04,
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0x0F08,
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0x0F0C,
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0x0F10,
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0x0F14,
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0x0F18,
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0x0F1C,
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0x0F20,
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0x0F24,
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0x0F28,
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0x0F2C,
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0x0F30,
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};
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#endif
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#undef __MT_EEMG_INTERNAL_C__
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