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https://github.com/physwizz/a155-U-u1.git
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94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 MediaTek Inc.
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*/
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#ifndef __CCIF_HIF_PLATFORM_H__
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#define __CCIF_HIF_PLATFORM_H__
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#include <linux/io.h>
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#define ccif_write16(b, a, v) \
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do {\
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writew(v, (b) + (a));\
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mb(); /* make sure register access in order */ \
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} while (0)
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#define ccif_write8(b, a, v) \
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do {\
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writeb(v, (b) + (a));\
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mb(); /* make sure register access in order */ \
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} while (0)
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#define ccif_read16(b, a) ioread16((void __iomem *)((b)+(a)))
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#define ccif_read8(b, a) ioread8((void __iomem *)((b)+(a)))
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int ccif_read32(void *b, unsigned long a);
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void ccif_write32(void *b, unsigned long a, unsigned int v);
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/*CCIF */
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#define APCCIF_CON (0x00)
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#define APCCIF_BUSY (0x04)
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#define APCCIF_START (0x08)
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#define APCCIF_TCHNUM (0x0C)
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#define APCCIF_RCHNUM (0x10)
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#define APCCIF_ACK (0x14)
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#define APCCIF_IRQ0_MASK (0x20)
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#define APCCIF_IRQ1_MASK (0x24)
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#define APCCIF_CHDATA (0x100)
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#define RINGQ_BASE (0)
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#define RINGQ_SRAM (15)
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#define RINGQ_EXP_BASE (15)
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#define CCIF_CH_NUM 24
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#define AP_MD_CCB_WAKEUP (7)
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/*AP to MD*/
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#define H2D_EXCEPTION_ACK (RINGQ_EXP_BASE+1)
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#define H2D_EXCEPTION_CLEARQ_ACK (RINGQ_EXP_BASE+2)
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#define H2D_FORCE_MD_ASSERT (RINGQ_EXP_BASE+3)
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#define H2D_MPU_FORCE_ASSERT (RINGQ_EXP_BASE+4)
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#define H2D_SRAM (RINGQ_SRAM)
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#define H2D_RINGQ0 (RINGQ_BASE+0)
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#define H2D_RINGQ1 (RINGQ_BASE+1)
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#define H2D_RINGQ2 (RINGQ_BASE+2)
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#define H2D_RINGQ3 (RINGQ_BASE+3)
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#define H2D_RINGQ4 (RINGQ_BASE+4)
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#define H2D_RINGQ5 (RINGQ_BASE+5)
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#define H2D_RINGQ6 (RINGQ_BASE+6)
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#define H2D_RINGQ7 (RINGQ_BASE+7)
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/*MD to AP*/
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#define CCIF_HW_CH_RX_RESERVED \
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((1 << (RINGQ_EXP_BASE+0)) | (1 << (RINGQ_EXP_BASE+5)))
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#define D2H_EXCEPTION_INIT (RINGQ_EXP_BASE+1)
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#define D2H_EXCEPTION_INIT_DONE (RINGQ_EXP_BASE+2)
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#define D2H_EXCEPTION_CLEARQ_DONE (RINGQ_EXP_BASE+3)
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#define D2H_EXCEPTION_ALLQ_RESET (RINGQ_EXP_BASE+4)
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#define AP_MD_PEER_WAKEUP (RINGQ_EXP_BASE+5)
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#define AP_MD_SEQ_ERROR (RINGQ_EXP_BASE+6)
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#define AP_MD_DATA_NOTIFY (RINGQ_EXP_BASE+8)
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#define D2H_SRAM (RINGQ_SRAM)
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#define D2H_RINGQ0 (RINGQ_BASE+0)
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#define D2H_RINGQ1 (RINGQ_BASE+1)
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#define D2H_RINGQ2 (RINGQ_BASE+2)
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#define D2H_RINGQ3 (RINGQ_BASE+3)
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#define D2H_RINGQ4 (RINGQ_BASE+4)
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#define D2H_RINGQ5 (RINGQ_BASE+5)
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#define D2H_RINGQ6 (RINGQ_BASE+6)
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#define D2H_RINGQ7 (RINGQ_BASE+7)
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#define CCIF_SRAM_SIZE 512
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/* use hw_channel = usr_id + AP_MD_DATA_NOTIFY */
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enum ccif_isr_cb_user_id {
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ID_CCIF_USER_DATA = 0,
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ID_CCIF_CB_MAX,
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};
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#endif /*__CCIF_HIF_PLATFORM_H__*/
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