mirror of
https://github.com/physwizz/a155-U-u1.git
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859 lines
25 KiB
C
859 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include <linux/io.h>
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#include <mt6789_dcm_internal.h>
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#include <mt6789_dcm_autogen.h>
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#include <mtk_dcm.h>
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/*====================auto gen code 20211130_181259=====================*/
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#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK ((0x1f << 12) | \
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(0x1 << 17) | \
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(0x1 << 18))
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#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON ((0x10 << 12) | \
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(0x1 << 17) | \
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(0x0 << 18))
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#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_OFF ((0x10 << 12) | \
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(0x0 << 17) | \
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(0x1 << 18))
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bool dcm_infracfg_ao_aximem_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
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INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_aximem_bus_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_aximem_bus_dcm'" */
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reg_write(INFRA_AXIMEM_IDLE_BIT_EN_0,
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(reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
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~INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_aximem_bus_dcm'" */
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reg_write(INFRA_AXIMEM_IDLE_BIT_EN_0,
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(reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
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~INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_AXIMEM_BUS_DCM_REG0_OFF);
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}
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}
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#define INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 3) | \
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(0x1 << 4) | \
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(0x1f << 5) | \
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(0x1 << 20) | \
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(0x1 << 23) | \
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(0x1 << 30))
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#define INFRACFG_AO_INFRA_BUS_DCM_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x10 << 5) | \
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(0x1 << 20) | \
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(0x1 << 23) | \
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(0x1 << 30))
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#define INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 3) | \
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(0x1 << 4) | \
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(0x10 << 5) | \
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(0x0 << 20) | \
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(0x0 << 23) | \
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(0x0 << 30))
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static void infracfg_ao_infra_dcm_rg_sfsel_set(unsigned int val)
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{
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~(0x1f << 10)) |
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(val & 0x1f) << 10);
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}
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bool dcm_infracfg_ao_infra_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(INFRA_BUS_DCM_CTRL) &
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INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_infra_bus_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_infra_bus_dcm'" */
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infracfg_ao_infra_dcm_rg_sfsel_set(0x1);
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_bus_dcm'" */
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infracfg_ao_infra_dcm_rg_sfsel_set(0x1);
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF);
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}
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}
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG2_MASK ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON ((0x0 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG2_ON ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_OFF ((0x0 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_OFF ((0x1 << 8))
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#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG2_OFF ((0x0 << 8))
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bool dcm_infracfg_ao_infra_conn_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(MODULE_SW_CG_2_STA) &
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INFRACFG_AO_INFRA_CONN_BUS_DCM_REG2_MASK) ==
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(unsigned int) INFRACFG_AO_INFRA_CONN_BUS_DCM_REG2_ON);
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return ret;
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}
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void dcm_infracfg_ao_infra_conn_bus_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_infra_conn_bus_dcm'" */
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reg_write(MODULE_SW_CG_2_SET,
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(reg_read(MODULE_SW_CG_2_SET) &
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~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_conn_bus_dcm'" */
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reg_write(MODULE_SW_CG_2_CLR,
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(reg_read(MODULE_SW_CG_2_CLR) &
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~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK) |
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INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_OFF);
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}
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}
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#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK ((0xf << 0))
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#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON ((0x0 << 0))
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#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_OFF ((0xf << 0))
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bool dcm_infracfg_ao_infra_rx_p2p_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(P2P_RX_CLK_ON) &
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INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_infra_rx_p2p_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_infra_rx_p2p_dcm'" */
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reg_write(P2P_RX_CLK_ON,
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(reg_read(P2P_RX_CLK_ON) &
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~INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) |
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INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_rx_p2p_dcm'" */
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reg_write(P2P_RX_CLK_ON,
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(reg_read(P2P_RX_CLK_ON) &
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~INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) |
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INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_OFF);
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}
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}
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#define INFRACFG_AO_PERI_BUS_DCM_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 3) | \
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(0x1 << 4) | \
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(0x1f << 5) | \
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(0x1f << 15) | \
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(0x1 << 20) | \
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(0x1 << 21))
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#define INFRACFG_AO_PERI_BUS_DCM_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x1f << 5) | \
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(0x1f << 15) | \
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(0x1 << 20) | \
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(0x1 << 21))
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#define INFRACFG_AO_PERI_BUS_DCM_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 3) | \
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(0x1 << 4) | \
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(0x1f << 5) | \
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(0x0 << 15) | \
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(0x0 << 20) | \
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(0x0 << 21))
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static void infracfg_ao_peri_dcm_rg_sfsel_set(unsigned int val)
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{
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~(0x1f << 10)) |
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(val & 0x1f) << 10);
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}
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bool dcm_infracfg_ao_peri_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
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INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_peri_bus_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_peri_bus_dcm'" */
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infracfg_ao_peri_dcm_rg_sfsel_set(0x0);
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_peri_bus_dcm'" */
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infracfg_ao_peri_dcm_rg_sfsel_set(0x1f);
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) |
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INFRACFG_AO_PERI_BUS_DCM_REG0_OFF);
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}
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}
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#define INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK ((0x1 << 29) | \
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(0x1 << 31))
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#define INFRACFG_AO_PERI_MODULE_DCM_REG0_ON ((0x1 << 29) | \
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(0x1 << 31))
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#define INFRACFG_AO_PERI_MODULE_DCM_REG0_OFF ((0x0 << 29) | \
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(0x0 << 31))
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bool dcm_infracfg_ao_peri_module_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
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INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_peri_module_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_peri_module_dcm'" */
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) |
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INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_peri_module_dcm'" */
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) |
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INFRACFG_AO_PERI_MODULE_DCM_REG0_OFF);
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}
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}
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 28))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK ((0x1f << 5))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK ((0x1 << 22))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 28))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON ((0x0 << 5))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON ((0x1 << 22))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_OFF ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x0 << 28))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_OFF ((0x0 << 5))
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#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_OFF ((0x0 << 22))
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bool dcm_infra_ao_bcrm_infra_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) ==
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(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON);
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ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) ==
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(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON);
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ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_9) &
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) ==
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(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON);
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return ret;
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}
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void dcm_infra_ao_bcrm_infra_bus_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infra_ao_bcrm_infra_bus_dcm'" */
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON);
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON);
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_9,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_9) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infra_ao_bcrm_infra_bus_dcm'" */
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_OFF);
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_OFF);
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reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_9,
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(reg_read(
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VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_9) &
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~INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) |
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INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_OFF);
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}
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}
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK ((0x1 << 26))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK ((0x1f << 5))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG2_MASK ((0x1 << 12))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON ((0x1 << 26))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON ((0x0 << 5))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG2_ON ((0x1 << 12))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_OFF ((0x0 << 26))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_OFF ((0x0 << 5))
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#define INFRA_AO_BCRM_PERI_BUS_DCM_REG2_OFF ((0x0 << 12))
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bool dcm_infra_ao_bcrm_peri_bus_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
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|
INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) ==
|
|
(unsigned int) INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON);
|
|
ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) ==
|
|
(unsigned int) INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON);
|
|
ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10) &
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG2_MASK) ==
|
|
(unsigned int) INFRA_AO_BCRM_PERI_BUS_DCM_REG2_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_infra_ao_bcrm_peri_bus_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'infra_ao_bcrm_peri_bus_dcm'" */
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON);
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON);
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG2_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG2_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'infra_ao_bcrm_peri_bus_dcm'" */
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG0_OFF);
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG1_OFF);
|
|
reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10,
|
|
(reg_read(
|
|
VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10) &
|
|
~INFRA_AO_BCRM_PERI_BUS_DCM_REG2_MASK) |
|
|
INFRA_AO_BCRM_PERI_BUS_DCM_REG2_OFF);
|
|
}
|
|
}
|
|
|
|
#define MCUSYS_PAR_WRAP_BIG_DCM_REG0_MASK ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 0) | \
|
|
(0x1 << 1))
|
|
#define MCUSYS_PAR_WRAP_BIG_DCM_REG0_ON ((0x0 << 0) | \
|
|
(0x0 << 1) | \
|
|
(0x0 << 0) | \
|
|
(0x0 << 1))
|
|
#define MCUSYS_PAR_WRAP_BIG_DCM_REG0_OFF ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 0) | \
|
|
(0x1 << 1))
|
|
|
|
bool dcm_mcusys_par_wrap_big_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MCUSYS_PAR_WRAP_STALL_DCM_CONF) &
|
|
MCUSYS_PAR_WRAP_BIG_DCM_REG0_MASK) ==
|
|
(unsigned int) MCUSYS_PAR_WRAP_BIG_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcusys_par_wrap_big_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcusys_par_wrap_big_dcm'" */
|
|
reg_write(MCUSYS_PAR_WRAP_STALL_DCM_CONF,
|
|
(reg_read(MCUSYS_PAR_WRAP_STALL_DCM_CONF) &
|
|
~MCUSYS_PAR_WRAP_BIG_DCM_REG0_MASK) |
|
|
MCUSYS_PAR_WRAP_BIG_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcusys_par_wrap_big_dcm'" */
|
|
reg_write(MCUSYS_PAR_WRAP_STALL_DCM_CONF,
|
|
(reg_read(MCUSYS_PAR_WRAP_STALL_DCM_CONF) &
|
|
~MCUSYS_PAR_WRAP_BIG_DCM_REG0_MASK) |
|
|
MCUSYS_PAR_WRAP_BIG_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK ((0x1 << 17))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK ((0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 18) | \
|
|
(0x1 << 21))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK ((0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 18))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON ((0x1 << 17))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON ((0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 18) | \
|
|
(0x1 << 21))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON ((0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 18))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
|
|
(0x0 << 16) | \
|
|
(0x0 << 17) | \
|
|
(0x0 << 18) | \
|
|
(0x0 << 21))
|
|
#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
|
|
(0x0 << 16) | \
|
|
(0x0 << 17) | \
|
|
(0x0 << 18))
|
|
|
|
bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
|
|
MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
|
|
MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_adb_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
|
|
reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
|
|
(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
|
|
reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
|
|
reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
|
|
(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
|
|
reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) |
|
|
MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK ((0x1 << 5))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK ((0x1 << 8))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK ((0x1 << 16))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG0_ON ((0x1 << 5))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG1_ON ((0x1 << 8))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG2_ON ((0x1 << 16))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
|
|
#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
|
|
|
|
bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
|
|
MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
|
|
MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_apb_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG0_ON);
|
|
reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG1_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG1_ON);
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG2_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG2_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
|
|
reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG1_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
|
|
~MP_CPUSYS_TOP_APB_DCM_REG2_MASK) |
|
|
MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK ((0x1 << 0))
|
|
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON ((0x1 << 0))
|
|
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
|
|
|
|
bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_core_stall_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
~MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
~MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
|
|
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
|
|
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
|
|
|
|
bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
|
|
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_cpubiu_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MCSIC_DCM0,
|
|
(reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
|
|
~MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MCSIC_DCM0,
|
|
(reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
|
|
~MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK ((0x1 << 4))
|
|
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON ((0x1 << 4))
|
|
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
|
|
|
|
bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_fcm_stall_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
~MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
|
|
reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
|
|
(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
|
|
~MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) |
|
|
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1 << 31))
|
|
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1 << 31))
|
|
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0 << 31))
|
|
|
|
bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
|
|
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
|
|
(unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mp_cpusys_top_last_cor_idle_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
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reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
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(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
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~MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) |
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MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
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reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
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(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
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~MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) |
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MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
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}
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}
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#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK ((0x1 << 1) | \
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(0x1 << 4))
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#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON ((0x1 << 1) | \
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(0x1 << 4))
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#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
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(0x0 << 4))
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bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
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(unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
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return ret;
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}
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void dcm_mp_cpusys_top_misc_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
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reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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~MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) |
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MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
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reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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~MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) |
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MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
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}
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}
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#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK ((0x1 << 3))
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#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 3))
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#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON ((0x1 << 3))
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#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 3))
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#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
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#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 2) | \
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(0x0 << 3))
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bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
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(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
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ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
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MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
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(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
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return ret;
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}
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void dcm_mp_cpusys_top_mp0_qdcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
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reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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~MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) |
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MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
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reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
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~MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) |
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MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
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reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
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~MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) |
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MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
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reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
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(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
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~MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) |
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MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
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}
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}
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#define CPCCFG_REG_EMI_WFIFO_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 3))
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#define CPCCFG_REG_EMI_WFIFO_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 3))
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#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 2) | \
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(0x0 << 3))
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bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(CPCCFG_REG_EMI_WFIFO) &
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CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
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(unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
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return ret;
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}
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void dcm_cpccfg_reg_emi_wfifo(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
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reg_write(CPCCFG_REG_EMI_WFIFO,
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(reg_read(CPCCFG_REG_EMI_WFIFO) &
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~CPCCFG_REG_EMI_WFIFO_REG0_MASK) |
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CPCCFG_REG_EMI_WFIFO_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
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reg_write(CPCCFG_REG_EMI_WFIFO,
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(reg_read(CPCCFG_REG_EMI_WFIFO) &
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~CPCCFG_REG_EMI_WFIFO_REG0_MASK) |
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CPCCFG_REG_EMI_WFIFO_REG0_OFF);
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}
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}
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