mirror of
https://github.com/physwizz/a155-U-u1.git
synced 2025-10-07 10:09:34 +00:00
250 lines
13 KiB
C
250 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_DCM_AUTOGEN_H__
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#define __MTK_DCM_AUTOGEN_H__
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#include <mtk_dcm.h>
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#if defined(__KERNEL__) && defined(CONFIG_OF)
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/* TODO: Fix all base addresses. */
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extern unsigned long dcm_infracfg_ao_base;
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extern unsigned long dcm_infracfg_ao_mem_base;
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extern unsigned long dcm_infra_ao_bcrm_base;
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extern unsigned long dcm_emi_base;
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extern unsigned long dcm_dramc_ch0_top0_base;
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extern unsigned long dcm_chn0_emi_base;
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extern unsigned long dcm_dramc_ch0_top5_base;
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extern unsigned long dcm_dramc_ch1_top0_base;
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extern unsigned long dcm_dramc_ch1_top5_base;
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extern unsigned long dcm_sspm_base;
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extern unsigned long dcm_audio_base;
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extern unsigned long dcm_mp_cpusys_top_base;
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extern unsigned long dcm_cpccfg_reg_base;
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#ifndef USE_DRAM_API_INSTEAD
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extern unsigned long dcm_ddrphy1_ao_base;
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#endif /* #ifndef USE_DRAM_API_INSTEAD */
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#define INFRACFG_AO_BASE (dcm_infracfg_ao_base)
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#define INFRACFG_AO_MEM_BASE (dcm_infracfg_ao_mem_base)
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#define INFRA_AO_BCRM_BASE (dcm_infra_ao_bcrm_base)
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#define EMI_BASE (dcm_emi_base)
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#define DRAMC_CH0_TOP0_BASE (dcm_dramc_ch0_top0_base)
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#define CHN0_EMI_BASE (dcm_chn0_emi_base)
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#define DRAMC_CH0_TOP5_BASE (dcm_dramc_ch0_top5_base)
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#define DRAMC_CH1_TOP0_BASE (dcm_dramc_ch1_top0_base)
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#define DRAMC_CH1_TOP5_BASE (dcm_dramc_ch1_top5_base)
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#define SSPM_BASE (dcm_sspm_base)
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#define AUDIO_BASE (dcm_audio_base)
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#define MP_CPUSYS_TOP_BASE (dcm_mp_cpusys_top_base)
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#define CPCCFG_REG_BASE (dcm_cpccfg_reg_base)
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#else /* !(defined(__KERNEL__) && defined(CONFIG_OF)) */
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/* Here below used in CTP and lk for references. */
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#undef INFRACFG_AO_BASE
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#undef INFRACFG_AO_MEM_BASE
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#undef INFRA_AO_BCRM_BASE
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#undef EMI_BASE
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#undef DRAMC_CH0_TOP0_BASE
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#undef CHN0_EMI_BASE
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#undef DRAMC_CH0_TOP5_BASE
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#undef DRAMC_CH1_TOP0_BASE
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#undef DRAMC_CH1_TOP5_BASE
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#undef SSPM_BASE
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#undef AUDIO_BASE
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#undef MP_CPUSYS_TOP_BASE
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#undef CPCCFG_REG_BASE
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/* Base */
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#define INFRACFG_AO_BASE 0x10001000
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#define INFRACFG_AO_MEM_BASE 0x10002000
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#define INFRA_AO_BCRM_BASE 0x10022000
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#define EMI_BASE 0x10219000
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#define DRAMC_CH0_TOP0_BASE 0x10230000
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#define CHN0_EMI_BASE 0x10235000
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#define DRAMC_CH0_TOP5_BASE 0x10238000
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#define DRAMC_CH1_TOP0_BASE 0x10240000
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#define DRAMC_CH1_TOP5_BASE 0x10248000
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#define SSPM_BASE 0x10400000
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#define AUDIO_BASE 0x11210000
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#define MP_CPUSYS_TOP_BASE 0xc538000
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#define CPCCFG_REG_BASE 0xc53a800
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#endif
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/* Register Definition */
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#define AUDIO_TOP_CON0 (AUDIO_BASE + 0x0)
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#define CHN0_EMI_CHN_EMI_CONB (CHN0_EMI_BASE + 0x8)
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#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
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#define DRAMC_CH0_TOP0_ACTIMING_CTRL (DRAMC_CH0_TOP0_BASE + 0x190)
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#define DRAMC_CH0_TOP0_CLKAR (DRAMC_CH0_TOP0_BASE + 0x260)
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#define DRAMC_CH0_TOP0_CMD_DEC_CTRL0 (DRAMC_CH0_TOP0_BASE + 0x21c)
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#define DRAMC_CH0_TOP0_DCM_CTRL0 (DRAMC_CH0_TOP0_BASE + 0x200)
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#define DRAMC_CH0_TOP0_DDRCOMMON0 (DRAMC_CH0_TOP0_BASE + 0x0)
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#define DRAMC_CH0_TOP0_DRAMC_PD_CTRL (DRAMC_CH0_TOP0_BASE + 0x1fc)
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#define DRAMC_CH0_TOP0_DUMMY_RD (DRAMC_CH0_TOP0_BASE + 0x110)
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#define DRAMC_CH0_TOP0_DVFS_CTRL0 (DRAMC_CH0_TOP0_BASE + 0x208)
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#define DRAMC_CH0_TOP0_MISCTL0 (DRAMC_CH0_TOP0_BASE + 0x250)
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#define DRAMC_CH0_TOP0_RX_CG_SET0 (DRAMC_CH0_TOP0_BASE + 0x244)
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#define DRAMC_CH0_TOP0_SCSMCTRL_CG (DRAMC_CH0_TOP0_BASE + 0x288)
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#define DRAMC_CH0_TOP0_SHU_APHY_TX_PICG_CTRL (DRAMC_CH0_TOP0_BASE + 0x16ac)
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#define DRAMC_CH0_TOP0_SREF_DPD_CTRL (DRAMC_CH0_TOP0_BASE + 0x168)
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#define DRAMC_CH0_TOP0_TEST2_A0 (DRAMC_CH0_TOP0_BASE + 0x100)
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#define DRAMC_CH0_TOP0_TEST2_A3 (DRAMC_CH0_TOP0_BASE + 0x108)
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#define DRAMC_CH0_TOP0_TX_CG_SET0 (DRAMC_CH0_TOP0_BASE + 0x23c)
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#define DRAMC_CH0_TOP0_TX_TRACKING_SET0 (DRAMC_CH0_TOP0_BASE + 0x1b0)
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#define DRAMC_CH0_TOP0_ZQ_SET0 (DRAMC_CH0_TOP0_BASE + 0x1a0)
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#define DRAMC_CH0_TOP5_MISC_CG_CTRL0 (DRAMC_CH0_TOP5_BASE + 0x4ec)
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#define DRAMC_CH0_TOP5_MISC_CG_CTRL2 (DRAMC_CH0_TOP5_BASE + 0x4f4)
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#define DRAMC_CH0_TOP5_MISC_CG_CTRL5 (DRAMC_CH0_TOP5_BASE + 0x500)
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#define DRAMC_CH0_TOP5_MISC_CTRL3 (DRAMC_CH0_TOP5_BASE + 0x648)
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#define DRAMC_CH0_TOP5_MISC_CTRL4 (DRAMC_CH0_TOP5_BASE + 0x64c)
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#define DRAMC_CH0_TOP5_MISC_DUTYSCAN1 (DRAMC_CH0_TOP5_BASE + 0x624)
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#define DRAMC_CH0_TOP5_MISC_RX_AUTOK_CFG0 (DRAMC_CH0_TOP5_BASE + 0x670)
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#define DRAMC_CH0_TOP5_MISC_SHU_CG_CTRL0 (DRAMC_CH0_TOP5_BASE + 0xda4)
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#define DRAMC_CH0_TOP5_MISC_SHU_RX_CG_CTRL (DRAMC_CH0_TOP5_BASE + 0xda0)
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#define DRAMC_CH0_TOP5_SHU_B0_DQ7 (DRAMC_CH0_TOP5_BASE + 0x884)
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#define DRAMC_CH0_TOP5_SHU_B0_DQ8 (DRAMC_CH0_TOP5_BASE + 0x888)
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#define DRAMC_CH0_TOP5_SHU_B1_DQ7 (DRAMC_CH0_TOP5_BASE + 0xa04)
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#define DRAMC_CH0_TOP5_SHU_B1_DQ8 (DRAMC_CH0_TOP5_BASE + 0xa08)
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#define DRAMC_CH0_TOP5_SHU_CA_CMD8 (DRAMC_CH0_TOP5_BASE + 0xb88)
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#define DRAMC_CH1_TOP0_ACTIMING_CTRL (DRAMC_CH1_TOP0_BASE + 0x190)
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#define DRAMC_CH1_TOP0_CLKAR (DRAMC_CH1_TOP0_BASE + 0x260)
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#define DRAMC_CH1_TOP0_CMD_DEC_CTRL0 (DRAMC_CH1_TOP0_BASE + 0x21c)
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#define DRAMC_CH1_TOP0_DCM_CTRL0 (DRAMC_CH1_TOP0_BASE + 0x200)
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#define DRAMC_CH1_TOP0_DDRCOMMON0 (DRAMC_CH1_TOP0_BASE + 0x0)
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#define DRAMC_CH1_TOP0_DRAMC_PD_CTRL (DRAMC_CH1_TOP0_BASE + 0x1fc)
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#define DRAMC_CH1_TOP0_DUMMY_RD (DRAMC_CH1_TOP0_BASE + 0x110)
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#define DRAMC_CH1_TOP0_DVFS_CTRL0 (DRAMC_CH1_TOP0_BASE + 0x208)
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#define DRAMC_CH1_TOP0_MISCTL0 (DRAMC_CH1_TOP0_BASE + 0x250)
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#define DRAMC_CH1_TOP0_RX_CG_SET0 (DRAMC_CH1_TOP0_BASE + 0x244)
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#define DRAMC_CH1_TOP0_SCSMCTRL_CG (DRAMC_CH1_TOP0_BASE + 0x288)
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#define DRAMC_CH1_TOP0_SHU_APHY_TX_PICG_CTRL (DRAMC_CH1_TOP0_BASE + 0x16ac)
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#define DRAMC_CH1_TOP0_SREF_DPD_CTRL (DRAMC_CH1_TOP0_BASE + 0x168)
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#define DRAMC_CH1_TOP0_TEST2_A0 (DRAMC_CH1_TOP0_BASE + 0x100)
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#define DRAMC_CH1_TOP0_TEST2_A3 (DRAMC_CH1_TOP0_BASE + 0x108)
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#define DRAMC_CH1_TOP0_TX_CG_SET0 (DRAMC_CH1_TOP0_BASE + 0x23c)
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#define DRAMC_CH1_TOP0_TX_TRACKING_SET0 (DRAMC_CH1_TOP0_BASE + 0x1b0)
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#define DRAMC_CH1_TOP0_ZQ_SET0 (DRAMC_CH1_TOP0_BASE + 0x1a0)
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#define DRAMC_CH1_TOP5_MISC_CG_CTRL0 (DRAMC_CH1_TOP5_BASE + 0x4ec)
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#define DRAMC_CH1_TOP5_MISC_CG_CTRL2 (DRAMC_CH1_TOP5_BASE + 0x4f4)
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#define DRAMC_CH1_TOP5_MISC_CG_CTRL5 (DRAMC_CH1_TOP5_BASE + 0x500)
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#define DRAMC_CH1_TOP5_MISC_CTRL3 (DRAMC_CH1_TOP5_BASE + 0x648)
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#define DRAMC_CH1_TOP5_MISC_CTRL4 (DRAMC_CH1_TOP5_BASE + 0x64c)
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#define DRAMC_CH1_TOP5_MISC_DUTYSCAN1 (DRAMC_CH1_TOP5_BASE + 0x624)
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#define DRAMC_CH1_TOP5_MISC_RX_AUTOK_CFG0 (DRAMC_CH1_TOP5_BASE + 0x670)
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#define DRAMC_CH1_TOP5_MISC_SHU_CG_CTRL0 (DRAMC_CH1_TOP5_BASE + 0xda4)
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#define DRAMC_CH1_TOP5_MISC_SHU_RX_CG_CTRL (DRAMC_CH1_TOP5_BASE + 0xda0)
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#define DRAMC_CH1_TOP5_SHU_B0_DQ7 (DRAMC_CH1_TOP5_BASE + 0x884)
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#define DRAMC_CH1_TOP5_SHU_B0_DQ8 (DRAMC_CH1_TOP5_BASE + 0x888)
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#define DRAMC_CH1_TOP5_SHU_B1_DQ7 (DRAMC_CH1_TOP5_BASE + 0xa04)
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#define DRAMC_CH1_TOP5_SHU_B1_DQ8 (DRAMC_CH1_TOP5_BASE + 0xa08)
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#define DRAMC_CH1_TOP5_SHU_CA_CMD8 (DRAMC_CH1_TOP5_BASE + 0xb88)
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#define EMI_CONM (EMI_BASE + 0x60)
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#define EMI_CONN (EMI_BASE + 0x68)
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#define EMI_THRO_CTRL0 (EMI_BASE + 0x830)
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#define INFRA_AXIMEM_IDLE_BIT_EN_0 (INFRACFG_AO_BASE + 0xa30)
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#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70)
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#define INFRA_EMI_DCM_CFG0 (INFRACFG_AO_MEM_BASE + 0x28)
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#define INFRA_EMI_DCM_CFG1 (INFRACFG_AO_MEM_BASE + 0x2c)
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#define INFRA_EMI_DCM_CFG3 (INFRACFG_AO_MEM_BASE + 0x34)
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#define MODULE_SW_CG_2_CLR (INFRACFG_AO_BASE + 0xa8)
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#define MODULE_SW_CG_2_SET (INFRACFG_AO_BASE + 0xa4)
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#define MODULE_SW_CG_2_STA (INFRACFG_AO_BASE + 0xac)
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#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG3 (MP_CPUSYS_TOP_BASE + 0x22ac)
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#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG4 (MP_CPUSYS_TOP_BASE + 0x22b0)
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#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
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#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
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#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
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#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
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#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
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#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
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#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
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#define P2P_RX_CLK_ON (INFRACFG_AO_BASE + 0xa0)
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#define PERI_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x74)
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#define SSPM_DCM_CTRL (SSPM_BASE + 0x43008)
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#define SSPM_MCLK_DIV (SSPM_BASE + 0x43004)
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#define TOP_CK_ANCHOR_CFG (INFRACFG_AO_MEM_BASE + 0x38)
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#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0 \
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(INFRA_AO_BCRM_BASE + 0x34)
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#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1 \
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(INFRA_AO_BCRM_BASE + 0x38)
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#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_10 \
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(INFRA_AO_BCRM_BASE + 0x5c)
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#define VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2 \
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(INFRA_AO_BCRM_BASE + 0x3c)
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bool dcm_infracfg_ao_aximem_bus_dcm_is_on(void);
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void dcm_infracfg_ao_aximem_bus_dcm(int on);
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bool dcm_infracfg_ao_infra_bus_dcm_is_on(void);
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void dcm_infracfg_ao_infra_bus_dcm(int on);
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bool dcm_infracfg_ao_infra_conn_bus_dcm_is_on(void);
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void dcm_infracfg_ao_infra_conn_bus_dcm(int on);
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bool dcm_infracfg_ao_infra_rx_p2p_dcm_is_on(void);
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void dcm_infracfg_ao_infra_rx_p2p_dcm(int on);
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bool dcm_infracfg_ao_mts_bus_dcm_is_on(void);
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void dcm_infracfg_ao_mts_bus_dcm(int on);
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bool dcm_infracfg_ao_peri_bus_dcm_is_on(void);
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void dcm_infracfg_ao_peri_bus_dcm(int on);
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bool dcm_infracfg_ao_peri_module_dcm_is_on(void);
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void dcm_infracfg_ao_peri_module_dcm(int on);
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bool dcm_infracfg_ao_mem_dcm_emi_group_is_on(void);
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void dcm_infracfg_ao_mem_dcm_emi_group(int on);
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bool dcm_infra_ao_bcrm_infra_bus_dcm_is_on(void);
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void dcm_infra_ao_bcrm_infra_bus_dcm(int on);
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bool dcm_infra_ao_bcrm_peri_bus_dcm_is_on(void);
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void dcm_infra_ao_bcrm_peri_bus_dcm(int on);
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bool dcm_emi_emi_dcm_is_on(void);
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void dcm_emi_emi_dcm(int on);
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bool dcm_dramc_ch0_top0_ddrphy_is_on(void);
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void dcm_dramc_ch0_top0_ddrphy(int on);
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bool dcm_chn0_emi_chn_emi_dcm_is_on(void);
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void dcm_chn0_emi_chn_emi_dcm(int on);
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bool dcm_dramc_ch0_top5_ddrphy_is_on(void);
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void dcm_dramc_ch0_top5_ddrphy(int on);
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bool dcm_dramc_ch1_top0_ddrphy_is_on(void);
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void dcm_dramc_ch1_top0_ddrphy(int on);
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bool dcm_dramc_ch1_top5_ddrphy_is_on(void);
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void dcm_dramc_ch1_top5_ddrphy(int on);
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bool dcm_sspm_sspm_dcm_is_on(void);
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void dcm_sspm_sspm_dcm(int on);
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bool dcm_audio_aud_mas_ahb_ck_dcm_is_on(void);
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void dcm_audio_aud_mas_ahb_ck_dcm(int on);
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bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
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void dcm_mp_cpusys_top_adb_dcm(int on);
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bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
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void dcm_mp_cpusys_top_apb_dcm(int on);
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bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
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void dcm_mp_cpusys_top_bus_pll_div_dcm(int on);
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bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_core_stall_dcm(int on);
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bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpubiu_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(int on);
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bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_fcm_stall_dcm(int on);
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bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
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void dcm_mp_cpusys_top_last_cor_idle_dcm(int on);
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bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
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void dcm_mp_cpusys_top_misc_dcm(int on);
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bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
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void dcm_mp_cpusys_top_mp0_qdcm(int on);
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bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
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void dcm_cpccfg_reg_emi_wfifo(int on);
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#endif /* __MTK_DCM_AUTOGEN_H__ */
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