mirror of
https://github.com/physwizz/a155-U-u1.git
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451 lines
21 KiB
C
451 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: ren-ting.wang <ren-ting.wang@mediatek.com>
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*/
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#ifndef CLKBUF_DCXO_6685_H
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#define CLKBUF_DCXO_6685_H
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#include "mtk-clkbuf-dcxo.h"
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#define MT6685_PMRC_CON0 (0x190)
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#define MT6685_PMRC_CON1 (0x191)
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#define MT6685_PMRC_CON0_SET (0x198)
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#define MT6685_PMRC_CON1_SET (0x199)
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#define MT6685_PMRC_CON0_CLR (0x19a)
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#define MT6685_PMRC_CON1_CLR (0x19b)
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#define MT6685_PMRC_CON3 (0x19c)
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#define MT6685_XO_BUF_CTL0_L (0x54c)
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#define MT6685_XO_BUF_CTL0_H (0x54d)
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#define MT6685_XO_BUF_CTL1_L (0x54e)
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#define MT6685_XO_BUF_CTL1_H (0x54f)
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#define MT6685_XO_BUF_CTL2_L (0x550)
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#define MT6685_XO_BUF_CTL2_H (0x551)
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#define MT6685_XO_BUF_CTL3_L (0x552)
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#define MT6685_XO_BUF_CTL3_H (0x553)
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#define MT6685_XO_BUF_CTL4_L (0x554)
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#define MT6685_XO_BUF_CTL4_H (0x555)
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#define MT6685_XO_BUF_CTL5_L (0x556)
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#define MT6685_XO_BUF_CTL5_H (0x557)
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#define MT6685_XO_BUF_CTL6_L (0x558)
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#define MT6685_XO_BUF_CTL6_H (0x559)
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#define MT6685_XO_BUF_CTL7_L (0x55a)
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#define MT6685_XO_BUF_CTL7_H (0x55b)
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#define MT6685_XO_BUF_CTL8_L (0x55c)
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#define MT6685_XO_BUF_CTL8_H (0x55d)
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#define MT6685_XO_BUF_CTL9_L (0x55e)
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#define MT6685_XO_BUF_CTL9_H (0x55f)
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#define MT6685_XO_BUF_CTL10_L (0x560)
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#define MT6685_XO_BUF_CTL10_H (0x561)
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#define MT6685_XO_BUF_CTL11_L (0x562)
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#define MT6685_XO_BUF_CTL11_H (0x563)
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#define MT6685_XO_BUF_CTL12_L (0x564)
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#define MT6685_XO_BUF_CTL12_H (0x565)
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#define MT6685_XO_CONN_BT0 (0x567)
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#define MT6685_DCXO_DIG_MANCTRL_CW1 (0x796)
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#define MT6685_DCXO_BBLPM_CW0 (0x797)
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#define MT6685_DCXO_BBLPM_CW1 (0x798)
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#define MT6685_DCXO_LDO_CW0 (0x799)
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#define MT6685_DCXO_EXTBUF1_CW0 (0x79a)
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#define MT6685_DCXO_EXTBUF2_CW0 (0x79b)
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#define MT6685_DCXO_EXTBUF3_CW0 (0x79c)
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#define MT6685_DCXO_EXTBUF4_CW0 (0x79d)
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#define MT6685_DCXO_EXTBUF5_CW0 (0x79e)
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#define MT6685_DCXO_EXTBUF6_CW0 (0x79f)
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#define MT6685_DCXO_EXTBUF7_CW0 (0x7a0)
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#define MT6685_DCXO_EXTBUF8_CW0 (0x7a1)
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#define MT6685_DCXO_EXTBUF9_CW0 (0x7a2)
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#define MT6685_DCXO_EXTBUF10_CW0 (0x7a3)
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#define MT6685_DCXO_EXTBUF11_CW0 (0x7a4)
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#define MT6685_DCXO_EXTBUF12_CW0 (0x7a5)
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#define MT6685_DCXO_EXTBUF13_CW0 (0x7a6)
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#define MT6685_DCXO_EXTBUF_CW0 (0x7a7)
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#define MT6685_DCXO_RGMON_CW0_L (0x7b2)
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#define MT6685_DCXO_RGMON_CW0_H (0x7b3)
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#define MT6685_DCXO_RGMON_CW2_L (0x7b4)
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#define MT6685_DCXO_RGMON_CW2_H (0x7b5)
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#define MT6685_DCXO_CDAC_CW1 (0x7c0)
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#define MT6685_DCXO_AAC_CW1 (0x7c2)
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#define MT6685_DCXO_RGMON_CW1 (0x7c3)
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#define MT6685_DCXO_DIGCLK_ELR (0x7f4)
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#define MT6685_PCHR_VREF_ANA_CON3 (0xa8b)
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#define MT6685_LDO_VBBCK_CON0 (0x1b87)
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#define MT6685_LDO_VBBCK_OP_EN1 (0x1b8e)
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#define MT6685_LDO_VBBCK_OP_EN1_SET (0x1b8f)
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#define MT6685_LDO_VBBCK_OP_EN1_CLR (0x1b90)
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#define MT6685_LDO_VRFCK1_CON0 (0x1b97)
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#define MT6685_LDO_VRFCK1_OP_EN1 (0x1b9e)
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#define MT6685_LDO_VRFCK1_OP_EN1_SET (0x1b9f)
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#define MT6685_LDO_VRFCK1_OP_EN1_CLR (0x1ba0)
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#define MT6685_LDO_VRFCK2_CON0 (0x1ba7)
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#define MT6685_LDO_VRFCK2_OP_EN1 (0x1bae)
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#define MT6685_LDO_VRFCK2_OP_EN1_SET (0x1baf)
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#define MT6685_LDO_VRFCK2_OP_EN1_CLR (0x1bb0)
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/* Register_TOP_REG*/
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#define MT6685_PMRC_EN0_ADDR (MT6685_PMRC_CON0)
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#define MT6685_PMRC_EN0_MASK (0xff)
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#define MT6685_PMRC_EN0_SHIFT (0)
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#define MT6685_PMRC_EN1_ADDR (MT6685_PMRC_CON1)
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#define MT6685_PMRC_EN1_MASK (0xff)
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#define MT6685_PMRC_EN1_SHIFT (0)
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#define MT6685_PMRC_CON0_SET_ADDR (MT6685_PMRC_CON0_SET)
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#define MT6685_PMRC_CON0_SET_MASK (0xff)
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#define MT6685_PMRC_CON0_SET_SHIFT (0)
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#define MT6685_PMRC_CON1_SET_ADDR (MT6685_PMRC_CON1_SET)
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#define MT6685_PMRC_CON1_SET_MASK (0xff)
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#define MT6685_PMRC_CON1_SET_SHIFT (0)
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#define MT6685_PMRC_CON0_CLR_ADDR (MT6685_PMRC_CON0_CLR)
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#define MT6685_PMRC_CON0_CLR_MASK (0xff)
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#define MT6685_PMRC_CON0_CLR_SHIFT (0)
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#define MT6685_PMRC_CON1_CLR_ADDR (MT6685_PMRC_CON1_CLR)
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#define MT6685_PMRC_CON1_CLR_MASK (0xff)
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#define MT6685_PMRC_CON1_CLR_SHIFT (0)
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#define MT6685_RG_DCXO_SRCLKEN1_MODE_ADDR (MT6685_PMRC_CON3)
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#define MT6685_RG_DCXO_SRCLKEN1_MODE_MASK (0x3)
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#define MT6685_RG_DCXO_SRCLKEN1_MODE_SHIFT (2)
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/* Register_SCK_REG*/
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#define MT6685_XO_BBCK1_VOTE_L_ADDR (MT6685_XO_BUF_CTL0_L)
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#define MT6685_XO_BBCK1_VOTE_L_MASK (0xff)
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#define MT6685_XO_BBCK1_VOTE_L_SHIFT (0)
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#define MT6685_XO_BBCK1_VOTE_H_ADDR (MT6685_XO_BUF_CTL0_H)
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#define MT6685_XO_BBCK1_VOTE_H_MASK (0x3f)
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#define MT6685_XO_BBCK1_VOTE_H_SHIFT (0)
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#define MT6685_XO_BBCK2_VOTE_L_ADDR (MT6685_XO_BUF_CTL1_L)
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#define MT6685_XO_BBCK2_VOTE_L_MASK (0xff)
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#define MT6685_XO_BBCK2_VOTE_L_SHIFT (0)
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#define MT6685_XO_BBCK2_VOTE_H_ADDR (MT6685_XO_BUF_CTL1_H)
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#define MT6685_XO_BBCK2_VOTE_H_MASK (0x3f)
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#define MT6685_XO_BBCK2_VOTE_H_SHIFT (0)
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#define MT6685_XO_BBCK3_VOTE_L_ADDR (MT6685_XO_BUF_CTL2_L)
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#define MT6685_XO_BBCK3_VOTE_L_MASK (0xff)
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#define MT6685_XO_BBCK3_VOTE_L_SHIFT (0)
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#define MT6685_XO_BBCK3_VOTE_H_ADDR (MT6685_XO_BUF_CTL2_H)
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#define MT6685_XO_BBCK3_VOTE_H_MASK (0x3f)
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#define MT6685_XO_BBCK3_VOTE_H_SHIFT (0)
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#define MT6685_XO_BBCK4_VOTE_L_ADDR (MT6685_XO_BUF_CTL3_L)
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#define MT6685_XO_BBCK4_VOTE_L_MASK (0xff)
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#define MT6685_XO_BBCK4_VOTE_L_SHIFT (0)
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#define MT6685_XO_BBCK4_VOTE_H_ADDR (MT6685_XO_BUF_CTL3_H)
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#define MT6685_XO_BBCK4_VOTE_H_MASK (0x3f)
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#define MT6685_XO_BBCK4_VOTE_H_SHIFT (0)
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#define MT6685_XO_BBCK5_VOTE_L_ADDR (MT6685_XO_BUF_CTL4_L)
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#define MT6685_XO_BBCK5_VOTE_L_MASK (0xff)
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#define MT6685_XO_BBCK5_VOTE_L_SHIFT (0)
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#define MT6685_XO_BBCK5_VOTE_H_ADDR (MT6685_XO_BUF_CTL4_H)
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#define MT6685_XO_BBCK5_VOTE_H_MASK (0x3f)
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#define MT6685_XO_BBCK5_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK1A_VOTE_L_ADDR (MT6685_XO_BUF_CTL5_L)
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#define MT6685_XO_RFCK1A_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK1A_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK1A_VOTE_H_ADDR (MT6685_XO_BUF_CTL5_H)
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#define MT6685_XO_RFCK1A_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK1A_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK1B_VOTE_L_ADDR (MT6685_XO_BUF_CTL6_L)
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#define MT6685_XO_RFCK1B_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK1B_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK1B_VOTE_H_ADDR (MT6685_XO_BUF_CTL6_H)
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#define MT6685_XO_RFCK1B_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK1B_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK1C_VOTE_L_ADDR (MT6685_XO_BUF_CTL7_L)
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#define MT6685_XO_RFCK1C_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK1C_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK1C_VOTE_H_ADDR (MT6685_XO_BUF_CTL7_H)
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#define MT6685_XO_RFCK1C_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK1C_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK2A_VOTE_L_ADDR (MT6685_XO_BUF_CTL8_L)
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#define MT6685_XO_RFCK2A_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK2A_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK2A_VOTE_H_ADDR (MT6685_XO_BUF_CTL8_H)
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#define MT6685_XO_RFCK2A_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK2A_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK2B_VOTE_L_ADDR (MT6685_XO_BUF_CTL9_L)
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#define MT6685_XO_RFCK2B_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK2B_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK2B_VOTE_H_ADDR (MT6685_XO_BUF_CTL9_H)
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#define MT6685_XO_RFCK2B_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK2B_VOTE_H_SHIFT (0)
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#define MT6685_XO_RFCK2C_VOTE_L_ADDR (MT6685_XO_BUF_CTL10_L)
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#define MT6685_XO_RFCK2C_VOTE_L_MASK (0xff)
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#define MT6685_XO_RFCK2C_VOTE_L_SHIFT (0)
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#define MT6685_XO_RFCK2C_VOTE_H_ADDR (MT6685_XO_BUF_CTL10_H)
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#define MT6685_XO_RFCK2C_VOTE_H_MASK (0x3f)
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#define MT6685_XO_RFCK2C_VOTE_H_SHIFT (0)
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#define MT6685_XO_CONCK1_VOTE_L_ADDR (MT6685_XO_BUF_CTL11_L)
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#define MT6685_XO_CONCK1_VOTE_L_MASK (0xff)
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#define MT6685_XO_CONCK1_VOTE_L_SHIFT (0)
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#define MT6685_XO_CONCK1_VOTE_H_ADDR (MT6685_XO_BUF_CTL11_H)
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#define MT6685_XO_CONCK1_VOTE_H_MASK (0x3f)
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#define MT6685_XO_CONCK1_VOTE_H_SHIFT (0)
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#define MT6685_XO_CONCK2_VOTE_L_ADDR (MT6685_XO_BUF_CTL12_L)
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#define MT6685_XO_CONCK2_VOTE_L_MASK (0xff)
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#define MT6685_XO_CONCK2_VOTE_L_SHIFT (0)
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#define MT6685_XO_CONCK2_VOTE_H_ADDR (MT6685_XO_BUF_CTL12_H)
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#define MT6685_XO_CONCK2_VOTE_H_MASK (0x3f)
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#define MT6685_XO_CONCK2_VOTE_H_SHIFT (0)
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#define MT6685_XO_MODE_CONN_BT_MASK_ADDR (MT6685_XO_CONN_BT0)
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#define MT6685_XO_MODE_CONN_BT_MASK_MASK (0x1)
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#define MT6685_XO_MODE_CONN_BT_MASK_SHIFT (0)
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#define MT6685_XO_BUF_CONN_BT_MASK_ADDR (MT6685_XO_CONN_BT0)
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#define MT6685_XO_BUF_CONN_BT_MASK_MASK (0x1)
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#define MT6685_XO_BUF_CONN_BT_MASK_SHIFT (1)
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/* Register_DCXO_REG*/
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#define MT6685_XO_PMIC_TOP_DIG_SW_ADDR (MT6685_DCXO_DIG_MANCTRL_CW1)
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#define MT6685_XO_PMIC_TOP_DIG_SW_MASK (0x1)
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#define MT6685_XO_PMIC_TOP_DIG_SW_SHIFT (0)
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#define MT6685_XO_ENBB_MAN_ADDR (MT6685_DCXO_DIG_MANCTRL_CW1)
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#define MT6685_XO_ENBB_MAN_MASK (0x1)
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#define MT6685_XO_ENBB_MAN_SHIFT (1)
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#define MT6685_XO_ENBB_EN_M_ADDR (MT6685_DCXO_DIG_MANCTRL_CW1)
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#define MT6685_XO_ENBB_EN_M_MASK (0x1)
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#define MT6685_XO_ENBB_EN_M_SHIFT (2)
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#define MT6685_XO_CLKSEL_MAN_ADDR (MT6685_DCXO_DIG_MANCTRL_CW1)
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#define MT6685_XO_CLKSEL_MAN_MASK (0x1)
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#define MT6685_XO_CLKSEL_MAN_SHIFT (3)
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#define MT6685_XO_CLKSEL_EN_M_ADDR (MT6685_DCXO_DIG_MANCTRL_CW1)
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#define MT6685_XO_CLKSEL_EN_M_MASK (0x1)
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#define MT6685_XO_CLKSEL_EN_M_SHIFT (4)
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#define MT6685_XO_BB_LPM_EN_M_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BB_LPM_EN_M_MASK (0x1)
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#define MT6685_XO_BB_LPM_EN_M_SHIFT (0)
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#define MT6685_XO_BB_LPM_EN_SEL_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BB_LPM_EN_SEL_MASK (0x1)
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#define MT6685_XO_BB_LPM_EN_SEL_SHIFT (1)
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#define MT6685_XO_BBCK1_BBLPM_EN_MASK_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BBCK1_BBLPM_EN_MASK_MASK (0x1)
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#define MT6685_XO_BBCK1_BBLPM_EN_MASK_SHIFT (2)
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#define MT6685_XO_BBCK2_BBLPM_EN_MASK_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BBCK2_BBLPM_EN_MASK_MASK (0x1)
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#define MT6685_XO_BBCK2_BBLPM_EN_MASK_SHIFT (3)
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#define MT6685_XO_BBCK3_BBLPM_EN_MASK_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BBCK3_BBLPM_EN_MASK_MASK (0x1)
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#define MT6685_XO_BBCK3_BBLPM_EN_MASK_SHIFT (4)
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#define MT6685_XO_BBCK4_BBLPM_EN_MASK_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BBCK4_BBLPM_EN_MASK_MASK (0x1)
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#define MT6685_XO_BBCK4_BBLPM_EN_MASK_SHIFT (5)
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#define MT6685_XO_BBCK5_BBLPM_EN_MASK_ADDR (MT6685_DCXO_BBLPM_CW0)
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#define MT6685_XO_BBCK5_BBLPM_EN_MASK_MASK (0x1)
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#define MT6685_XO_BBCK5_BBLPM_EN_MASK_SHIFT (6)
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#define MT6685_XO_BBLPM_EN_MAN_ADDR (MT6685_DCXO_BBLPM_CW1)
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#define MT6685_XO_BBLPM_EN_MAN_MASK (0x1)
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#define MT6685_XO_BBLPM_EN_MAN_SHIFT (0)
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#define MT6685_XO_BBLPM_EN_MAN_M_ADDR (MT6685_DCXO_BBLPM_CW1)
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#define MT6685_XO_BBLPM_EN_MAN_M_MASK (0x1)
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#define MT6685_XO_BBLPM_EN_MAN_M_SHIFT (1)
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#define MT6685_XO_VBBCK_EN_MAN_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VBBCK_EN_MAN_MASK (0x1)
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#define MT6685_XO_VBBCK_EN_MAN_SHIFT (0)
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#define MT6685_XO_VBBCK_EN_M_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VBBCK_EN_M_MASK (0x1)
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#define MT6685_XO_VBBCK_EN_M_SHIFT (1)
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#define MT6685_XO_VRFCK1_EN_MAN_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VRFCK1_EN_MAN_MASK (0x1)
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#define MT6685_XO_VRFCK1_EN_MAN_SHIFT (2)
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#define MT6685_XO_VRFCK1_EN_M_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VRFCK1_EN_M_MASK (0x1)
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#define MT6685_XO_VRFCK1_EN_M_SHIFT (3)
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#define MT6685_XO_VRFCK2_EN_MAN_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VRFCK2_EN_MAN_MASK (0x1)
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#define MT6685_XO_VRFCK2_EN_MAN_SHIFT (4)
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#define MT6685_XO_VRFCK2_EN_M_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VRFCK2_EN_M_MASK (0x1)
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#define MT6685_XO_VRFCK2_EN_M_SHIFT (5)
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#define MT6685_XO_VCONCK_EN_MAN_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VCONCK_EN_MAN_MASK (0x1)
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#define MT6685_XO_VCONCK_EN_MAN_SHIFT (6)
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#define MT6685_XO_VCONCK_EN_M_ADDR (MT6685_DCXO_LDO_CW0)
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#define MT6685_XO_VCONCK_EN_M_MASK (0x1)
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#define MT6685_XO_VCONCK_EN_M_SHIFT (7)
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#define MT6685_XO_BBCK1_MODE_ADDR (MT6685_DCXO_EXTBUF1_CW0)
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#define MT6685_XO_BBCK1_MODE_MASK (0x3)
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#define MT6685_XO_BBCK1_MODE_SHIFT (0)
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#define MT6685_XO_BBCK1_EN_M_ADDR (MT6685_DCXO_EXTBUF1_CW0)
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#define MT6685_XO_BBCK1_EN_M_MASK (0x1)
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#define MT6685_XO_BBCK1_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_BBCK1_RSEL_ADDR (MT6685_DCXO_EXTBUF1_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK1_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_BBCK1_RSEL_SHIFT (3)
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#define MT6685_RG_XO_EXTBUF_BBCK1_HD_ADDR (MT6685_DCXO_EXTBUF1_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK1_HD_MASK (0x3)
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#define MT6685_RG_XO_EXTBUF_BBCK1_HD_SHIFT (6)
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#define MT6685_XO_BBCK2_MODE_ADDR (MT6685_DCXO_EXTBUF2_CW0)
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#define MT6685_XO_BBCK2_MODE_MASK (0x3)
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#define MT6685_XO_BBCK2_MODE_SHIFT (0)
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#define MT6685_XO_BBCK2_EN_M_ADDR (MT6685_DCXO_EXTBUF2_CW0)
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#define MT6685_XO_BBCK2_EN_M_MASK (0x1)
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#define MT6685_XO_BBCK2_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_BBCK2_RSEL_ADDR (MT6685_DCXO_EXTBUF2_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK2_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_BBCK2_RSEL_SHIFT (3)
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#define MT6685_RG_XO_EXTBUF_BBCK2_HD_ADDR (MT6685_DCXO_EXTBUF2_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK2_HD_MASK (0x3)
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#define MT6685_RG_XO_EXTBUF_BBCK2_HD_SHIFT (6)
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#define MT6685_XO_BBCK3_MODE_ADDR (MT6685_DCXO_EXTBUF3_CW0)
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#define MT6685_XO_BBCK3_MODE_MASK (0x3)
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#define MT6685_XO_BBCK3_MODE_SHIFT (0)
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#define MT6685_XO_BBCK3_EN_M_ADDR (MT6685_DCXO_EXTBUF3_CW0)
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#define MT6685_XO_BBCK3_EN_M_MASK (0x1)
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#define MT6685_XO_BBCK3_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_BBCK3_RSEL_ADDR (MT6685_DCXO_EXTBUF3_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK3_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_BBCK3_RSEL_SHIFT (3)
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#define MT6685_RG_XO_EXTBUF_BBCK3_HD_ADDR (MT6685_DCXO_EXTBUF3_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK3_HD_MASK (0x3)
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#define MT6685_RG_XO_EXTBUF_BBCK3_HD_SHIFT (6)
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#define MT6685_XO_BBCK4_MODE_ADDR (MT6685_DCXO_EXTBUF4_CW0)
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#define MT6685_XO_BBCK4_MODE_MASK (0x3)
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#define MT6685_XO_BBCK4_MODE_SHIFT (0)
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#define MT6685_XO_BBCK4_EN_M_ADDR (MT6685_DCXO_EXTBUF4_CW0)
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#define MT6685_XO_BBCK4_EN_M_MASK (0x1)
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#define MT6685_XO_BBCK4_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_BBCK4_RSEL_ADDR (MT6685_DCXO_EXTBUF4_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK4_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_BBCK4_RSEL_SHIFT (3)
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#define MT6685_RG_XO_EXTBUF_BBCK4_HD_ADDR (MT6685_DCXO_EXTBUF4_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK4_HD_MASK (0x3)
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#define MT6685_RG_XO_EXTBUF_BBCK4_HD_SHIFT (6)
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#define MT6685_XO_BBCK5_MODE_ADDR (MT6685_DCXO_EXTBUF5_CW0)
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#define MT6685_XO_BBCK5_MODE_MASK (0x3)
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#define MT6685_XO_BBCK5_MODE_SHIFT (0)
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#define MT6685_XO_BBCK5_EN_M_ADDR (MT6685_DCXO_EXTBUF5_CW0)
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#define MT6685_XO_BBCK5_EN_M_MASK (0x1)
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#define MT6685_XO_BBCK5_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_BBCK5_RSEL_ADDR (MT6685_DCXO_EXTBUF5_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK5_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_BBCK5_RSEL_SHIFT (3)
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#define MT6685_RG_XO_EXTBUF_BBCK5_HD_ADDR (MT6685_DCXO_EXTBUF5_CW0)
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#define MT6685_RG_XO_EXTBUF_BBCK5_HD_MASK (0x3)
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#define MT6685_RG_XO_EXTBUF_BBCK5_HD_SHIFT (6)
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#define MT6685_XO_RFCK1A_MODE_ADDR (MT6685_DCXO_EXTBUF6_CW0)
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#define MT6685_XO_RFCK1A_MODE_MASK (0x3)
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#define MT6685_XO_RFCK1A_MODE_SHIFT (0)
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#define MT6685_XO_RFCK1A_EN_M_ADDR (MT6685_DCXO_EXTBUF6_CW0)
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#define MT6685_XO_RFCK1A_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK1A_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK1A_RSEL_ADDR (MT6685_DCXO_EXTBUF6_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK1A_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK1A_RSEL_SHIFT (3)
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#define MT6685_XO_RFCK1B_MODE_ADDR (MT6685_DCXO_EXTBUF7_CW0)
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#define MT6685_XO_RFCK1B_MODE_MASK (0x3)
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#define MT6685_XO_RFCK1B_MODE_SHIFT (0)
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#define MT6685_XO_RFCK1B_EN_M_ADDR (MT6685_DCXO_EXTBUF7_CW0)
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#define MT6685_XO_RFCK1B_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK1B_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK1B_RSEL_ADDR (MT6685_DCXO_EXTBUF7_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK1B_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK1B_RSEL_SHIFT (3)
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#define MT6685_XO_RFCK1C_MODE_ADDR (MT6685_DCXO_EXTBUF8_CW0)
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#define MT6685_XO_RFCK1C_MODE_MASK (0x3)
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#define MT6685_XO_RFCK1C_MODE_SHIFT (0)
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#define MT6685_XO_RFCK1C_EN_M_ADDR (MT6685_DCXO_EXTBUF8_CW0)
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#define MT6685_XO_RFCK1C_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK1C_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK1C_RSEL_ADDR (MT6685_DCXO_EXTBUF8_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK1C_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK1C_RSEL_SHIFT (3)
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#define MT6685_XO_RFCK2A_MODE_ADDR (MT6685_DCXO_EXTBUF9_CW0)
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#define MT6685_XO_RFCK2A_MODE_MASK (0x3)
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#define MT6685_XO_RFCK2A_MODE_SHIFT (0)
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#define MT6685_XO_RFCK2A_EN_M_ADDR (MT6685_DCXO_EXTBUF9_CW0)
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#define MT6685_XO_RFCK2A_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK2A_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK2A_RSEL_ADDR (MT6685_DCXO_EXTBUF9_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK2A_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK2A_RSEL_SHIFT (3)
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#define MT6685_XO_RFCK2B_MODE_ADDR (MT6685_DCXO_EXTBUF10_CW0)
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#define MT6685_XO_RFCK2B_MODE_MASK (0x3)
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#define MT6685_XO_RFCK2B_MODE_SHIFT (0)
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#define MT6685_XO_RFCK2B_EN_M_ADDR (MT6685_DCXO_EXTBUF10_CW0)
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#define MT6685_XO_RFCK2B_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK2B_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK2B_RSEL_ADDR (MT6685_DCXO_EXTBUF10_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK2B_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK2B_RSEL_SHIFT (3)
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#define MT6685_XO_RFCK2C_MODE_ADDR (MT6685_DCXO_EXTBUF11_CW0)
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#define MT6685_XO_RFCK2C_MODE_MASK (0x3)
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#define MT6685_XO_RFCK2C_MODE_SHIFT (0)
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#define MT6685_XO_RFCK2C_EN_M_ADDR (MT6685_DCXO_EXTBUF11_CW0)
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#define MT6685_XO_RFCK2C_EN_M_MASK (0x1)
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#define MT6685_XO_RFCK2C_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_RFCK2C_RSEL_ADDR (MT6685_DCXO_EXTBUF11_CW0)
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#define MT6685_RG_XO_EXTBUF_RFCK2C_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_RFCK2C_RSEL_SHIFT (3)
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#define MT6685_XO_CONCK1_MODE_ADDR (MT6685_DCXO_EXTBUF12_CW0)
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#define MT6685_XO_CONCK1_MODE_MASK (0x3)
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#define MT6685_XO_CONCK1_MODE_SHIFT (0)
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#define MT6685_XO_CONCK1_EN_M_ADDR (MT6685_DCXO_EXTBUF12_CW0)
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#define MT6685_XO_CONCK1_EN_M_MASK (0x1)
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#define MT6685_XO_CONCK1_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_CONCK1_RSEL_ADDR (MT6685_DCXO_EXTBUF12_CW0)
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#define MT6685_RG_XO_EXTBUF_CONCK1_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_CONCK1_RSEL_SHIFT (3)
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#define MT6685_XO_CONCK2_MODE_ADDR (MT6685_DCXO_EXTBUF13_CW0)
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#define MT6685_XO_CONCK2_MODE_MASK (0x3)
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#define MT6685_XO_CONCK2_MODE_SHIFT (0)
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#define MT6685_XO_CONCK2_EN_M_ADDR (MT6685_DCXO_EXTBUF13_CW0)
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#define MT6685_XO_CONCK2_EN_M_MASK (0x1)
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#define MT6685_XO_CONCK2_EN_M_SHIFT (2)
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#define MT6685_RG_XO_EXTBUF_CONCK2_RSEL_ADDR (MT6685_DCXO_EXTBUF13_CW0)
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#define MT6685_RG_XO_EXTBUF_CONCK2_RSEL_MASK (0x7)
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#define MT6685_RG_XO_EXTBUF_CONCK2_RSEL_SHIFT (3)
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#define MT6685_XO_BBCK_ALL_EN_ADDR (MT6685_DCXO_EXTBUF_CW0)
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#define MT6685_XO_BBCK_ALL_EN_MASK (0x1)
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#define MT6685_XO_BBCK_ALL_EN_SHIFT (0)
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#define MT6685_XO_RFCK1_ALL_EN_ADDR (MT6685_DCXO_EXTBUF_CW0)
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#define MT6685_XO_RFCK1_ALL_EN_MASK (0x1)
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#define MT6685_XO_RFCK1_ALL_EN_SHIFT (1)
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#define MT6685_XO_RFCK2_ALL_EN_ADDR (MT6685_DCXO_EXTBUF_CW0)
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#define MT6685_XO_RFCK2_ALL_EN_MASK (0x1)
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#define MT6685_XO_RFCK2_ALL_EN_SHIFT (2)
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#define MT6685_XO_CONCK_ALL_EN_ADDR (MT6685_DCXO_EXTBUF_CW0)
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#define MT6685_XO_CONCK_ALL_EN_MASK (0x1)
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#define MT6685_XO_CONCK_ALL_EN_SHIFT (3)
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#define MT6685_XO_AUXOUT_SEL_L_ADDR (MT6685_DCXO_RGMON_CW0_L)
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#define MT6685_XO_AUXOUT_SEL_L_MASK (0xff)
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#define MT6685_XO_AUXOUT_SEL_L_SHIFT (0)
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#define MT6685_XO_AUXOUT_SEL_H_ADDR (MT6685_DCXO_RGMON_CW0_H)
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#define MT6685_XO_AUXOUT_SEL_H_MASK (0x3)
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#define MT6685_XO_AUXOUT_SEL_H_SHIFT (0)
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#define MT6685_XO_STATIC_AUXOUT_L_ADDR (MT6685_DCXO_RGMON_CW2_L)
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#define MT6685_XO_STATIC_AUXOUT_L_MASK (0xff)
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#define MT6685_XO_STATIC_AUXOUT_L_SHIFT (0)
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#define MT6685_XO_STATIC_AUXOUT_H_ADDR (MT6685_DCXO_RGMON_CW2_H)
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#define MT6685_XO_STATIC_AUXOUT_H_MASK (0xff)
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#define MT6685_XO_STATIC_AUXOUT_H_SHIFT (0)
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#define MT6685_XO_STATIC_AUXOUT_SEL_ADDR (MT6685_DCXO_RGMON_CW1)
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#define MT6685_XO_STATIC_AUXOUT_SEL_MASK (0x7f)
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#define MT6685_XO_STATIC_AUXOUT_SEL_SHIFT (0)
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#define MT6685_RG_XO_DIG26M_DIV2_ADDR (MT6685_DCXO_DIGCLK_ELR)
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#define MT6685_RG_XO_DIG26M_DIV2_MASK (0x1)
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#define MT6685_RG_XO_DIG26M_DIV2_SHIFT (0)
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#define MT6685_RG_XO_CDAC_FPM_ADDR (MT6685_DCXO_CDAC_CW1)
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#define MT6685_RG_XO_CDAC_FPM_MASK (0xff)
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#define MT6685_RG_XO_CDAC_FPM_SHIFT (0)
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#define MT6685_RG_XO_AAC_FPM_SWEN_ADDR (MT6685_DCXO_AAC_CW1)
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#define MT6685_RG_XO_AAC_FPM_SWEN_MASK (0x1)
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#define MT6685_RG_XO_AAC_FPM_SWEN_SHIFT (6)
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#define MT6685_RG_XO_HEATER_SEL_ADDR (MT6685_PCHR_VREF_ANA_CON3)
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#define MT6685_RG_XO_HEATER_SEL_MASK (0x3)
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#define MT6685_RG_XO_HEATER_SEL_SHIFT (0)
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/* Register_LDO_REG*/
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#define MT6685_RG_LDO_VBBCK_EN_ADDR (MT6685_LDO_VBBCK_CON0)
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#define MT6685_RG_LDO_VBBCK_EN_MASK (0x1)
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#define MT6685_RG_LDO_VBBCK_EN_SHIFT (0)
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#define MT6685_RG_LDO_VBBCK_HW14_OP_EN_ADDR (MT6685_LDO_VBBCK_OP_EN1)
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#define MT6685_RG_LDO_VBBCK_HW14_OP_EN_MASK (0x1)
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#define MT6685_RG_LDO_VBBCK_HW14_OP_EN_SHIFT (6)
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#define MT6685_RG_LDO_VRFCK1_EN_ADDR (MT6685_LDO_VRFCK1_CON0)
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#define MT6685_RG_LDO_VRFCK1_EN_MASK (0x1)
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#define MT6685_RG_LDO_VRFCK1_EN_SHIFT (0)
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#define MT6685_RG_LDO_VRFCK1_HW14_OP_EN_ADDR (MT6685_LDO_VRFCK1_OP_EN1)
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#define MT6685_RG_LDO_VRFCK1_HW14_OP_EN_MASK (0x1)
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#define MT6685_RG_LDO_VRFCK1_HW14_OP_EN_SHIFT (6)
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#define MT6685_RG_LDO_VRFCK2_EN_ADDR (MT6685_LDO_VRFCK2_CON0)
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#define MT6685_RG_LDO_VRFCK2_EN_MASK (0x1)
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#define MT6685_RG_LDO_VRFCK2_EN_SHIFT (0)
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#define MT6685_RG_LDO_VRFCK2_HW14_OP_EN_ADDR (MT6685_LDO_VRFCK2_OP_EN1)
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#define MT6685_RG_LDO_VRFCK2_HW14_OP_EN_MASK (0x1)
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#define MT6685_RG_LDO_VRFCK2_HW14_OP_EN_SHIFT (6)
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#endif /* CLKBUF_DCXO_6685P_H */
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