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160 lines
6.3 KiB
C
160 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: ky.liu <ky.liu@mediatek.com>
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*/
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#ifndef CLKBUF_DCXO_6366_H
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#define CLKBUF_DCXO_6366_H
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#include "mtk-clkbuf-dcxo.h"
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#define MT6366_DCXO_CW00 (0x788)
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#define MT6366_DCXO_CW03 (0x792)
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#define MT6366_DCXO_CW04 (0x794)
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#define MT6366_DCXO_CW08 (0x79c)
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#define MT6366_DCXO_CW09 (0x79e)
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#define MT6366_DCXO_CW11 (0x7a2)
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#define MT6366_DCXO_CW12 (0x7a8)
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#define MT6366_DCXO_CW13 (0x7aa)
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#define MT6366_DCXO_CW15 (0x7ae)
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#define MT6366_DCXO_CW16 (0x7b0)
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#define MT6366_DCXO_CW18 (0x7b4)
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#define MT6366_DCXO_CW19 (0x7b6)
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#define MT6366_DCXO_CW20 (0x7b8)
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#define MT6366_DCXO_CW23 (0x7be)
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/* Register_DCXO_REG*/
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#define MT6366_XO_EXTBUF1_MODE_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF1_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF1_MODE_SHIFT (0)
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#define MT6366_XO_EXTBUF1_EN_M_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF1_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF1_EN_M_SHIFT (2)
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#define MT6366_XO_EXTBUF2_MODE_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF2_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF2_MODE_SHIFT (3)
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#define MT6366_XO_EXTBUF2_EN_M_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF2_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF2_EN_M_SHIFT (5)
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#define MT6366_XO_EXTBUF3_MODE_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF3_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF3_MODE_SHIFT (6)
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#define MT6366_XO_EXTBUF3_EN_M_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF3_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF3_EN_M_SHIFT (8)
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#define MT6366_XO_EXTBUF4_MODE_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF4_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF4_MODE_SHIFT (9)
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#define MT6366_XO_EXTBUF4_EN_M_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_EXTBUF4_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF4_EN_M_SHIFT (11)
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#define MT6366_XO_CDAC_FPM_ADDR (MT6366_DCXO_CW04)
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#define MT6366_XO_CDAC_FPM_MASK (0xFF)
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#define MT6366_XO_CDAC_FPM_SHIFT (0)
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#define MT6366_XO_AAC_FPM_SWEN_ADDR (MT6366_DCXO_CW09)
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#define MT6366_XO_AAC_FPM_SWEN_MASK (0x1)
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#define MT6366_XO_AAC_FPM_SWEN_SHIFT (14)
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#define MT6366_XO_EXTBUF6_MODE_ADDR (MT6366_DCXO_CW11)
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#define MT6366_XO_EXTBUF6_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF6_MODE_SHIFT (8)
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#define MT6366_XO_EXTBUF6_EN_M_ADDR (MT6366_DCXO_CW11)
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#define MT6366_XO_EXTBUF6_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF6_EN_M_SHIFT (10)
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#define MT6366_XO_EXTBUF7_MODE_ADDR (MT6366_DCXO_CW11)
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#define MT6366_XO_EXTBUF7_MODE_MASK (0x3)
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#define MT6366_XO_EXTBUF7_MODE_SHIFT (11)
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#define MT6366_XO_EXTBUF7_EN_M_ADDR (MT6366_DCXO_CW11)
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#define MT6366_XO_EXTBUF7_EN_M_MASK (0x1)
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#define MT6366_XO_EXTBUF7_EN_M_SHIFT (13)
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#define MT6366_XO_BB_LPM_EN_M_ADDR (MT6366_DCXO_CW00)
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#define MT6366_XO_BB_LPM_EN_M_MASK (0x1)
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#define MT6366_XO_BB_LPM_EN_M_SHIFT (12)
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#define MT6366_RG_XO_HEATER_SEL_ADDR (MT6366_DCXO_CW20)
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#define MT6366_RG_XO_HEATER_SEL_MASK (0x3)
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#define MT6366_RG_XO_HEATER_SEL_SHIFT (1)
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#define MT6366_XO_BB_LPM_EN_SEL_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_BB_LPM_EN_SEL_MASK (0x1)
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#define MT6366_XO_BB_LPM_EN_SEL_SHIFT (0)
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#define MT6366_XO_EXTBUF1_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF1_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF1_BBLPM_EN_MASK_SHIFT (1)
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#define MT6366_XO_EXTBUF2_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF2_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF2_BBLPM_EN_MASK_SHIFT (2)
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#define MT6366_XO_EXTBUF3_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF3_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF3_BBLPM_EN_MASK_SHIFT (3)
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#define MT6366_XO_EXTBUF4_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF4_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF4_BBLPM_EN_MASK_SHIFT (4)
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#define MT6366_XO_EXTBUF6_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF6_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF6_BBLPM_EN_MASK_SHIFT (5)
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#define MT6366_XO_EXTBUF7_BBLPM_EN_MASK_ADDR (MT6366_DCXO_CW23)
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#define MT6366_XO_EXTBUF7_BBLPM_EN_MASK_MASK (0x1)
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#define MT6366_XO_EXTBUF7_BBLPM_EN_MASK_SHIFT (6)
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#define MT6366_RG_XO_EXTBUF1_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF1_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF1_HD_SHIFT (2)
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#define MT6366_RG_XO_EXTBUF2_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF2_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF2_HD_SHIFT (4)
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#define MT6366_RG_XO_EXTBUF3_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF3_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF3_HD_SHIFT (6)
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#define MT6366_RG_XO_EXTBUF4_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF4_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF4_HD_SHIFT (8)
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#define MT6366_RG_XO_EXTBUF6_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF6_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF6_HD_SHIFT (12)
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#define MT6366_RG_XO_EXTBUF7_HD_ADDR (MT6366_DCXO_CW15)
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#define MT6366_RG_XO_EXTBUF7_HD_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF7_HD_SHIFT (14)
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#define MT6366_XO_STATIC_AUXOUT_SEL_ADDR (MT6366_DCXO_CW18)
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#define MT6366_XO_STATIC_AUXOUT_SEL_MASK (0x3f)
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#define MT6366_XO_STATIC_AUXOUT_SEL_SHIFT (0)
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#define MT6366_XO_AUXOUT_SEL_ADDR (MT6366_DCXO_CW18)
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#define MT6366_XO_AUXOUT_SEL_MASK (0x3ff)
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#define MT6366_XO_AUXOUT_SEL_SHIFT (6)
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#define MT6366_XO_STATIC_AUXOUT_ADDR (MT6366_DCXO_CW19)
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#define MT6366_XO_STATIC_AUXOUT_MASK (0xffff)
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#define MT6366_XO_STATIC_AUXOUT_SHIFT (0)
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#define MT6366_RG_XO_EXTBUF1_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF1_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF1_ISET_SHIFT (0)
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#define MT6366_RG_XO_EXTBUF2_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF2_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF2_ISET_SHIFT (2)
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#define MT6366_RG_XO_EXTBUF3_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF3_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF3_ISET_SHIFT (4)
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#define MT6366_RG_XO_EXTBUF4_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF4_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF4_ISET_SHIFT (6)
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#define MT6366_RG_XO_EXTBUF6_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF6_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF6_ISET_SHIFT (10)
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#define MT6366_RG_XO_EXTBUF7_ISET_ADDR (MT6366_DCXO_CW16)
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#define MT6366_RG_XO_EXTBUF7_ISET_MASK (0x3)
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#define MT6366_RG_XO_EXTBUF7_ISET_SHIFT (12)
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enum MT6366_XO_NAME {
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XO_SOC = 0,
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XO_WCN,
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XO_NFC,
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XO_CEL,
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XO_RSV1,
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XO_RSV2,
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XO_EXT,
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MT6366_XO_NUM,
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};
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#endif /* CLKBUF_DCXO_6366_H */
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