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https://github.com/physwizz/a155-U-u1.git
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186 lines
8.3 KiB
C
186 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: ren-ting.wang <ren-ting.wang@mediatek.com>
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*/
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#ifndef CLKBUF_DCXO_6359P_H
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#define CLKBUF_DCXO_6359P_H
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#include "mtk-clkbuf-dcxo.h"
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#define MT6359P_PMRC_CON0 (0x1A6)
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#define MT6359P_TOP_SPI_CON1 (0x458)
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#define MT6359P_XO_BUF_CTL0 (0x54c)
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#define MT6359P_XO_BUF_CTL1 (0x54e)
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#define MT6359P_XO_BUF_CTL2 (0x550)
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#define MT6359P_XO_BUF_CTL3 (0x552)
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#define MT6359P_XO_BUF_CTL4 (0x554)
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#define MT6359P_DCXO_CW00 (0x788)
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#define MT6359P_DCXO_CW08 (0x79c)
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#define MT6359P_DCXO_CW09 (0x79e)
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#define MT6359P_DCXO_CW12 (0x7a8)
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#define MT6359P_DCXO_CW13 (0x7aa)
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#define MT6359P_DCXO_CW16 (0x7b0)
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#define MT6359P_DCXO_CW17 (0x7b2)
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#define MT6359P_DCXO_CW19 (0x7b6)
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#define MT6359P_LDO_VRFCK_ELR (0x1b40)
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#define MT6359P_LDO_VRFCK_CON0 (0x1d1c)
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#define MT6359P_LDO_VRFCK_OP_EN (0x1d22)
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#define MT6359P_LDO_VRFCK_OP_EN_SET (0x1d24)
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#define MT6359P_LDO_VRFCK_OP_EN_CLR (0x1d26)
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#define MT6359P_LDO_VBBCK_CON0 (0x1d2e)
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#define MT6359P_LDO_VBBCK_OP_EN (0x1d34)
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#define MT6359P_LDO_VBBCK_OP_EN_SET (0x1d36)
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#define MT6359P_LDO_VBBCK_OP_EN_CLR (0x1d38)
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#define MT6359P_DCXO_ADLDO_BIAS_ELR_0 (0x209c)
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#define MT6359P_DCXO_ADLDO_BIAS_ELR_1 (0x209e)
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/* Register_TOP_REG */
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#define MT6359P_PMRC_EN_ADDR (MT6359P_PMRC_CON0)
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#define MT6359P_PMRC_EN_MASK (0xFFFF)
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#define MT6359P_PMRC_EN_SHIFT (0)
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/* Register_PLT_REG*/
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#define MT6359P_RG_SRCLKEN_IN3_EN_ADDR (MT6359P_TOP_SPI_CON1)
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#define MT6359P_RG_SRCLKEN_IN3_EN_MASK (0x1)
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#define MT6359P_RG_SRCLKEN_IN3_EN_SHIFT (0)
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/* Register_SCK_REG*/
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#define MT6359P_XO_SOC_VOTE_ADDR (MT6359P_XO_BUF_CTL0)
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#define MT6359P_XO_SOC_VOTE_MASK (0x7ff)
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#define MT6359P_XO_SOC_VOTE_SHIFT (0)
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#define MT6359P_XO_WCN_VOTE_ADDR (MT6359P_XO_BUF_CTL1)
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#define MT6359P_XO_WCN_VOTE_MASK (0x7ff)
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#define MT6359P_XO_WCN_VOTE_SHIFT (0)
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#define MT6359P_XO_NFC_VOTE_ADDR (MT6359P_XO_BUF_CTL2)
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#define MT6359P_XO_NFC_VOTE_MASK (0x7ff)
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#define MT6359P_XO_NFC_VOTE_SHIFT (0)
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#define MT6359P_XO_CEL_VOTE_ADDR (MT6359P_XO_BUF_CTL3)
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#define MT6359P_XO_CEL_VOTE_MASK (0x7ff)
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#define MT6359P_XO_CEL_VOTE_SHIFT (0)
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#define MT6359P_XO_EXT_VOTE_ADDR (MT6359P_XO_BUF_CTL4)
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#define MT6359P_XO_EXT_VOTE_MASK (0x7ff)
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#define MT6359P_XO_EXT_VOTE_SHIFT (0)
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/* Register_DCXO_REG*/
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#define MT6359P_XO_EXTBUF1_MODE_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF1_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF1_MODE_SHIFT (0)
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#define MT6359P_XO_EXTBUF1_EN_M_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF1_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF1_EN_M_SHIFT (2)
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#define MT6359P_XO_EXTBUF2_MODE_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF2_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF2_MODE_SHIFT (3)
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#define MT6359P_XO_EXTBUF2_EN_M_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF2_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF2_EN_M_SHIFT (5)
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#define MT6359P_XO_EXTBUF3_MODE_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF3_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF3_MODE_SHIFT (6)
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#define MT6359P_XO_EXTBUF3_EN_M_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF3_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF3_EN_M_SHIFT (8)
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#define MT6359P_XO_EXTBUF4_MODE_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF4_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF4_MODE_SHIFT (9)
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#define MT6359P_XO_EXTBUF4_EN_M_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_EXTBUF4_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF4_EN_M_SHIFT (11)
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#define MT6359P_XO_BB_LPM_EN_M_ADDR (MT6359P_DCXO_CW00)
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#define MT6359P_XO_BB_LPM_EN_M_MASK (0x1)
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#define MT6359P_XO_BB_LPM_EN_M_SHIFT (12)
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#define MT6359P_XO_PMIC_TOP_DIG_SW_ADDR (MT6359P_DCXO_CW08)
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#define MT6359P_XO_PMIC_TOP_DIG_SW_MASK (0x1)
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#define MT6359P_XO_PMIC_TOP_DIG_SW_SHIFT (2)
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#define MT6359P_XO_EXTBUF6_MODE_ADDR (MT6359P_DCXO_CW09)
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#define MT6359P_XO_EXTBUF6_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF6_MODE_SHIFT (9)
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#define MT6359P_XO_EXTBUF6_EN_M_ADDR (MT6359P_DCXO_CW09)
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#define MT6359P_XO_EXTBUF6_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF6_EN_M_SHIFT (11)
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#define MT6359P_XO_EXTBUF7_MODE_ADDR (MT6359P_DCXO_CW09)
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#define MT6359P_XO_EXTBUF7_MODE_MASK (0x3)
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#define MT6359P_XO_EXTBUF7_MODE_SHIFT (12)
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#define MT6359P_XO_EXTBUF7_EN_M_ADDR (MT6359P_DCXO_CW09)
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#define MT6359P_XO_EXTBUF7_EN_M_MASK (0x1)
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#define MT6359P_XO_EXTBUF7_EN_M_SHIFT (14)
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#define MT6359P_XO_BB_LPM_EN_SEL_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_BB_LPM_EN_SEL_MASK (0x1)
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#define MT6359P_XO_BB_LPM_EN_SEL_SHIFT (0)
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#define MT6359P_XO_EXTBUF1_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF1_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF1_BBLPM_EN_MASK_SHIFT (1)
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#define MT6359P_XO_EXTBUF2_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF2_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF2_BBLPM_EN_MASK_SHIFT (2)
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#define MT6359P_XO_EXTBUF3_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF3_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF3_BBLPM_EN_MASK_SHIFT (3)
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#define MT6359P_XO_EXTBUF4_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF4_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF4_BBLPM_EN_MASK_SHIFT (4)
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#define MT6359P_XO_EXTBUF6_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF6_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF6_BBLPM_EN_MASK_SHIFT (5)
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#define MT6359P_XO_EXTBUF7_BBLPM_EN_MASK_ADDR (MT6359P_DCXO_CW12)
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#define MT6359P_XO_EXTBUF7_BBLPM_EN_MASK_MASK (0x1)
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#define MT6359P_XO_EXTBUF7_BBLPM_EN_MASK_SHIFT (6)
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#define MT6359P_RG_XO_EXTBUF2_SRSEL_ADDR (MT6359P_DCXO_CW13)
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#define MT6359P_RG_XO_EXTBUF2_SRSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF2_SRSEL_SHIFT (0)
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#define MT6359P_RG_XO_EXTBUF4_SRSEL_ADDR (MT6359P_DCXO_CW13)
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#define MT6359P_RG_XO_EXTBUF4_SRSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF4_SRSEL_SHIFT (4)
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#define MT6359P_RG_XO_EXTBUF3_HD_ADDR (MT6359P_DCXO_CW13)
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#define MT6359P_RG_XO_EXTBUF3_HD_MASK (0x3)
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#define MT6359P_RG_XO_EXTBUF3_HD_SHIFT (10)
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#define MT6359P_XO_STATIC_AUXOUT_SEL_ADDR (MT6359P_DCXO_CW16)
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#define MT6359P_XO_STATIC_AUXOUT_SEL_MASK (0x3f)
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#define MT6359P_XO_STATIC_AUXOUT_SEL_SHIFT (0)
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#define MT6359P_XO_AUXOUT_SEL_ADDR (MT6359P_DCXO_CW16)
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#define MT6359P_XO_AUXOUT_SEL_MASK (0x3ff)
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#define MT6359P_XO_AUXOUT_SEL_SHIFT (6)
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#define MT6359P_XO_STATIC_AUXOUT_ADDR (MT6359P_DCXO_CW17)
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#define MT6359P_XO_STATIC_AUXOUT_MASK (0xffff)
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#define MT6359P_XO_STATIC_AUXOUT_SHIFT (0)
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#define MT6359P_RG_XO_EXTBUF1_RSEL_ADDR (MT6359P_DCXO_CW19)
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#define MT6359P_RG_XO_EXTBUF1_RSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF1_RSEL_SHIFT (1)
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#define MT6359P_RG_XO_EXTBUF2_RSEL_ADDR (MT6359P_DCXO_CW19)
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#define MT6359P_RG_XO_EXTBUF2_RSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF2_RSEL_SHIFT (4)
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#define MT6359P_RG_XO_EXTBUF3_RSEL_ADDR (MT6359P_DCXO_CW19)
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#define MT6359P_RG_XO_EXTBUF3_RSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF3_RSEL_SHIFT (7)
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#define MT6359P_RG_XO_EXTBUF4_RSEL_ADDR (MT6359P_DCXO_CW19)
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#define MT6359P_RG_XO_EXTBUF4_RSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF4_RSEL_SHIFT (10)
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#define MT6359P_RG_XO_EXTBUF7_RSEL_ADDR (MT6359P_DCXO_CW19)
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#define MT6359P_RG_XO_EXTBUF7_RSEL_MASK (0x7)
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#define MT6359P_RG_XO_EXTBUF7_RSEL_SHIFT (13)
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/* Register_LDO_REG*/
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#define MT6359P_RG_LDO_VRFCK_ANA_SEL_ADDR (MT6359P_LDO_VRFCK_ELR)
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#define MT6359P_RG_LDO_VRFCK_ANA_SEL_MASK (0x1)
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#define MT6359P_RG_LDO_VRFCK_ANA_SEL_SHIFT (0)
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#define MT6359P_RG_LDO_VRFCK_EN_ADDR (MT6359P_LDO_VRFCK_CON0)
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#define MT6359P_RG_LDO_VRFCK_EN_MASK (0x1)
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#define MT6359P_RG_LDO_VRFCK_EN_SHIFT (0)
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#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR (MT6359P_LDO_VRFCK_OP_EN)
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#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_MASK (0x1)
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#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_SHIFT (14)
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#define MT6359P_RG_LDO_VBBCK_EN_ADDR (MT6359P_LDO_VBBCK_CON0)
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#define MT6359P_RG_LDO_VBBCK_EN_MASK (0x1)
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#define MT6359P_RG_LDO_VBBCK_EN_SHIFT (0)
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#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR (MT6359P_LDO_VBBCK_OP_EN)
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#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_MASK (0x1)
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#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_SHIFT (14)
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#define MT6359P_RG_VRFCK_HV_EN_ADDR (MT6359P_DCXO_ADLDO_BIAS_ELR_0)
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#define MT6359P_RG_VRFCK_HV_EN_MASK (0x1)
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#define MT6359P_RG_VRFCK_HV_EN_SHIFT (9)
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#define MT6359P_RG_VRFCK_NDIS_EN_ADDR (MT6359P_DCXO_ADLDO_BIAS_ELR_0)
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#define MT6359P_RG_VRFCK_NDIS_EN_MASK (0x1)
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#define MT6359P_RG_VRFCK_NDIS_EN_SHIFT (11)
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#define MT6359P_RG_VRFCK_1_NDIS_EN_ADDR (MT6359P_DCXO_ADLDO_BIAS_ELR_1)
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#define MT6359P_RG_VRFCK_1_NDIS_EN_MASK (0x1)
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#define MT6359P_RG_VRFCK_1_NDIS_EN_SHIFT (0)
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#endif /* CLKBUF_DCXO_6359P_H */
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