mirror of
https://github.com/physwizz/a155-U-u1.git
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427 lines
9.8 KiB
C
427 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#include "vpu_cfg.h"
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#include "vpu_cmn.h"
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#ifdef VPU_EFUSE_READY // TODO: update header for get_devinfo_with_index()
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#include "mtk_devinfo.h"
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#endif
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#include "vpu_debug.h"
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#include <soc/mediatek/emi.h>
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static void vpu_emi_mpu_set_dummy(unsigned long start, unsigned int size)
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{
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}
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/* VPU EMI MPU setting for MT6885, MT6873, MT6853, MT6833 */
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static void vpu_emi_mpu_set_mt68xx(unsigned long start, unsigned int size)
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{
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#define MPU_PROCT_REGION 21
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#define MPU_PROCT_D0_AP 0
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#define MPU_PROCT_D5_APUSYS 5
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#if IS_ENABLED(CONFIG_MTK_EMI)
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struct emimpu_region_t md_region;
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mtk_emimpu_init_region(&md_region, MPU_PROCT_REGION);
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mtk_emimpu_set_addr(&md_region, start,
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(start + (unsigned long)size) - 0x1);
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mtk_emimpu_set_apc(&md_region, MPU_PROCT_D0_AP,
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MTK_EMIMPU_NO_PROTECTION);
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mtk_emimpu_set_apc(&md_region, MPU_PROCT_D5_APUSYS,
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MTK_EMIMPU_NO_PROTECTION);
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mtk_emimpu_lock_region(&md_region, true);
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mtk_emimpu_set_protection(&md_region);
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mtk_emimpu_free_region(&md_region);
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#endif
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#undef MPU_PROCT_REGION
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#undef MPU_PROCT_D0_AP
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#undef MPU_PROCT_D5_APUSYS
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}
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/**
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* vpu_is_disabled - enable/disable vpu from efuse
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* @vd: struct vpu_device to get the id
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*
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* return 1: this vd->id is disabled
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* return 0: this vd->id is enabled
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*/
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static bool vpu_is_disabled_dummy(struct vpu_device *vd)
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{
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return false;
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}
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static bool vpu_is_disabled_mt6885(struct vpu_device *vd)
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{
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#ifdef VPU_EFUSE_READY
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#define EFUSE_VPU_OFFSET 5
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#define EFUSE_VPU_MASK 0x7
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#define EFUSE_VPU_SHIFT 16
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#define EFUSE_SEG_OFFSET 30
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bool ret;
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unsigned int efuse;
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unsigned int seg;
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unsigned int mask;
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mask = 1 << vd->id;
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seg = get_devinfo_with_index(EFUSE_SEG_OFFSET);
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efuse = get_devinfo_with_index(EFUSE_VPU_OFFSET);
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efuse = (efuse >> EFUSE_VPU_SHIFT) & EFUSE_VPU_MASK;
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/* disabled by mask, or disabled by segment */
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ret = (efuse & mask) || ((seg == 0x1) && (vd->id >= 2));
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/* show efuse info to let user know */
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pr_info("%s: seg: 0x%x, efuse: 0x%x, core%d is %s\n",
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__func__, seg, efuse, vd->id,
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ret ? "disabled" : "enabled");
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return ret;
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#undef EFUSE_VPU_OFFSET
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#undef EFUSE_VPU_MASK
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#undef EFUSE_VPU_SHIFT
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#undef EFUSE_SEG_OFFSET
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#else
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return false;
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#endif
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}
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/* VPU register setting for MT6885, MT6873, MT6853, MT6833 */
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struct vpu_register vpu_reg_mt68xx = {
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/* register defines */
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.mbox_inbox_0 = 0x000,
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.mbox_inbox_1 = 0x004,
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.mbox_inbox_2 = 0x008,
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.mbox_inbox_3 = 0x00c,
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.mbox_inbox_4 = 0x010,
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.mbox_inbox_5 = 0x014,
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.mbox_inbox_6 = 0x018,
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.mbox_inbox_7 = 0x01c,
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.mbox_inbox_8 = 0x020,
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.mbox_inbox_9 = 0x024,
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.mbox_inbox_10 = 0x028,
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.mbox_inbox_11 = 0x02c,
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.mbox_inbox_12 = 0x030,
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.mbox_inbox_13 = 0x034,
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.mbox_inbox_14 = 0x038,
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.mbox_inbox_15 = 0x03c,
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.mbox_inbox_16 = 0x040,
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.mbox_inbox_17 = 0x044,
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.mbox_inbox_18 = 0x048,
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.mbox_inbox_19 = 0x04c,
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.mbox_inbox_20 = 0x050,
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.mbox_inbox_21 = 0x054,
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.mbox_inbox_22 = 0x058,
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.mbox_inbox_23 = 0x05c,
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.mbox_inbox_24 = 0x060,
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.mbox_inbox_25 = 0x064,
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.mbox_inbox_26 = 0x068,
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.mbox_inbox_27 = 0x06c,
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.mbox_inbox_28 = 0x070,
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.mbox_inbox_29 = 0x074,
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.mbox_inbox_30 = 0x078,
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.mbox_inbox_31 = 0x07c,
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.mbox_dummy_0 = 0x080,
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.mbox_dummy_1 = 0x084,
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.mbox_dummy_2 = 0x088,
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.mbox_dummy_3 = 0x08c,
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.mbox_dummy_4 = 0x090,
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.mbox_dummy_5 = 0x094,
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.mbox_dummy_6 = 0x098,
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.mbox_dummy_7 = 0x09c,
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.mbox_inbox_irq = 0x0a0,
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.mbox_inbox_mask = 0x0a4,
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.mbox_inbox_pri_mask = 0x0a8,
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.cg_con = 0x100,
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.cg_clr = 0x108,
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.sw_rst = 0x10c,
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.done_st = 0x90c,
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.ctrl = 0x910,
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.xtensa_int = 0x200,
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.ctl_xtensa_int = 0x204,
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.default0 = 0x93c,
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.default1 = 0x940,
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.default2 = 0x944,
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.xtensa_info00 = 0x250,
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.xtensa_info01 = 0x254,
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.xtensa_info02 = 0x258,
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.xtensa_info03 = 0x25c,
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.xtensa_info04 = 0x260,
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.xtensa_info05 = 0x264,
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.xtensa_info06 = 0x268,
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.xtensa_info07 = 0x26c,
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.xtensa_info08 = 0x270,
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.xtensa_info09 = 0x274,
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.xtensa_info10 = 0x278,
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.xtensa_info11 = 0x27c,
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.xtensa_info12 = 0x280,
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.xtensa_info13 = 0x284,
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.xtensa_info14 = 0x288,
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.xtensa_info15 = 0x28c,
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.xtensa_info16 = 0x290,
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.xtensa_info17 = 0x294,
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.xtensa_info18 = 0x298,
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.xtensa_info19 = 0x29c,
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.xtensa_info20 = 0x2a0,
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.xtensa_info21 = 0x2a4,
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.xtensa_info22 = 0x2a8,
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.xtensa_info23 = 0x2ac,
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.xtensa_info24 = 0x2b0,
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.xtensa_info25 = 0x2b4,
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.xtensa_info26 = 0x2b8,
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.xtensa_info27 = 0x2bc,
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.xtensa_info28 = 0x2c0,
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.xtensa_info29 = 0x2c4,
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.xtensa_info30 = 0x2c8,
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.xtensa_info31 = 0x2cc,
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.debug_info00 = 0x2d0,
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.debug_info01 = 0x2d4,
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.debug_info02 = 0x2d8,
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.debug_info03 = 0x2dc,
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.debug_info04 = 0x2e0,
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.debug_info05 = 0x2e4,
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.debug_info06 = 0x2e8,
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.debug_info07 = 0x2ec,
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.xtensa_altresetvec = 0x2f8,
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/* register config: ctrl */
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.p_debug_enable = (1 << 31),
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.state_vector_select = (1 << 19),
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.pbclk_enable = (1 << 26),
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.prid = (0x1fffe),
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.pif_gated = (1 << 17),
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.stall = (1 << 23),
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/* register config: sw_rst */
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.apu_d_rst = (1 << 8),
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.apu_b_rst = (1 << 4),
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.ocdhaltonreset = (1 << 12),
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/* register config: default0 */
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.aruser = (0x2 << 23),
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.awuser = (0x2 << 18),
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.qos_swap = (1 << 28),
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/* register config: default1 */
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.aruser_idma = (0x2 << 0),
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.awuser_idma = (0x2 << 5),
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/* register config: default2 */
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.dbg_en = (0xf),
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/* register config: cg_clr */
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.jtag_cg_clr = (0x2),
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/* register mask: done_st */
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.pwaitmode = (1 << 7),
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};
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/* VPU register setting for MT6779, MT6785 */
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struct vpu_register vpu_reg_mt67xx = {
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/* register defines */
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.cg_con = 0x0,
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.cg_clr = 0x8,
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.sw_rst = 0xc,
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.done_st = 0x10c,
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.ctrl = 0x110,
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.xtensa_int = 0x114,
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.ctl_xtensa_int = 0x118,
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.default0 = 0x13c,
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.default1 = 0x140,
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.default2 = 0x144,
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.xtensa_info00 = 0x150,
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.xtensa_info01 = 0x154,
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.xtensa_info02 = 0x158,
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.xtensa_info03 = 0x15c,
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.xtensa_info04 = 0x160,
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.xtensa_info05 = 0x164,
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.xtensa_info06 = 0x168,
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.xtensa_info07 = 0x16c,
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.xtensa_info08 = 0x170,
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.xtensa_info09 = 0x174,
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.xtensa_info10 = 0x178,
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.xtensa_info11 = 0x17c,
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.xtensa_info12 = 0x180,
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.xtensa_info13 = 0x184,
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.xtensa_info14 = 0x188,
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.xtensa_info15 = 0x18c,
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.xtensa_info16 = 0x190,
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.xtensa_info17 = 0x194,
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.xtensa_info18 = 0x198,
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.xtensa_info19 = 0x19c,
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.xtensa_info20 = 0x1a0,
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.xtensa_info21 = 0x1a4,
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.xtensa_info22 = 0x1a8,
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.xtensa_info23 = 0x1ac,
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.xtensa_info24 = 0x1b0,
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.xtensa_info25 = 0x1b4,
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.xtensa_info26 = 0x1b8,
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.xtensa_info27 = 0x1bc,
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.xtensa_info28 = 0x1c0,
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.xtensa_info29 = 0x1c4,
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.xtensa_info30 = 0x1c8,
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.xtensa_info31 = 0x1cc,
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.debug_info00 = 0x1d0,
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.debug_info01 = 0x1d4,
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.debug_info02 = 0x1d8,
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.debug_info03 = 0x1dc,
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.debug_info04 = 0x1e0,
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.debug_info05 = 0x1e4,
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.debug_info06 = 0x1e8,
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.debug_info07 = 0x1ec,
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.xtensa_altresetvec = 0x1f8,
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/* register config: ctrl */
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.p_debug_enable = (1 << 31),
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.state_vector_select = (1 << 19),
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.pbclk_enable = (1 << 26),
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.prid = (0x1fffe),
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.pif_gated = (1 << 17),
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.stall = (1 << 23),
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/* register config: sw_rst */
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.apu_d_rst = (1 << 8),
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.apu_b_rst = (1 << 4),
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.ocdhaltonreset = (1 << 12),
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/* register config: default0 */
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.aruser = (0x8 << 23),
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.awuser = (0x8 << 18),
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.qos_swap = (1 << 28),
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/* register config: default1 */
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.aruser_idma = (0x8 << 0),
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.awuser_idma = (0x8 << 5),
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/* register config: default2 */
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.dbg_en = (0xf),
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/* register config: cg_clr */
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.jtag_cg_clr = (0x2),
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/* register mask: done_st */
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.pwaitmode = (1 << 7),
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};
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/* VPU config for MT6885, MT6873, MT6853, MT6833 */
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struct vpu_config vpu_cfg_mt68xx = {
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.host_ver = HOST_VERSION,
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.iova_bank = 0x300000000ULL,
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.iova_start = 0x70000000,
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.iova_heap = 0x80000000,
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.iova_end = 0x82600000,
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.bin_type = VPU_IMG_PRELOAD, // VPU_IMG_LEGACY, VPU_IMG_PRELOAD
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.bin_sz_code = 0x2a10000,
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.bin_ofs_algo = 0xc00000,
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.bin_ofs_imem = (0x2a10000 - 0xc0000),
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.bin_ofs_header = (0x2a10000 - 0x30000),
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.cmd_timeout = 9000,
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.pw_off_latency_ms = 3000,
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.wait_cmd_latency_us = 2000,
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.wait_cmd_retry = 5,
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.wait_xos_latency_us = 500,
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.wait_xos_retry = 10,
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.xos = VPU_XOS,
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.xos_timeout = 1000000,
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.max_prio = VPU_MAX_PRIORITY,
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/* Log Buffer */
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.log_ofs = 0,
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.log_header_sz = 0x10,
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/* Dump: Sizes */
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.dmp_sz_reset = 0x400U,
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.dmp_sz_main = 0x40000U, // 256 KB
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.dmp_sz_kernel = 0x20000U, // 128 KB
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.dmp_sz_preload = 0x20000U, // 128 KB
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.dmp_sz_iram = 0x10000U, // 64 KB
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.dmp_sz_work = 0x2000U, // 8 KB
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.dmp_sz_reg = 0x1000U, // 4 KB
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.dmp_sz_imem = 0x30000U, // 192 KB
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.dmp_sz_dmem = 0x40000U, // 256 KB
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/* Dump: Registers */
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.dmp_reg_cnt_info = 32,
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.dmp_reg_cnt_dbg = 8,
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.dmp_reg_cnt_mbox = 32,
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};
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// TODO: mt6779, mt6785 UT/IT
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/* VPU config for MT6779, MT6785 */
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struct vpu_config vpu_cfg_mt67xx = {
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.host_ver = HOST_VERSION,
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.iova_bank = 0,
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.iova_start = 0x70000000,
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.iova_heap = 0x70000000,
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.iova_end = 0x80000000,
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.bin_type = VPU_IMG_LEGACY, // VPU_IMG_LEGACY, VPU_IMG_PRELOAD
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.bin_sz_code = 0x2a10000,
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.bin_ofs_algo = 0xc00000,
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.bin_ofs_imem = (0x2a10000 - 0xc0000),
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.bin_ofs_header = (0x2a10000 - 0x30000),
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.cmd_timeout = 9000,
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.pw_off_latency_ms = 3000,
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.wait_cmd_latency_us = 2000,
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.wait_cmd_retry = 5,
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.wait_xos_latency_us = 500,
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.wait_xos_retry = 10,
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.xos = VPU_NON_XOS,
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.xos_timeout = 1000000,
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.max_prio = 1,
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/* Log Buffer */
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.log_ofs = 0,
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.log_header_sz = 0x10,
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/* Dump: Sizes */
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.dmp_sz_reset = 0x400U,
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.dmp_sz_main = 0x40000U, // 256 KB
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.dmp_sz_kernel = 0x20000U, // 128 KB
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.dmp_sz_preload = 0x20000U, // 128 KB
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.dmp_sz_iram = 0x10000U, // 64 KB
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.dmp_sz_work = 0x2000U, // 8 KB
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.dmp_sz_reg = 0x1000U, // 4 KB
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.dmp_sz_imem = 0x30000U, // 192 KB
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.dmp_sz_dmem = 0x40000U, // 256 KB
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/* Dump: Registers */
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.dmp_reg_cnt_info = 32,
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.dmp_reg_cnt_dbg = 8,
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.dmp_reg_cnt_mbox = 0,
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};
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struct vpu_misc_ops vpu_cops_mt6885 = {
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.emi_mpu_set = vpu_emi_mpu_set_mt68xx,
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.is_disabled = vpu_is_disabled_mt6885,
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};
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struct vpu_misc_ops vpu_cops_mt68xx = {
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.emi_mpu_set = vpu_emi_mpu_set_mt68xx,
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.is_disabled = vpu_is_disabled_dummy,
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};
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// TODO: implement misc ops for mt67xx
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struct vpu_misc_ops vpu_cops_mt67xx = {
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.emi_mpu_set = vpu_emi_mpu_set_dummy,
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.is_disabled = vpu_is_disabled_dummy,
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};
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