mirror of
https://github.com/physwizz/a155-U-u1.git
synced 2025-09-26 19:04:54 +00:00
587 lines
14 KiB
C
587 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <apusys_device.h>
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#include <common/mdla_driver.h>
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#include <common/mdla_device.h>
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#include <utilities/mdla_debug.h>
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#include <utilities/mdla_util.h>
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#include <utilities/mdla_profile.h>
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#include <platform/mdla_plat_api.h>
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struct mdla_pmu_result {
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u16 cmd_len;
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u16 cmd_id;
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u32 pmu_val[MDLA_PMU_COUNTERS + 1]; /* global counter + PMU counter*/
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};
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/* platform */
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u32 mdla_util_get_core_num(void)
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{
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return mdla_plat_get_core_num();
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}
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u32 mdla_util_get_ip_version(void)
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{
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return get_major_num(mdla_plat_get_version());
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}
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const struct of_device_id *mdla_util_get_device_id(void)
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{
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return mdla_plat_get_device();
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}
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int mdla_util_plat_init(struct platform_device *pdev)
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{
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if (mdla_plat_init(pdev) != 0)
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return -1;
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mdla_dbg_fs_setup(&pdev->dev);
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if (mdla_plat_micro_p_support())
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return 1;
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//mdla_drv_create_device_node(&pdev->dev);
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mdla_prof_init(mdla_plat_get_prof_ver());
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return 0;
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}
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void mdla_util_plat_deinit(struct platform_device *pdev)
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{
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if (!mdla_plat_micro_p_support()) {
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mdla_prof_deinit();
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mdla_drv_destroy_device_node();
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}
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mdla_plat_deinit(pdev);
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}
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/* pmu */
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static void mdla_util_dummy_cnt_save(u32 a0, struct mdla_pmu_info *a1) {}
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static void mdla_util_dummy_cnt_read(u32 a0, u32 *a1) {}
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static void mdla_util_dummy_cnt_clr(struct mdla_pmu_info *pmu) {}
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static u32 mdla_util_dummy_get_num_evt(u32 a0, int a1)
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{
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return 0;
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}
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static void mdla_util_dummy_set_num_evt(u32 a0, int a1, int a2) {}
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static void mdla_util_dummy_set_mode(struct mdla_pmu_info *a0, u32 a1) {}
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static int mdla_util_dummy_get_mode(struct mdla_pmu_info *a0)
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{
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return 0;
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}
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static u64 mdla_util_dummy_get_addr(struct mdla_pmu_info *a0)
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{
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return 0;
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}
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static u32 mdla_util_dummy_get_val(struct mdla_pmu_info *a0)
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{
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return 0;
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}
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static u16 mdla_util_dummy_get_cmdcnt(struct mdla_pmu_info *a0)
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{
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return 0;
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}
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static u32 mdla_util_dummy_get_data(struct mdla_pmu_info *a0, u32 a1)
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{
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return 0;
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}
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static void mdla_util_dummy_ops(u32 a0) {}
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static void mdla_util_dummy_exec(u32 a0, u16 a1) {}
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static struct mdla_pmu_info *mdla_util_dummy_get_info(u32 a0, u16 a1)
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{
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return NULL;
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}
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static void mdla_util_dummy_set_evt(struct mdla_pmu_info *a0,
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u32 a1, u32 a2)
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{
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}
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static int mdla_util_dummy_prepare(struct mdla_dev *mdla_info,
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struct apusys_cmd_handle *apusys_hd, u16 priority)
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{
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return 0;
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}
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static struct mdla_util_pmu_ops pmu_ops = {
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.reg_counter_save = mdla_util_dummy_cnt_save,
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.reg_counter_read = mdla_util_dummy_cnt_read,
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.clr_counter_variable = mdla_util_dummy_cnt_clr,
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.clr_cycle_variable = mdla_util_dummy_cnt_clr,
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.get_num_evt = mdla_util_dummy_get_num_evt,
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.set_num_evt = mdla_util_dummy_set_num_evt,
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.set_percmd_mode = mdla_util_dummy_set_mode,
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.get_curr_mode = mdla_util_dummy_get_mode,
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.get_perf_end = mdla_util_dummy_get_val,
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.get_perf_cycle = mdla_util_dummy_get_val,
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.get_perf_cmdid = mdla_util_dummy_get_cmdcnt,
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.get_perf_cmdcnt = mdla_util_dummy_get_cmdcnt,
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.get_counter = mdla_util_dummy_get_data,
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.reset_counter = mdla_util_dummy_ops,
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.disable_counter = mdla_util_dummy_ops,
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.enable_counter = mdla_util_dummy_ops,
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.reset = mdla_util_dummy_ops,
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.write_evt_exec = mdla_util_dummy_exec,
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.reset_write_evt_exec = mdla_util_dummy_exec,
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.get_hnd_evt = mdla_util_dummy_get_data,
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.get_hnd_evt_num = mdla_util_dummy_get_val,
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.get_hnd_mode = mdla_util_dummy_get_val,
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.get_hnd_buf_addr = mdla_util_dummy_get_addr,
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.get_hnd_buf_size = mdla_util_dummy_get_val,
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.set_evt_handle = mdla_util_dummy_set_evt,
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.get_info = mdla_util_dummy_get_info,
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.apu_cmd_prepare = mdla_util_dummy_prepare,
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};
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struct mdla_util_pmu_ops *mdla_util_pmu_ops_get(void)
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{
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return &pmu_ops;
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}
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/* apusys pmu */
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static bool mdla_util_pmu_addr_is_invalid(struct apusys_cmd_handle *apusys_hd)
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{
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if (apusys_hd->num_cmdbufs < CMD_PMU_BUF_0_IDX + 1)
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return true;
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if (!apusys_hd->cmdbufs[CMD_PMU_INFO_IDX].kva ||
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!apusys_hd->cmdbufs[CMD_PMU_BUF_0_IDX].kva)
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return true;
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if (apusys_hd->multicore_total == 2) {
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if ((apusys_hd->num_cmdbufs < CMD_PMU_BUF_1_IDX + 1) ||
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!apusys_hd->cmdbufs[CMD_PMU_BUF_1_IDX].kva) {
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return true;
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}
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mdla_pmu_debug("pmu kva: buf0 = %08llx, buf1 = %08llx\n",
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(u64)apusys_hd->cmdbufs[CMD_PMU_BUF_0_IDX].kva,
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(u64)apusys_hd->cmdbufs[CMD_PMU_BUF_1_IDX].kva);
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} else {
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mdla_pmu_debug("pmu kva: buf0 = %08llx\n",
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(u64)apusys_hd->cmdbufs[CMD_PMU_BUF_0_IDX].kva);
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}
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return false;
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}
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static bool apusys_pmu_support;
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void mdla_util_pmu_cmd_timer(bool enable)
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{
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/* Not support polling pmu data with per cmd mode yet */
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}
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/* initial local variable and extract pmu setting from input */
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int mdla_util_apu_pmu_handle(struct mdla_dev *mdla_info,
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struct apusys_cmd_handle *apusys_hd, u16 priority)
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{
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int i, pmu_mode;
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u32 evt, evt_num;
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struct mdla_pmu_info *pmu;
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u32 core_id;
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core_id = mdla_info->mdla_id;
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pmu = pmu_ops.get_info(core_id, priority);
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if (!pmu) {
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mdla_err("%s: No pmu info device\n", __func__);
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return -1;
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}
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pmu_ops.clr_counter_variable(pmu);
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pmu_ops.clr_cycle_variable(pmu);
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if (mdla_prof_use_dbgfs_pmu_event(mdla_info->mdla_id)) {
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pmu_ops.set_num_evt(core_id,
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priority, MDLA_PMU_COUNTERS);
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for (i = 0; i < MDLA_PMU_COUNTERS; i++) {
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evt = mdla_dbg_read_u32(FS_C1 + i);
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pmu_ops.set_evt_handle(pmu, i,
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(evt & 0x1f0000) | (evt & 0xf));
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}
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return 0;
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}
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if (!apusys_pmu_support)
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return -1;
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if (mdla_util_pmu_addr_is_invalid(apusys_hd)) {
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for (i = 0; i < MDLA_PMU_COUNTERS; i++)
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pmu_ops.set_evt_handle(pmu, i, COUNTER_CLEAR);
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return -1;
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}
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if (pmu_ops.apu_cmd_prepare(mdla_info, apusys_hd, priority))
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return -1;
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pmu_mode = pmu_ops.get_curr_mode(pmu);
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evt_num = pmu_ops.get_hnd_evt_num(pmu);
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/* save to local variable */
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pmu_ops.set_percmd_mode(pmu, pmu_mode);
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pmu_ops.set_num_evt(core_id, priority,
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evt_num);
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mdla_pmu_debug("PMU number_of_event:%d, mode: %d\n",
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evt_num,
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pmu_mode);
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for (i = 0; i < evt_num; i++) {
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evt = pmu_ops.get_hnd_evt(pmu, i);
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pmu_ops.set_evt_handle(pmu, i,
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((evt & 0x1f00) << 8) | (evt & 0xf));
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}
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return 0;
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}
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void mdla_util_apu_pmu_update(struct mdla_dev *mdla_info,
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struct apusys_cmd_handle *apusys_hd, u16 priority)
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{
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int i;
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struct mdla_pmu_result result;
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void *base = NULL, *desc = NULL, *src = NULL;
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int sz = 0;
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//int event_num = 0;
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int offset = 0;
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//u16 final_len = 0;
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u16 loop_count;
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u32 core_id;
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struct mdla_pmu_info *pmu;
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if (!apusys_pmu_support)
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return;
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/* FIXME: NOT always upload pmu info to NN? */
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if (mdla_prof_use_dbgfs_pmu_event(mdla_info->mdla_id))
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return;
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if (mdla_util_pmu_addr_is_invalid(apusys_hd))
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return;
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core_id = mdla_info->mdla_id;
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pmu = pmu_ops.get_info(core_id, priority);
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if (!pmu) {
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mdla_err("%s: no pmu info device(core:%d, prio:%d)\n",
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__func__, core_id, priority);
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return;
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}
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//loop_count = pmu->pmu_hnd->number_of_event;
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loop_count = pmu_ops.get_hnd_evt_num(pmu);
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//event_num = loop_count + 1;
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//result.cmd_len = pmu->data.l_cmd_cnt;
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result.cmd_len = pmu_ops.get_perf_cmdcnt(pmu);
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result.cmd_id = pmu_ops.get_perf_cmdid(pmu);
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if (pmu_ops.get_curr_mode(pmu) == PER_CMD) {
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mdla_util_pmu_cmd_timer(false);
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result.pmu_val[0] = pmu_ops.get_perf_end(pmu);
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} else {
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result.pmu_val[0] = pmu_ops.get_perf_cycle(pmu);
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}
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mdla_pmu_debug("global counter:%08x\n", result.pmu_val[0]);
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for (i = 1; i < loop_count; i++) {
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result.pmu_val[i] =
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pmu_ops.get_counter(pmu, i);
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mdla_pmu_debug("event %d cnt :%08x\n",
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i, result.pmu_val[i]);
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}
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mdla_pmu_debug("mode: %d, cmd_len: %d, cmd_id: %d\n",
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pmu_ops.get_hnd_mode(pmu),
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result.cmd_len, result.cmd_id);
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sz = sizeof(struct mdla_pmu_result) - sizeof(u16);
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base = (void *)pmu_ops.get_hnd_buf_addr(pmu);
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if (result.cmd_len)
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offset = sizeof(u16) + (result.cmd_len - 1) * sz;
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else
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return;
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/* update command length */
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((struct mdla_pmu_result *)base)->cmd_len = result.cmd_len;
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if (pmu_ops.get_hnd_buf_size(pmu) < offset + sz)
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return;
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/* update current command pmu result */
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desc = (void *)(base + offset);
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src = (void *)&(result.cmd_id);
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memcpy(desc, src, sz);
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if (result.cmd_id == mdla_info->max_cmd_id) {
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if (unlikely(mdla_dbg_read_u32(FS_KLOG) & MDLA_DBG_PMU)) {
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struct mdla_pmu_result check;
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memset((void *)&check, 0, sizeof(struct mdla_pmu_result));
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check.cmd_len = ((struct mdla_pmu_result *)base)->cmd_len;
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memcpy((void *)&(check.cmd_id), desc, sz);
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mdla_pmu_debug("[-] check cmd_len: %d\n", check.cmd_len);
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mdla_pmu_debug("[-] check offset: %d\n", offset);
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mdla_pmu_debug("[-] check cmd_id: %d\n", check.cmd_id);
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mdla_pmu_debug("[-] check cmd_val[1]: %08x\n", check.pmu_val[1]);
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}
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}
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}
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void mdla_util_apusys_pmu_support(bool enable)
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{
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apusys_pmu_support = enable;
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}
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/* IO operation */
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static struct mdla_reg_ctl *mdla_reg_control;
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static void *apu_conn_top;
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static void *infracfg_ao_top;
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static u32 mdla_util_dummy_core_r(u32 i, u32 ofs) { return 0; }
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static void mdla_util_dummy_core_w(u32 i, u32 ofs, u32 val) {}
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static u32 mdla_util_dummy_r(u32 ofs) { return 0; }
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static void mdla_util_dummy_w(u32 ofs, u32 val) {}
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static struct mdla_util_io_ops io_ops = {
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.cfg = { .read = mdla_util_dummy_core_r,
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.write = mdla_util_dummy_core_w,
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.set_b = mdla_util_dummy_core_w,
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.clr_b = mdla_util_dummy_core_w},
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.cmde = { .read = mdla_util_dummy_core_r,
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.write = mdla_util_dummy_core_w,
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.set_b = mdla_util_dummy_core_w,
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.clr_b = mdla_util_dummy_core_w},
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.biu = { .read = mdla_util_dummy_core_r,
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.write = mdla_util_dummy_core_w,
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.set_b = mdla_util_dummy_core_w,
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.clr_b = mdla_util_dummy_core_w},
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.apu_conn = { .read = mdla_util_dummy_r,
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.write = mdla_util_dummy_w,
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.set_b = mdla_util_dummy_w,
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.clr_b = mdla_util_dummy_w},
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.infra_cfg = { .read = mdla_util_dummy_r,
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.write = mdla_util_dummy_w,
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.set_b = mdla_util_dummy_w,
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.clr_b = mdla_util_dummy_w},
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};
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const struct mdla_util_io_ops *mdla_util_io_ops_get(void)
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{
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return &io_ops;
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}
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static inline void reg_set(void *base, u32 offset, u32 value)
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{
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iowrite32(ioread32(base + offset) | value, base + offset);
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}
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static inline void reg_clr(void *base, u32 offset, u32 value)
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{
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iowrite32(ioread32(base + offset) & (~value), base + offset);
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}
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static u32 mdla_cfg_read(u32 id, u32 offset)
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{
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if (unlikely(core_id_is_invalid(id)))
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return 0;
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return ioread32(mdla_reg_control[id].apu_mdla_config_top + offset);
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}
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static void mdla_cfg_write(u32 id, u32 offset, u32 value)
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{
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if (unlikely(core_id_is_invalid(id)))
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return;
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iowrite32(value, mdla_reg_control[id].apu_mdla_config_top + offset);
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}
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static void mdla_cfg_set_b(u32 id, u32 offset, u32 value)
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{
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if (unlikely(core_id_is_invalid(id)))
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return;
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reg_set(mdla_reg_control[id].apu_mdla_config_top, offset, value);
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}
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static void mdla_cfg_clr_b(u32 id, u32 offset, u32 value)
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{
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if (unlikely(core_id_is_invalid(id)))
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return;
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reg_clr(mdla_reg_control[id].apu_mdla_config_top, offset, value);
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}
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static u32 mdla_reg_read(u32 id, u32 offset)
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{
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if (unlikely(core_id_is_invalid(id)))
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return 0;
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return ioread32(mdla_reg_control[id].apu_mdla_cmde_mreg_top + offset);
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}
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static void mdla_reg_write(u32 id, u32 offset, u32 value)
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{
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if (unlikely(core_id_is_invalid(id)))
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return;
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iowrite32(value, mdla_reg_control[id].apu_mdla_cmde_mreg_top + offset);
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}
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static void mdla_reg_set_b(u32 id, u32 offset, u32 value)
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{
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if (unlikely(core_id_is_invalid(id)))
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return;
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reg_set(mdla_reg_control[id].apu_mdla_cmde_mreg_top, offset, value);
|
|
}
|
|
|
|
static void mdla_reg_clr_b(u32 id, u32 offset, u32 value)
|
|
{
|
|
if (unlikely(core_id_is_invalid(id)))
|
|
return;
|
|
|
|
reg_clr(mdla_reg_control[id].apu_mdla_cmde_mreg_top, offset, value);
|
|
}
|
|
|
|
static u32 mdla_biu_read(u32 id, u32 offset)
|
|
{
|
|
if (unlikely(core_id_is_invalid(id)))
|
|
return 0;
|
|
|
|
return ioread32(mdla_reg_control[id].apu_mdla_biu_top + offset);
|
|
}
|
|
|
|
static void mdla_biu_write(u32 id, u32 offset, u32 value)
|
|
{
|
|
if (unlikely(core_id_is_invalid(id)))
|
|
return;
|
|
|
|
iowrite32(value, mdla_reg_control[id].apu_mdla_biu_top + offset);
|
|
}
|
|
|
|
static void mdla_biu_set_b(u32 id, u32 offset, u32 value)
|
|
{
|
|
if (unlikely(core_id_is_invalid(id)))
|
|
return;
|
|
|
|
reg_set(mdla_reg_control[id].apu_mdla_biu_top, offset, value);
|
|
}
|
|
|
|
static void mdla_biu_clr_b(u32 id, u32 offset, u32 value)
|
|
{
|
|
if (unlikely(core_id_is_invalid(id)))
|
|
return;
|
|
|
|
reg_clr(mdla_reg_control[id].apu_mdla_biu_top, offset, value);
|
|
}
|
|
|
|
static u32 mdla_apu_conn_read(u32 offset)
|
|
{
|
|
return ioread32(apu_conn_top + offset);
|
|
}
|
|
|
|
static void mdla_apu_conn_write(u32 offset, u32 value)
|
|
{
|
|
iowrite32(value, apu_conn_top + offset);
|
|
}
|
|
|
|
static void mdla_apu_conn_set_b(u32 offset, u32 value)
|
|
{
|
|
reg_set(apu_conn_top, offset, value);
|
|
}
|
|
|
|
static void mdla_apu_conn_clr_b(u32 offset, u32 value)
|
|
{
|
|
reg_clr(apu_conn_top, offset, value);
|
|
}
|
|
|
|
static u32 mdla_infracfg_ao_read(u32 offset)
|
|
{
|
|
return ioread32(infracfg_ao_top + offset);
|
|
}
|
|
|
|
static void mdla_infracfg_ao_write(u32 offset, u32 value)
|
|
{
|
|
iowrite32(value, infracfg_ao_top + offset);
|
|
}
|
|
|
|
static void mdla_infracfg_ao_set_b(u32 offset, u32 value)
|
|
{
|
|
reg_set(infracfg_ao_top, offset, value);
|
|
}
|
|
|
|
static void mdla_infracfg_ao_clr_b(u32 offset, u32 value)
|
|
{
|
|
reg_clr(infracfg_ao_top, offset, value);
|
|
}
|
|
|
|
void mdla_util_io_set_addr(struct mdla_reg_ctl *reg_ctl)
|
|
{
|
|
if (reg_ctl == NULL)
|
|
return;
|
|
|
|
mdla_reg_control = reg_ctl;
|
|
|
|
io_ops.cfg.read = mdla_cfg_read;
|
|
io_ops.cfg.write = mdla_cfg_write;
|
|
io_ops.cfg.set_b = mdla_cfg_set_b;
|
|
io_ops.cfg.clr_b = mdla_cfg_clr_b;
|
|
io_ops.cmde.read = mdla_reg_read;
|
|
io_ops.cmde.write = mdla_reg_write;
|
|
io_ops.cmde.set_b = mdla_reg_set_b;
|
|
io_ops.cmde.clr_b = mdla_biu_clr_b;
|
|
io_ops.biu.read = mdla_biu_read;
|
|
io_ops.biu.write = mdla_biu_write;
|
|
io_ops.biu.set_b = mdla_biu_set_b;
|
|
io_ops.biu.clr_b = mdla_reg_clr_b;
|
|
}
|
|
|
|
void mdla_util_io_set_extra_addr(int type,
|
|
void *addr1, void *addr2, void *addr3)
|
|
{
|
|
switch (type) {
|
|
case EXTRA_ADDR_V1P0:
|
|
apu_conn_top = addr1;
|
|
infracfg_ao_top = addr2;
|
|
break;
|
|
case EXTRA_ADDR_V1PX:
|
|
apu_conn_top = addr1;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
if (apu_conn_top) {
|
|
io_ops.apu_conn.read = mdla_apu_conn_read;
|
|
io_ops.apu_conn.write = mdla_apu_conn_write;
|
|
io_ops.apu_conn.set_b = mdla_apu_conn_set_b;
|
|
io_ops.apu_conn.clr_b = mdla_apu_conn_clr_b;
|
|
}
|
|
|
|
if (infracfg_ao_top) {
|
|
io_ops.infra_cfg.read = mdla_infracfg_ao_read;
|
|
io_ops.infra_cfg.write = mdla_infracfg_ao_write;
|
|
io_ops.infra_cfg.set_b = mdla_infracfg_ao_set_b;
|
|
io_ops.infra_cfg.clr_b = mdla_infracfg_ao_clr_b;
|
|
}
|
|
}
|