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219 lines
6.1 KiB
C
219 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MDLA_IOCTL__
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#define __MDLA_IOCTL__
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#include <stdbool.h>
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#ifndef __KERNEL__
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#include <stdint.h>
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#endif
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/* Memory type for mdla_buf_alloc */
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enum mem_type {
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MEM_DRAM,
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MEM_IOMMU,
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MEM_GSM
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};
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enum MDLA_PMU_INTERFACE {
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MDLA_PMU_IF_WDEC0 = 0xe,
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MDLA_PMU_IF_WDEC1 = 0xf,
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MDLA_PMU_IF_CBLD0 = 0x10,
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MDLA_PMU_IF_CBLD1 = 0x11,
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MDLA_PMU_IF_SBLD0 = 0x12,
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MDLA_PMU_IF_SBLD1 = 0x13,
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MDLA_PMU_IF_STE0 = 0x14,
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MDLA_PMU_IF_STE1 = 0x15,
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MDLA_PMU_IF_CMDE = 0x16,
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MDLA_PMU_IF_DDE = 0x17,
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MDLA_PMU_IF_CONV = 0x18,
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MDLA_PMU_IF_RQU = 0x19,
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MDLA_PMU_IF_POOLING = 0x1a,
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MDLA_PMU_IF_EWE = 0x1b,
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MDLA_PMU_IF_CFLD = 0x1c
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};
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enum MDLA_PMU_DDE_EVENT {
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MDLA_PMU_DDE_WORK_CYC = 0x0,
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MDLA_PMU_DDE_TILE_DONE_CNT,
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MDLA_PMU_DDE_EFF_WORK_CYC,
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MDLA_PMU_DDE_BLOCK_CNT,
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MDLA_PMU_DDE_READ_CB_WT_CNT,
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MDLA_PMU_DDE_READ_CB_ACT_CNT,
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MDLA_PMU_DDE_WAIT_CB_TOKEN_CNT,
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MDLA_PMU_DDE_WAIT_CONV_RDY_CNT,
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MDLA_PMU_DDE_WAIT_CB_FCWT_CNT,
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};
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enum MDLA_PMU_MODE {
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MDLA_PMU_ACC_MODE = 0x0,
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MDLA_PMU_INTERVAL_MODE = 0x1,
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};
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#define MDLA_IOC_MAGIC (0x3d1a632fULL)
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struct ioctl_malloc {
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uint32_t size; /* [in] allocate size */
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uint32_t mva; /* [out] modified virtual address */
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void *pa; /* [out] physical address */
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void *kva; /* [out] kernel virtual address */
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uint8_t type; /* [in] allocate memory type */
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void *data; /* [out] userspace virtual address */
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};
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struct ioctl_run_cmd {
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struct {
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uint32_t size;
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uint32_t mva;
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void *pa;
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void *kva;
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uint32_t id;
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uint8_t type;
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void *data;
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int32_t ion_share_fd;
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int32_t ion_handle; /* user space handle */
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uint64_t ion_khandle; /* kernel space handle */
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} buf;
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uint32_t offset; /* [in] command byte offset in buf */
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uint32_t count; /* [in] # of commands */
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uint32_t id; /* [out] command id */
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uint8_t priority; /* [in] dvfs priority */
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uint8_t boost_value; /* [in] dvfs boost value */
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};
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enum MDLA_CMD_RESULT {
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MDLA_CMD_SUCCESS = 0,
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MDLA_CMD_TIMEOUT = 1,
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};
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#define MDLA_IOC_SET_ARRAY_CNT(n) \
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((MDLA_IOC_MAGIC << 32) | ((n) & 0xFFFFFFFF))
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#define MDLA_IOC_GET_ARRAY_CNT(n) \
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(((n >> 32) == MDLA_IOC_MAGIC) ? ((n) & 0xFFFFFFFF) : 0)
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#define MDLA_IOC_SET_ARRAY_PTR(a) \
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((unsigned long)(a))
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#define MDLA_IOC_GET_ARRAY_PTR(a) \
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((void *)((unsigned long)(a)))
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#define MDLA_WAIT_CMD_ARRAY_SIZE 6
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struct ioctl_wait_cmd {
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uint32_t id; /* [in] command id */
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int32_t result; /* [out] success(0), timeout(1) */
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uint64_t queue_time; /* [out] time queued in driver (ns) */
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uint64_t busy_time; /* [out] mdla execution time (ns) */
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uint32_t bandwidth; /* [out] mdla bandwidth */
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};
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struct ioctl_run_cmd_sync {
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struct ioctl_run_cmd req;
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struct ioctl_wait_cmd res;
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uint32_t mdla_id;
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};
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struct ioctl_perf {
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uint32_t handle;
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uint32_t interface;
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uint32_t event;
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uint32_t counter;
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uint32_t start;
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uint32_t end;
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uint32_t mode;
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uint32_t mdlaid;
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};
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struct ioctl_ion {
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int32_t fd; /* [in] user handle, eq. ion_user_handle_t */
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uint64_t mva; /* [in] phyiscal address */
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uint64_t kva; /* [in(unmap)/out(map)] kernel virtual address */
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uint64_t khandle; /* [in(unmap)/out(map)] kernel handle */
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size_t len; /* [in] memory size */
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};
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enum MDLA_CONFIG {
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MDLA_CFG_NONE = 0,
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MDLA_CFG_TIMEOUT_GET = 1,
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MDLA_CFG_TIMEOUT_SET = 2,
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MDLA_CFG_FIFO_SZ_GET = 3,
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MDLA_CFG_FIFO_SZ_SET = 4,
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MDLA_CFG_GSM_INFO = 5,
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};
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struct ioctl_config {
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uint32_t op;
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uint32_t arg_count;
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uint64_t arg[8];
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};
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struct mdla_power {
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uint8_t boost_value;
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/* align with core index defined in user space header file */
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uint32_t core_id;
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};
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enum MDLA_OPP_PRIORIYY {
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MDLA_OPP_DEBUG = 0,
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MDLA_OPP_THERMAL = 1,
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MDLA_OPP_POWER_HAL = 2,
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MDLA_OPP_EARA_QOS = 3,
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MDLA_OPP_NORMAL = 4,
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MDLA_OPP_PRIORIYY_NUM
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};
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struct mdla_lock_power {
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uint32_t core;
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uint8_t max_boost_value;
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uint8_t min_boost_value;
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bool lock;
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enum MDLA_OPP_PRIORIYY priority;
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};
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#define IOC_MDLA ('\x1d')
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#define IOCTL_MALLOC _IOWR(IOC_MDLA, 0, struct ioctl_malloc)
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#define IOCTL_FREE _IOWR(IOC_MDLA, 1, struct ioctl_malloc)
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#define IOCTL_RUN_CMD_SYNC _IOWR(IOC_MDLA, 2, struct ioctl_run_cmd)
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#define IOCTL_RUN_CMD_ASYNC _IOWR(IOC_MDLA, 3, struct ioctl_run_cmd_sync)
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#define IOCTL_WAIT_CMD _IOWR(IOC_MDLA, 4, struct ioctl_wait_cmd)
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#define IOCTL_PERF_SET_EVENT _IOWR(IOC_MDLA, 5, struct ioctl_perf)
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#define IOCTL_PERF_GET_EVENT _IOWR(IOC_MDLA, 6, struct ioctl_perf)
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#define IOCTL_PERF_GET_CNT _IOWR(IOC_MDLA, 7, struct ioctl_perf)
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#define IOCTL_PERF_UNSET_EVENT _IOWR(IOC_MDLA, 8, struct ioctl_perf)
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#define IOCTL_PERF_GET_START _IOWR(IOC_MDLA, 9, struct ioctl_perf)
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#define IOCTL_PERF_GET_END _IOWR(IOC_MDLA, 10, struct ioctl_perf)
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#define IOCTL_PERF_GET_CYCLE _IOWR(IOC_MDLA, 11, struct ioctl_perf)
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#define IOCTL_PERF_RESET_CNT _IOWR(IOC_MDLA, 12, struct ioctl_perf)
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#define IOCTL_PERF_RESET_CYCLE _IOWR(IOC_MDLA, 13, struct ioctl_perf)
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#define IOCTL_PERF_SET_MODE _IOWR(IOC_MDLA, 14, struct ioctl_perf)
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#define IOCTL_ION_KMAP _IOWR(IOC_MDLA, 15, struct ioctl_ion)
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#define IOCTL_ION_KUNMAP _IOWR(IOC_MDLA, 16, struct ioctl_ion)
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/* 17 ~ 63: reserved for DVFS */
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#define IOCTL_SET_POWER _IOW(IOC_MDLA, 17, struct mdla_power)
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#define IOCTL_EARA_LOCK_POWER _IOW(IOC_MDLA, 18, struct mdla_lock_power)
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#define IOCTL_POWER_HAL_LOCK_POWER _IOW(IOC_MDLA, 19, struct mdla_lock_power)
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#define IOCTL_EARA_UNLOCK_POWER _IOW(IOC_MDLA, 20, struct mdla_lock_power)
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#define IOCTL_POWER_HAL_UNLOCK_POWER _IOW(IOC_MDLA, 21, struct mdla_lock_power)
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#define MDLA_DVFS_IOCTL_START IOCTL_SET_POWER
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#define MDLA_DVFS_IOCTL_END IOCTL_POWER_HAL_UNLOCK_POWER
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#define IOCTL_CONFIG _IOWR(IOC_MDLA, 64, struct ioctl_config)
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const struct file_operations *mdla_ioctl_get_fops(void);
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void mdla_ioctl_register_perf_handle(int (*pmu_ioctl)(struct file *filp,
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unsigned int command,
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unsigned long arg,
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bool need_pwr_on));
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void mdla_ioctl_unregister_perf_handle(void);
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#endif /* __MDLA_IOCTL__ */
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