mirror of
https://github.com/physwizz/a155-U-u1.git
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95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/mt6685-audclk.h>
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/* PMIC EFUSE registers definition */
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#define MT6685_DCXO_EXTBUF5_CW0 0x79e
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/* offset mask of OTP_CON0 */
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#define XO_BBCK5_MODE_SFT 0
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#define XO_BBCK5_MODE_MASK 0x3
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#define XO_BBCK5_MODE_MSK_SFT (0x3 << 0)
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#define XO_BBCK5_EN_M_SFT 2
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#define XO_BBCK5_EN_M_MASK 0x1
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#define XO_BBCK5_EN_M_MSK_SFT (0x1 << 2)
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struct clk_chip_data {
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unsigned int reg_num;
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unsigned int base;
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};
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struct mt6685_clk {
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struct device *dev;
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struct regmap *regmap;
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struct mutex lock;
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};
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struct mt6685_clk *clk;
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void mt6685_set_dcxo(bool enable)
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{
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if (!clk || !clk->regmap)
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return;
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if (enable) {
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regmap_update_bits(clk->regmap, MT6685_DCXO_EXTBUF5_CW0,
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XO_BBCK5_EN_M_MSK_SFT, 0x1 << XO_BBCK5_EN_M_SFT);
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usleep_range(400, 420);
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} else {
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regmap_update_bits(clk->regmap, MT6685_DCXO_EXTBUF5_CW0,
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XO_BBCK5_EN_M_MSK_SFT, 0x0 << XO_BBCK5_EN_M_SFT);
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}
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}
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EXPORT_SYMBOL(mt6685_set_dcxo);
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static int mt6685_audclk_probe(struct platform_device *pdev)
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{
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clk = devm_kzalloc(&pdev->dev, sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return -ENOMEM;
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clk->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!clk->regmap) {
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dev_info(&pdev->dev, "failed to get efuse regmap\n");
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return -ENODEV;
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}
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mutex_init(&clk->lock);
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clk->dev = &pdev->dev;
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dev_info(&pdev->dev, "%s done\n", __func__);
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return 0;
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}
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static const struct clk_chip_data mt6685_audclk_data = {
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.reg_num = 128,
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.base = MT6685_DCXO_EXTBUF5_CW0,
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};
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static const struct of_device_id mt6338_of_match[] = {
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{.compatible = "mediatek,mt6338_snd",},
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{},
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};
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static const struct of_device_id mt6685_audclk_of_match[] = {
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{.compatible = "mediatek,mt6685-audclk",},
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{/* sentinel */},
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};
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static struct platform_driver mt6685_audclk_driver = {
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.probe = mt6685_audclk_probe,
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.driver = {
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.name = "mt6685-audclk",
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.of_match_table = mt6685_audclk_of_match,
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},
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};
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module_platform_driver(mt6685_audclk_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Ting-Fang Hou <ting-fang.hou@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek PMIC AUDCLK Driver for MT6685 PMIC");
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