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523 lines
16 KiB
C
523 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/mt6323/core.h>
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#include <linux/mfd/mt6358/core.h>
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#include <linux/mfd/mt6359p/core.h>
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#include <linux/mfd/mt6366/core.h>
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#include <linux/mfd/mt6397/core.h>
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#include <linux/mfd/mt6323/registers.h>
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#include <linux/mfd/mt6358/registers.h>
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#include <linux/mfd/mt6359p/registers.h>
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#include <linux/mfd/mt6397/registers.h>
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#define MT6323_RTC_BASE 0x8000
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#define MT6323_RTC_SIZE 0x40
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#define MT6358_RTC_BASE 0x0588
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#define MT6358_RTC_SIZE 0x3c
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#define MT6397_RTC_BASE 0xe000
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#define MT6397_RTC_SIZE 0x3e
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#define MT6323_PWRC_BASE 0x8000
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#define MT6323_PWRC_SIZE 0x40
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static const struct resource mt6323_rtc_resources[] = {
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DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
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};
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static const struct resource mt6358_rtc_resources[] = {
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DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
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DEFINE_RES_IRQ(MT6358_IRQ_RTC),
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};
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static const struct resource mt6359p_rtc_resources[] = {
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DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
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DEFINE_RES_IRQ(MT6359P_IRQ_RTC),
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};
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static const struct resource mt6397_rtc_resources[] = {
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DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
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DEFINE_RES_IRQ(MT6397_IRQ_RTC),
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};
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static const struct resource mt6323_keys_resources[] = {
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
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};
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static const struct resource mt6359p_keys_resources[] = {
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DEFINE_RES_IRQ(MT6359P_IRQ_PWRKEY),
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DEFINE_RES_IRQ(MT6359P_IRQ_HOMEKEY),
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DEFINE_RES_IRQ(MT6359P_IRQ_PWRKEY_R),
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DEFINE_RES_IRQ(MT6359P_IRQ_HOMEKEY_R),
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};
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static const struct resource mt6397_keys_resources[] = {
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DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
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DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
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};
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static const struct resource mt6366_keys_resources[] = {
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DEFINE_RES_IRQ(MT6366_IRQ_PWRKEY),
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DEFINE_RES_IRQ(MT6366_IRQ_HOMEKEY),
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DEFINE_RES_IRQ(MT6366_IRQ_PWRKEY_R),
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DEFINE_RES_IRQ(MT6366_IRQ_HOMEKEY_R),
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};
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static const struct resource mt6359p_auxadc_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_AUXADC_IMP, "imp"),
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};
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static const struct resource mt6359p_battery_oc_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_CUR_H, "fg_cur_h"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_CUR_L, "fg_cur_l"),
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};
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static const struct resource mt6366_battery_oc_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_CUR_H, "fg_cur_h"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_CUR_L, "fg_cur_l"),
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};
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static const struct resource mt6359p_lbat_service_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT_H, "bat_h"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT_L, "bat_l"),
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};
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static const struct resource mt6366_lbat_service_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT_H, "bat_h"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT_L, "bat_l"),
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};
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static const struct resource mt6323_pwrc_resources[] = {
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DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
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};
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static const struct resource mt6366_gauge_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_BAT1_H, "COULOMB_H"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_BAT1_L, "COULOMB_L"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT2_H, "VBAT_H"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT2_L, "VBAT_L"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_NAG_C_DLTV, "NAFG"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BATON_BAT_OUT, "BAT_OUT"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_ZCV, "ZCV"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_N_CHARGE_L, "FG_N_CHARGE_L"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_IAVG_H, "FG_IAVG_H"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_FG_IAVG_L, "FG_IAVG_L"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT_TEMP_H, "BAT_TMP_H"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_BAT_TEMP_L, "BAT_TMP_L"),
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};
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static const struct resource mt6359p_gauge_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_BAT_H, "COULOMB_H"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_BAT_L, "COULOMB_L"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT2_H, "VBAT_H"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT2_L, "VBAT_L"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_NAG_C_DLTV, "NAFG"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BATON_BAT_OU, "BAT_OUT"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_ZCV, "ZCV"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_N_CHARGE_L, "FG_N_CHARGE_L"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_IAVG_H, "FG_IAVG_H"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_FG_IAVG_L, "FG_IAVG_L"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT_TEMP_H, "BAT_TMP_H"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_BAT_TEMP_L, "BAT_TMP_L"),
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};
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static const struct resource mt6359p_accdet_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_ACCDET, "ACCDET_IRQ"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_ACCDET_EINT0, "ACCDET_EINT0"),
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DEFINE_RES_IRQ_NAMED(MT6359P_IRQ_ACCDET_EINT1, "ACCDET_EINT1"),
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};
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static const struct resource mt6366_accdet_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_ACCDET, "ACCDET_IRQ"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_ACCDET_EINT0, "ACCDET_EINT0"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_ACCDET_EINT1, "ACCDET_EINT1"),
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};
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static const struct resource mt6366_regulators_resources[] = {
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VPROC11_OC, "VPROC11"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VPROC12_OC, "VPROC12"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VCORE_OC, "VCORE"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VGPU_OC, "VGPU"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VMODEM_OC, "VMODEM"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VDRAM1_OC, "VDRAM1"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VS1_OC, "VS1"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VS2_OC, "VS2"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VPA_OC, "VPA"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VCORE_PREOC, "VCORE_PR"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VFE28_OC, "VFE28"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VXO22_OC, "VXO22"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VRF18_OC, "VRF18"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VRF12_OC, "VRF12"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VEFUSE_OC, "VEFUSE"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VCN33_OC, "VCN33"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VCN28_OC, "VCN28"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VCN18_OC, "VCN18"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VM18_OC, "VM18"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VMDDR_OC, "VMDDR"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSRAM_CORE_OC, "VSRAM_CORE"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VA12_OC, "VA12"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VAUX18_OC, "VAUX18"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VAUD28_OC, "VAUD28"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VIO28_OC, "VIO28"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VIO18_OC, "VIO18"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSRAM_PROC11_OC, "VSRAM_PROC11"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSRAM_PROC12_OC, "VSRAM_PROC12"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSRAM_OTHERS_OC, "VSRAM_OTHERS"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSRAM_GPU_OC, "VSRAM_GPU"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VDRAM2_OC, "VDRAM2"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VMC_OC, "VMC"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VMCH_OC, "VMCH"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VEMC_OC, "VEMC"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSIM1_OC, "VSIM1"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VSIM2_OC, "VSIM2"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VIBR_OC, "VIBR"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VUSB_OC, "VUSB"),
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DEFINE_RES_IRQ_NAMED(MT6366_IRQ_VBIF28_OC, "VBIF28"),
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};
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static const struct mfd_cell mt6323_devs[] = {
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{
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.name = "mt6323-rtc",
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.num_resources = ARRAY_SIZE(mt6323_rtc_resources),
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.resources = mt6323_rtc_resources,
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.of_compatible = "mediatek,mt6323-rtc",
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}, {
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.name = "mt6323-regulator",
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.of_compatible = "mediatek,mt6323-regulator"
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}, {
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.name = "mt6323-led",
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.of_compatible = "mediatek,mt6323-led"
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6323_keys_resources),
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.resources = mt6323_keys_resources,
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.of_compatible = "mediatek,mt6323-keys"
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}, {
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.name = "mt6323-pwrc",
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.num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
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.resources = mt6323_pwrc_resources,
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.of_compatible = "mediatek,mt6323-pwrc"
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},
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};
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static const struct mfd_cell mt6358_devs[] = {
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{
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.name = "mt6358-regulator",
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.of_compatible = "mediatek,mt6358-regulator"
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}, {
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.name = "mt6358-rtc",
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.num_resources = ARRAY_SIZE(mt6358_rtc_resources),
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.resources = mt6358_rtc_resources,
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.of_compatible = "mediatek,mt6358-rtc",
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}, {
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.name = "mt6358-sound",
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.of_compatible = "mediatek,mt6358-sound"
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}, {
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.name = "mt6358-gauge",
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.num_resources = ARRAY_SIZE(mt6366_gauge_resources),
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.resources = mt6366_gauge_resources,
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.of_compatible = "mediatek,mt6358-gauge",
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},
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};
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static const struct mfd_cell mt6359p_devs[] = {
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{
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.name = "mt-pmic",
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.of_compatible = "mediatek,mt63xx-debug",
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}, {
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.name = "mt6359p-accdet",
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.of_compatible = "mediatek,mt6359p-accdet",
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.num_resources = ARRAY_SIZE(mt6359p_accdet_resources),
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.resources = mt6359p_accdet_resources,
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}, {
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.name = "mt635x-auxadc",
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.of_compatible = "mediatek,mt6359p-auxadc",
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.num_resources = ARRAY_SIZE(mt6359p_auxadc_resources),
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.resources = mt6359p_auxadc_resources,
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}, {
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.name = "mt6359p-efuse",
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.of_compatible = "mediatek,mt6359p-efuse",
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}, {
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.name = "mt6359p-regulator",
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.of_compatible = "mediatek,mt6359p-regulator"
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}, {
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.name = "mt6359p-rtc",
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.num_resources = ARRAY_SIZE(mt6359p_rtc_resources),
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.resources = mt6359p_rtc_resources,
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.of_compatible = "mediatek,mt6359p-rtc",
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}, {
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.name = "mt6359p-gauge",
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.num_resources = ARRAY_SIZE(mt6359p_gauge_resources),
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.resources = mt6359p_gauge_resources,
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.of_compatible = "mediatek,mt6359p-gauge",
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}, {
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.name = "mtk-battery-oc-throttling",
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.of_compatible = "mediatek,mt6359p-battery_oc_throttling",
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.num_resources = ARRAY_SIZE(mt6359p_battery_oc_resources),
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.resources = mt6359p_battery_oc_resources,
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}, {
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.name = "mtk-dynamic-loading-throttling",
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.of_compatible = "mediatek,mt6359p-dynamic_loading_throttling",
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}, {
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.name = "mtk-lbat_service",
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.of_compatible = "mediatek,mt6359p-lbat_service",
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.num_resources = ARRAY_SIZE(mt6359p_lbat_service_resources),
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.resources = mt6359p_lbat_service_resources,
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6359p_keys_resources),
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.resources = mt6359p_keys_resources,
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.of_compatible = "mediatek,mt6359p-keys"
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}, {
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.name = "mt6359-sound",
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.of_compatible = "mediatek,mt6359p-sound"
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}, {
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.name = "mtk-clock-buffer",
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.of_compatible = "mediatek,clock_buffer",
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}
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};
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static const struct mfd_cell mt6366_devs[] = {
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{
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.name = "mt-pmic",
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.of_compatible = "mediatek,mt63xx-debug",
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}, {
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.name = "mediatek,pmic-accdet",
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.of_compatible = "mediatek,mt6358-accdet",
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.num_resources = ARRAY_SIZE(mt6366_accdet_resources),
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.resources = mt6366_accdet_resources,
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}, {
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.name = "mt635x-auxadc",
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.of_compatible = "mediatek,mt6358-auxadc",
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}, {
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.name = "mt6358-efuse",
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.of_compatible = "mediatek,mt6358-efuse",
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}, {
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.name = "mt6358-regulator",
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.of_compatible = "mediatek,mt6358-regulator",
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.num_resources = ARRAY_SIZE(mt6366_regulators_resources),
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.resources = mt6366_regulators_resources,
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}, {
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.name = "mtk-battery-oc-throttling",
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.of_compatible = "mediatek,mt6358-battery_oc_throttling",
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.num_resources = ARRAY_SIZE(mt6366_battery_oc_resources),
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.resources = mt6366_battery_oc_resources,
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}, {
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.name = "mtk-dynamic-loading-throttling",
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.of_compatible = "mediatek,mt6358-dynamic_loading_throttling",
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}, {
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.name = "mtk-lbat_service",
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.of_compatible = "mediatek,mt6358-lbat_service",
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.num_resources = ARRAY_SIZE(mt6366_lbat_service_resources),
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.resources = mt6366_lbat_service_resources,
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}, {
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.name = "mt63xx-oc-debug",
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.of_compatible = "mediatek,mt63xx-oc-debug",
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}, {
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.name = "mt6358-sound",
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.of_compatible = "mediatek,mt6366-sound"
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6366_keys_resources),
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.resources = mt6366_keys_resources,
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.of_compatible = "mediatek,mt6366-keys"
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}, {
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.name = "mt6358-gauge",
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.num_resources = ARRAY_SIZE(mt6366_gauge_resources),
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.resources = mt6366_gauge_resources,
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.of_compatible = "mediatek,mt6358-gauge",
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}, {
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.name = "mtk-clock-buffer",
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.of_compatible = "mediatek,clock_buffer",
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}, {
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.name = "mt6358-rtc",
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.num_resources = ARRAY_SIZE(mt6358_rtc_resources),
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.resources = mt6358_rtc_resources,
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.of_compatible = "mediatek,mt6358-rtc",
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},
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};
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static const struct mfd_cell mt6397_devs[] = {
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{
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.name = "mt6397-rtc",
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.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
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.resources = mt6397_rtc_resources,
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.of_compatible = "mediatek,mt6397-rtc",
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}, {
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.name = "mt6397-regulator",
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.of_compatible = "mediatek,mt6397-regulator",
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}, {
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.name = "mt6397-codec",
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.of_compatible = "mediatek,mt6397-codec",
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}, {
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.name = "mt6397-clk",
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.of_compatible = "mediatek,mt6397-clk",
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}, {
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.name = "mt6397-pinctrl",
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.of_compatible = "mediatek,mt6397-pinctrl",
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6397_keys_resources),
|
|
.resources = mt6397_keys_resources,
|
|
.of_compatible = "mediatek,mt6397-keys"
|
|
}
|
|
};
|
|
|
|
struct chip_data {
|
|
u32 cid_addr;
|
|
u32 cid_shift;
|
|
const struct mfd_cell *cells;
|
|
int cell_size;
|
|
int (*irq_init)(struct mt6397_chip *chip);
|
|
};
|
|
|
|
static const struct chip_data mt6323_core = {
|
|
.cid_addr = MT6323_CID,
|
|
.cid_shift = 0,
|
|
.cells = mt6323_devs,
|
|
.cell_size = ARRAY_SIZE(mt6323_devs),
|
|
.irq_init = mt6397_irq_init,
|
|
};
|
|
|
|
static const struct chip_data mt6358_core = {
|
|
.cid_addr = MT6358_SWCID,
|
|
.cid_shift = 8,
|
|
.cells = mt6358_devs,
|
|
.cell_size = ARRAY_SIZE(mt6358_devs),
|
|
.irq_init = mt6358_irq_init,
|
|
};
|
|
|
|
static const struct chip_data mt6359p_core = {
|
|
.cid_addr = MT6359P_SWCID,
|
|
.cid_shift = 8,
|
|
.cells = mt6359p_devs,
|
|
.cell_size = ARRAY_SIZE(mt6359p_devs),
|
|
.irq_init = mt6358_irq_init,
|
|
};
|
|
|
|
static const struct chip_data mt6366_core = {
|
|
.cid_addr = MT6358_SWCID,
|
|
.cid_shift = 8,
|
|
.cells = mt6366_devs,
|
|
.cell_size = ARRAY_SIZE(mt6366_devs),
|
|
.irq_init = mt6358_irq_init,
|
|
};
|
|
|
|
static const struct chip_data mt6397_core = {
|
|
.cid_addr = MT6397_CID,
|
|
.cid_shift = 0,
|
|
.cells = mt6397_devs,
|
|
.cell_size = ARRAY_SIZE(mt6397_devs),
|
|
.irq_init = mt6397_irq_init,
|
|
};
|
|
|
|
static int mt6397_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
unsigned int id = 0;
|
|
struct mt6397_chip *pmic;
|
|
const struct chip_data *pmic_core;
|
|
|
|
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
|
|
if (!pmic)
|
|
return -ENOMEM;
|
|
|
|
pmic->dev = &pdev->dev;
|
|
|
|
/*
|
|
* mt6397 MFD is child device of soc pmic wrapper.
|
|
* Regmap is set from its parent.
|
|
*/
|
|
pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
|
if (!pmic->regmap)
|
|
return -ENODEV;
|
|
|
|
pmic_core = of_device_get_match_data(&pdev->dev);
|
|
if (!pmic_core)
|
|
return -ENODEV;
|
|
|
|
ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
|
|
|
|
platform_set_drvdata(pdev, pmic);
|
|
|
|
pmic->irq = platform_get_irq(pdev, 0);
|
|
if (pmic->irq <= 0)
|
|
return pmic->irq;
|
|
|
|
ret = pmic_core->irq_init(pmic);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
|
|
pmic_core->cells, pmic_core->cell_size,
|
|
NULL, 0, pmic->irq_domain);
|
|
if (ret) {
|
|
irq_domain_remove(pmic->irq_domain);
|
|
dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id mt6397_of_match[] = {
|
|
{
|
|
.compatible = "mediatek,mt6323",
|
|
.data = &mt6323_core,
|
|
}, {
|
|
.compatible = "mediatek,mt6358",
|
|
.data = &mt6358_core,
|
|
}, {
|
|
.compatible = "mediatek,mt6359p",
|
|
.data = &mt6359p_core,
|
|
}, {
|
|
.compatible = "mediatek,mt6366",
|
|
.data = &mt6366_core,
|
|
}, {
|
|
.compatible = "mediatek,mt6397",
|
|
.data = &mt6397_core,
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mt6397_of_match);
|
|
|
|
static const struct platform_device_id mt6397_id[] = {
|
|
{ "mt6397", 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, mt6397_id);
|
|
|
|
static struct platform_driver mt6397_driver = {
|
|
.probe = mt6397_probe,
|
|
.driver = {
|
|
.name = "mt6397",
|
|
.of_match_table = of_match_ptr(mt6397_of_match),
|
|
},
|
|
.id_table = mt6397_id,
|
|
};
|
|
|
|
module_platform_driver(mt6397_driver);
|
|
|
|
MODULE_AUTHOR("Flora Fu, MediaTek");
|
|
MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
|
|
MODULE_LICENSE("GPL");
|