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https://github.com/physwizz/a155-U-u1.git
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237 lines
7.7 KiB
C
237 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Tiffany Lin <tiffany.lin@mediatek.com>
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*/
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#ifndef _MTK_VCODEC_PM_H_
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#define _MTK_VCODEC_PM_H_
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//#include "ion_drv.h"
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//#include "mach/mt_iommu.h"
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#define MTK_PLATFORM_STR "platform:mt6873" //TODO: remove when venc ready
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#define MTK_VDEC_RACING_INFO_OFFSET 0x100
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#define MTK_VDEC_RACING_INFO_SIZE 68
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#define MTK_VDEC_MAX_LARB_COUNT 2
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#define MTK_MAX_VDEC_CLK_COUNT 10
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#define MTK_MAX_VDEC_CLK_SOC_COUNT 3
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#define MTK_MAX_VDEC_CLK_CORE_COUNT 3
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#define MTK_MAX_VDEC_CLK_LAT_COUNT 3
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#define MTK_MAX_VDEC_CLK_MAIN_COUNT 4
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#define MTK_MAX_VDEC_CLK_PARENT_SET_COUNT 4
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// to distingush clock type, the clock name in dts should start with these prefix
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#define MTK_VDEC_CLK_LAT_PREFIX "LAT"
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#define MTK_VDEC_CLK_CORE_PREFIX "CORE"
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#define MTK_VDEC_CLK_SOC_PREFIX "SOC"
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#define MTK_VDEC_CLK_MAIN_PREFIX "MAIN"
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#define MTK_MAX_VENC_CLK_COUNT 2
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#define MTK_MAX_VENC_CLK_CORE_COUNT 2
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#define MTK_VENC_MAX_LARB_COUNT 2
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#define IS_SPECIFIC_CLK_TYPE(clk_name, prefix) \
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!strncmp(clk_name, prefix, strlen(prefix)) ? true : false
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struct mtk_vcodec_clk {
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unsigned int clk_id; // the array index of vdec_clks
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const char *clk_name;
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};
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struct mtk_vcodec_parent_clk {
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struct mtk_vcodec_clk parent;
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struct mtk_vcodec_clk child;
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};
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struct mtk_vdec_clks_data {
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struct mtk_vcodec_clk main_clks[MTK_MAX_VDEC_CLK_MAIN_COUNT];
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unsigned int main_clks_len;
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struct mtk_vcodec_clk soc_clks[MTK_MAX_VDEC_CLK_SOC_COUNT];
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unsigned int soc_clks_len;
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struct mtk_vcodec_clk lat_clks[MTK_MAX_VDEC_CLK_LAT_COUNT];
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unsigned int lat_clks_len;
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struct mtk_vcodec_clk core_clks[MTK_MAX_VDEC_CLK_CORE_COUNT];
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unsigned int core_clks_len;
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struct mtk_vcodec_parent_clk parent_clks[MTK_MAX_VDEC_CLK_PARENT_SET_COUNT];
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unsigned int parent_clks_len;
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};
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struct mtk_venc_clks_data {
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struct mtk_vcodec_clk core_clks[MTK_MAX_VENC_CLK_CORE_COUNT];
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unsigned int core_clks_len;
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};
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/**
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* struct mtk_vcodec_pm - Power management data structure
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*/
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struct mtk_vcodec_pm {
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struct clk *vdec_bus_clk_src;
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struct clk *vencpll;
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struct clk *vcodecpll;
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struct clk *univpll_d2;
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struct clk *clk_cci400_sel;
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struct clk *vdecpll;
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struct clk *vdec_sel;
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struct clk *vencpll_d2;
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struct clk *venc_sel;
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struct clk *univpll1_d2;
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struct clk *venc_lt_sel;
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struct clk *img_resz;
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struct device *larbvdecs[MTK_VDEC_MAX_LARB_COUNT];
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struct device *larbvencs[MTK_VENC_MAX_LARB_COUNT];
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struct device *larbvenclt;
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struct device *dev;
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struct device_node *chip_node;
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struct mtk_vcodec_dev *mtkdev;
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struct mtk_vdec_clks_data vdec_clks_data;
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struct clk *vdec_clks[MTK_MAX_VDEC_CLK_COUNT];
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struct mtk_venc_clks_data venc_clks_data;
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struct clk *venc_clks[MTK_MAX_VENC_CLK_COUNT];
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atomic_t dec_active_cnt;
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__u32 vdec_racing_info[MTK_VDEC_RACING_INFO_SIZE];
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struct mutex dec_racing_info_mutex;
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};
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enum mtk_dec_dump_addr_type {
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DUMP_VDEC_IN_BUF,
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DUMP_VDEC_OUT_BUF,
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DUMP_VDEC_REF_BUF,
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DUMP_VDEC_MV_BUF,
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DUMP_VDEC_UBE_BUF,
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};
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// The port name should same with dts
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#define MTK_VDEC_M4U_PORT_NAME_MC "M4U_PORT_VDEC_MC"
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#define MTK_VDEC_M4U_PORT_NAME_UFO "M4U_PORT_VDEC_UFO"
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#define MTK_VDEC_M4U_PORT_NAME_PP "M4U_PORT_VDEC_PP"
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#define MTK_VDEC_M4U_PORT_NAME_PRED_RD "M4U_PORT_VDEC_PRED_RD"
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#define MTK_VDEC_M4U_PORT_NAME_PRED_WR "M4U_PORT_VDEC_PRED_WR"
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#define MTK_VDEC_M4U_PORT_NAME_PPWRAP "M4U_PORT_VDEC_PPWRAP"
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#define MTK_VDEC_M4U_PORT_NAME_TILE "M4U_PORT_VDEC_TILE"
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#define MTK_VDEC_M4U_PORT_NAME_VLD "M4U_PORT_VDEC_VLD"
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#define MTK_VDEC_M4U_PORT_NAME_VLD2 "M4U_PORT_VDEC_VLD2"
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#define MTK_VDEC_M4U_PORT_NAME_AVC_MV "M4U_PORT_VDEC_AVC_MV"
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#define MTK_VDEC_M4U_PORT_NAME_RG_CTRL_DMA "M4U_PORT_VDEC_RG_CTRL_DMA"
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#define MTK_VDEC_M4U_PORT_NAME_UFO_ENC "M4U_PORT_VDEC_UFO_ENC"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_VLD "M4U_PORT_VDEC_LAT0_VLD"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_VLD2 "M4U_PORT_VDEC_LAT0_VLD2"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_AVC_MV "M4U_PORT_VDEC_LAT0_AVC_MV"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_PRED_RD "M4U_PORT_VDEC_LAT0_PRED_RD"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_TILE "M4U_PORT_VDEC_LAT0_TILE"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_WDMA "M4U_PORT_VDEC_LAT0_WDMA"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_RG_CTRL_DMA "M4U_PORT_VDEC_LAT0_RG_CTRL_DMA"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_MC "M4U_PORT_VDEC_LAT0_MC"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_UFO_ENC "M4U_PORT_VDEC_LAT0_UFO_ENC"
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#define MTK_VDEC_M4U_PORT_NAME_LAT0_UFO_ENC_C "M4U_PORT_VDEC_LAT0_UFO_ENC_C"
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#define MTK_VDEC_M4U_PORT_NAME_UP_1 "M4U_PORT_VIDEO_UP_1"
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#define MTK_VDEC_M4U_PORT_NAME_UP_2 "M4U_PORT_VIDEO_UP_2"
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#define MTK_VDEC_M4U_PORT_NAME_UP_3 "M4U_PORT_VIDEO_UP_3"
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#define MTK_VDEC_M4U_PORT_NAME_UP_4 "M4U_PORT_VIDEO_UP_4"
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enum mtk_dec_dtsi_m4u_port_idx {
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VDEC_M4U_PORT_MC,
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VDEC_M4U_PORT_UFO,
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VDEC_M4U_PORT_PP,
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VDEC_M4U_PORT_PRED_RD,
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VDEC_M4U_PORT_PRED_WR,
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VDEC_M4U_PORT_PPWRAP,
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VDEC_M4U_PORT_TILE,
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VDEC_M4U_PORT_VLD,
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VDEC_M4U_PORT_VLD2,
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VDEC_M4U_PORT_AVC_MV,
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VDEC_M4U_PORT_RG_CTRL_DMA,
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VDEC_M4U_PORT_UFO_ENC,
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VDEC_M4U_PORT_LAT0_VLD,
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VDEC_M4U_PORT_LAT0_VLD2,
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VDEC_M4U_PORT_LAT0_AVC_MV,
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VDEC_M4U_PORT_LAT0_PRED_RD,
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VDEC_M4U_PORT_LAT0_TILE,
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VDEC_M4U_PORT_LAT0_WDMA,
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VDEC_M4U_PORT_LAT0_RG_CTRL_DMA,
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VDEC_M4U_PORT_LAT0_MC,
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VDEC_M4U_PORT_LAT0_UFO,
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VDEC_M4U_PORT_LAT0_UFO_C,
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VDEC_M4U_PORT_UP_1,
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VDEC_M4U_PORT_UP_2,
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VDEC_M4U_PORT_UP_3,
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VDEC_M4U_PORT_UP_4,
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NUM_MAX_VDEC_M4U_PORT
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};
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static char *dec_port_name[NUM_MAX_VDEC_M4U_PORT+1] = {
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[VDEC_M4U_PORT_MC] = "MC",
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[VDEC_M4U_PORT_UFO] = "UFO",
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[VDEC_M4U_PORT_PP] = "PP",
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[VDEC_M4U_PORT_PRED_RD] = "PRED_RD",
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[VDEC_M4U_PORT_PRED_WR] = "PRED_WR",
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[VDEC_M4U_PORT_PPWRAP] = "PPWRAP",
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[VDEC_M4U_PORT_TILE] = "TILE",
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[VDEC_M4U_PORT_VLD] = "VLD",
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[VDEC_M4U_PORT_VLD2] = "VLD2",
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[VDEC_M4U_PORT_AVC_MV] = "MV",
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[VDEC_M4U_PORT_RG_CTRL_DMA] = "RG_CTRL_DMA",
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[VDEC_M4U_PORT_UFO_ENC] = "UFO_ENC",
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[VDEC_M4U_PORT_LAT0_VLD] = "LAT_VLD",
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[VDEC_M4U_PORT_LAT0_VLD2] = "LAT_VLD2",
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[VDEC_M4U_PORT_LAT0_AVC_MV] = "LAT_MV",
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[VDEC_M4U_PORT_LAT0_PRED_RD] = "LAT_PRED_RD",
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[VDEC_M4U_PORT_LAT0_TILE] = "LAT_TILE",
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[VDEC_M4U_PORT_LAT0_WDMA] = "LAT_WDMA",
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[VDEC_M4U_PORT_LAT0_RG_CTRL_DMA] = "LAT_RG_CTRL_DMA",
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[VDEC_M4U_PORT_LAT0_MC] = "LAT_MC",
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[VDEC_M4U_PORT_LAT0_UFO] = "LAT_UFO",
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[VDEC_M4U_PORT_LAT0_UFO_C] = "LAT_UFO_C",
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[VDEC_M4U_PORT_UP_1] = "UP_1",
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[VDEC_M4U_PORT_UP_2] = "UP_2",
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[VDEC_M4U_PORT_UP_3] = "UP_3",
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[VDEC_M4U_PORT_UP_4] = "UP_4",
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[NUM_MAX_VDEC_M4U_PORT] = "UNKNOWN",
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};
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// The reg name should same with dts
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#define MTK_VDEC_REG_NAME_VDEC_BASE "VDEC_BASE"
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#define MTK_VDEC_REG_NAME_VDEC_SYS "VDEC_SYS"
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#define MTK_VDEC_REG_NAME_VDEC_VLD "VDEC_VLD"
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#define MTK_VDEC_REG_NAME_VDEC_MC "VDEC_MC"
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#define MTK_VDEC_REG_NAME_VDEC_MV "VDEC_MV"
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#define MTK_VDEC_REG_NAME_VDEC_MISC "VDEC_MISC"
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#define MTK_VDEC_REG_NAME_VDEC_LAT_MISC "VDEC_LAT_MISC"
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#define MTK_VDEC_REG_NAME_VDEC_LAT_VLD "VDEC_LAT_VLD"
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#define MTK_VDEC_REG_NAME_VDEC_SOC_GCON "VDEC_SOC_GCON"
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#define MTK_VDEC_REG_NAME_VDEC_RACING_CTRL "VDEC_RACING_CTRL"
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#define MTK_VDEC_REG_NAME_VENC_SYS "VENC_SYS"
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#define MTK_VDEC_REG_NAME_VENC_C1_SYS "VENC_C1_SYS"
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#define MTK_VDEC_REG_NAME_VENC_GCON "VENC_GCON"
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enum mtk_dec_dtsi_reg_idx {
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VDEC_BASE,
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VDEC_SYS,
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VDEC_VLD,
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VDEC_MC,
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VDEC_MV,
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VDEC_MISC,
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VDEC_LAT_MISC,
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VDEC_LAT_VLD,
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VDEC_SOC_GCON,
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VDEC_RACING_CTRL,
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NUM_MAX_VDEC_REG_BASE,
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};
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enum mtk_enc_dtsi_reg_idx {
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VENC_SYS,
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VENC_C1_SYS,
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VENC_GCON,
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NUM_MAX_VENC_REG_BASE
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};
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#endif /* _MTK_VCODEC_PM_H_ */
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