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a155-U-u1/kernel-5.10/drivers/interconnect/mediatek/mmqos-mt6853.c
physwizz 99537be4e2 first
2024-03-11 06:53:12 +11:00

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Ming-Fan Chen <ming-fan.chen@mediatek.com>
*/
#include <dt-bindings/interconnect/mtk,mmqos.h>
#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
#include <dt-bindings/memory/mt6853-larb-port.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include "mmqos-mtk.h"
static const struct mtk_node_desc node_descs_mt6853[] = {
DEFINE_MNODE(common0,
SLAVE_COMMON(0), 0, false, 0x0, MMQOS_NO_LINK),
DEFINE_MNODE(common0_port0,
MASTER_COMMON_PORT(0, 0), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port1,
MASTER_COMMON_PORT(0, 1), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port2,
MASTER_COMMON_PORT(0, 2), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port3,
MASTER_COMMON_PORT(0, 3), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port4,
MASTER_COMMON_PORT(0, 4), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port5,
MASTER_COMMON_PORT(0, 5), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port6,
MASTER_COMMON_PORT(0, 6), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port7,
MASTER_COMMON_PORT(0, 7), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(common0_port8,
MASTER_COMMON_PORT(0, 8), 0, false, 0x0, SLAVE_COMMON(0)),
DEFINE_MNODE(larb0, SLAVE_LARB(0), 0, false, 0x0, MASTER_COMMON_PORT(0, 0)),
DEFINE_MNODE(larb1, SLAVE_LARB(1), 0, false, 0x0, MASTER_COMMON_PORT(0, 1)),
DEFINE_MNODE(larb2, SLAVE_LARB(2), 0, false, 0x0, MASTER_COMMON_PORT(0, 4)),
DEFINE_MNODE(larb4, SLAVE_LARB(4), 0, false, 0x0, MASTER_COMMON_PORT(0, 2)),
DEFINE_MNODE(larb7, SLAVE_LARB(7), 0, false, 0x0, MASTER_COMMON_PORT(0, 3)),
DEFINE_MNODE(larb9, SLAVE_LARB(9), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
DEFINE_MNODE(larb11, SLAVE_LARB(11), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
DEFINE_MNODE(larb13, SLAVE_LARB(13), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
DEFINE_MNODE(larb14, SLAVE_LARB(14), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
DEFINE_MNODE(larb16, SLAVE_LARB(16), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
DEFINE_MNODE(larb17, SLAVE_LARB(17), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
DEFINE_MNODE(larb19, SLAVE_LARB(19), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
DEFINE_MNODE(larb20, SLAVE_LARB(20), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
DEFINE_MNODE(larb21, SLAVE_LARB(21), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
DEFINE_MNODE(larb22, SLAVE_LARB(22), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
DEFINE_MNODE(larb23, SLAVE_LARB(23), 0, false, 0x1, MASTER_COMMON_PORT(0, 8)),
DEFINE_MNODE(disp_postmask0,
MASTER_LARB_PORT(M4U_PORT_L0_DISP_POSTMASK0), 8, false, 0x1, SLAVE_LARB(0)),
DEFINE_MNODE(ovl_rdma0_hdr,
MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0_HDR), 7, false, 0x1, SLAVE_LARB(0)),
DEFINE_MNODE(ovl_rdma0,
MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0), 8, false, 0x1, SLAVE_LARB(0)),
DEFINE_MNODE(disp_fake0,
MASTER_LARB_PORT(M4U_PORT_L0_DISP_FAKE0), 8, false, 0x1, SLAVE_LARB(0)),
DEFINE_MNODE(ovl_2L_rdma0_hdr,
MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0_HDR), false, 7, 0x2, SLAVE_LARB(1)),
DEFINE_MNODE(ovl_2L_rdma0,
MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0), 8, false, 0x2, SLAVE_LARB(1)),
DEFINE_MNODE(disp_rdma0,
MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA0), 8, false, 0x2, SLAVE_LARB(1)),
DEFINE_MNODE(disp_wdma0,
MASTER_LARB_PORT(M4U_PORT_L1_DISP_WDMA0), 9, true, 0x2, SLAVE_LARB(1)),
DEFINE_MNODE(disp_fake1,
MASTER_LARB_PORT(M4U_PORT_L1_DISP_FAKE1), 8, false, 0x2, SLAVE_LARB(1)),
DEFINE_MNODE(mdp_rdma0,
MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0), 7, false, 0x2, SLAVE_LARB(2)),
DEFINE_MNODE(mdp_rdma1,
MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1), 7, false, 0x2, SLAVE_LARB(2)),
DEFINE_MNODE(mdp_wrot0,
MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0), 8, true, 0x2, SLAVE_LARB(2)),
DEFINE_MNODE(mdp_wrot1,
MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1), 8, true, 0x2, SLAVE_LARB(2)),
DEFINE_MNODE(mdp_disp_fake0,
MASTER_LARB_PORT(M4U_PORT_L2_MDP_DISP_FAKE0), 8, false, 0x2, SLAVE_LARB(2)),
DEFINE_MNODE(hw_vdec_mc_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_MC_EXT), 6, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_ufo_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_UFO_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_pp_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PP_EXT), 8, true, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_pred_rd_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_RD_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_pred_wr_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_WR_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_ppwrap_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PPWRAP_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_tile_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_TILE_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_vld_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_vld2_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD2_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_avc_mv_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_AVC_MV_EXT), 6, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_rg_ctrl_dma_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT), 7, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(hw_vdec_ufo_enc_ext,
MASTER_LARB_PORT(M4U_PORT_L4_VDEC_UFO_ENC_EXT), 6, false, 0x2, SLAVE_LARB(4)),
DEFINE_MNODE(venc_rcpu,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_rec,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC), 8, true, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_bsdma,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDMA), 8, true, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_sv_comv,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV), 8, true, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_rd_comv,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_cur_luma,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_cur_chroma,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_ref_luma,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(venc_ref_chroma,
MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(jpgenc_y_rdma,
MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(jpgenc_c_rdma,
MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(jpgenc_q_table,
MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(jpgenc_bsdma,
MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA), 8, true, 0x1, SLAVE_LARB(7)),
DEFINE_MNODE(imgi_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(imgbi_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGBI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(dmgi_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_DMGI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(depi_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_DEPI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(lce_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_ICE_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(smti_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(smto_d2,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_D2), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(smto_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_D1), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(crzo_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_CRZO_D1), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img3o_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMG3O_D1), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(vipi_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_VIPI_D1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(smti_d5,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_D5), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(timgo_d1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_TIMGO_D1), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(ufbc_w0,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_UFBC_W0), 9, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(ufbc_r0,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_UFBC_R0), 8, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_wpe_rdma1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_WPE_RDMA1), 6, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_wpe_rdma0,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_WPE_RDMA0), 6, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_wpe_wmda,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_WPE_WDMA), 7, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma0,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA0), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA1), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma2,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA2), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma3,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA3), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma4,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA4), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_rdma5,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_RDMA5), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_wdma0,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_WDMA0), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_mfb_wdma1,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_MFB_WDMA1), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_reserve6,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_RESERVE6), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_reserve7,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_RESERVE7), 8, true, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(img_reserve8,
MASTER_LARB_PORT(M4U_PORT_L9_IMG_RESERVE8), 7, false, 0x2, SLAVE_LARB(9)),
DEFINE_MNODE(imgi_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMGI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(imgbi_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMGBI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(dmgi_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_DMGI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(depi_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_DEPI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(lce_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_ICE_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(smti_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(smto_d2,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTO_D2), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(smto_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTO_D1), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(crzo_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_CRZO_D1), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(img3o_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMG3O_D1), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(vipi_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_VIPI_D1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(smti_d5,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTI_D5), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(timgo_d1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_TIMGO_D1), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(ufbc_w0,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_UFBC_W0), 9, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(ufbc_r0,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_UFBC_R0), 8, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(wpe_rdma1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_RDMA1), 6, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(wpe_rdma0,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_RDMA0), 6, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(wpe_wdma,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_WDMA), 7, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma0,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA0), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA1), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma2,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA2), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma3,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA3), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma4,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA4), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_rdma5,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA5), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_wdma0,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_WDMA0), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mfb_wdma1,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_WDMA1), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(reserve6,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_RESERVE6), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(reserve7,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_RESERVE7), 8, true, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(reserve8,
MASTER_LARB_PORT(M4U_PORT_L11_IMG_RESERVE8), 7, false, 0x2, SLAVE_LARB(11)),
DEFINE_MNODE(mrawi,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_MRAWI), 7, false, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(mrawo_0,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_MRAWO0), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(mrawo_1,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_MRAWO1), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_1,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_RESERVE1), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_2,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_RESERVE2), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_3,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_RESERVE3), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_4,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_CAMSV4), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_5,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_CAMSV5), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(camsv_6,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_CAMSV6), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(ccui,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_CCUI), 7, false, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(ccuo,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_CCUO), 8, true, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(fake,
MASTER_LARB_PORT(M4U_PORT_L13_CAM_FAKE), 7, false, 0x2, SLAVE_LARB(13)),
DEFINE_MNODE(mrawi,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_RESERVE1), 7, false, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(mrawo_0,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_RESERVE2), 8, true, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(mrawo_1,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_RESERVE3), 8, true, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(mrawo_1,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_RESERVE4), 8, true, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(ccui,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_CCUI), 7, false, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(ccuo,
MASTER_LARB_PORT(M4U_PORT_L14_CAM_CCUO), 8, true, 0x1, SLAVE_LARB(14)),
DEFINE_MNODE(imgo_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_IMGO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(rrzo_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_RRZO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(cqi_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_CQI_R1_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(bpci_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_BPCI_R1_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(yuvo_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_YUVO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(ufdi_r2_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_UFDI_R2_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(rawi_r2_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R2_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(rawi_r3_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R3_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(aao_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_AAO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(afo_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_AFO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(flko_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_FLKO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(lceso_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_LCESO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(crzo_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_CRZO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(ltmso_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_LTMSO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(rsso_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_RSSO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(aaho_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_AAHO_R1_A), 8, true, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(lsci_r1_a,
MASTER_LARB_PORT(M4U_PORT_L16_CAM_LSCI_R1_A), 7, false, 0x1, SLAVE_LARB(16)),
DEFINE_MNODE(imgo_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_IMGO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(rrzo_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_RRZO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(cqi_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_CQI_R1_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(bpci_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_BPCI_R1_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(yuvo_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_YUVO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(ufdi_r2_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_UFDI_R2_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(rawi_r2_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_RAWI_R2_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(rawi_r3_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_RAWI_R3_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(aao_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_AAO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(afo_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_AFO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(flko_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_FLKO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(lceso_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_LCESO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(crzo_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_CRZO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(ltmso_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_LTMSO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(rsso_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_RSSO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(aaho_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_AAHO_R1_B), 8, true, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(lsci_r1_b,
MASTER_LARB_PORT(M4U_PORT_L17_CAM_LSCI_R1_B), 7, false, 0x2, SLAVE_LARB(17)),
DEFINE_MNODE(dvs_rdma,
MASTER_LARB_PORT(M4U_PORT_L19_IPE_DVS_RDMA), 7, false, 0x2, SLAVE_LARB(19)),
DEFINE_MNODE(dvs_wdma,
MASTER_LARB_PORT(M4U_PORT_L19_IPE_DVS_WDMA), 8, true, 0x2, SLAVE_LARB(19)),
DEFINE_MNODE(dvp_rdma,
MASTER_LARB_PORT(M4U_PORT_L19_IPE_DVP_RDMA), 7, false, 0x2, SLAVE_LARB(19)),
DEFINE_MNODE(dvp_wdma,
MASTER_LARB_PORT(M4U_PORT_L19_IPE_DVP_WDMA), 8, true, 0x2, SLAVE_LARB(19)),
DEFINE_MNODE(fdvt_rda,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_FDVT_RDA), 7, false, 0x2, SLAVE_LARB(20)),
DEFINE_MNODE(fdvt_rdb,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_FDVT_RDB), 7, false, 0x2, SLAVE_LARB(20)),
DEFINE_MNODE(fdvt_wra,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_FDVT_WRA), 8, true, 0x2, SLAVE_LARB(20)),
DEFINE_MNODE(fdvt_wrb,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_FDVT_WRB), 8, true, 0x2, SLAVE_LARB(20)),
DEFINE_MNODE(rsc_rdma0,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_RSC_RDMA0), 7, false, 0x2, SLAVE_LARB(20)),
DEFINE_MNODE(rsc_wdma,
MASTER_LARB_PORT(M4U_PORT_L20_IPE_RSC_WDMA), 8, true, 0x2, SLAVE_LARB(20)),
};
static const char * const comm_muxes_mt6853[] = { "mm" };
static const char * const comm_icc_path_names_mt6853[] = { "icc-bw" };
static const char * const comm_icc_hrt_path_names_mt6853[] = { "icc-hrt-bw" };
static const char * const larb_icc_path_names_mt6853[] = { "larb0", "larb1", "larb2", NULL,
"larb4", NULL, NULL, "larb7", NULL, "larb9", NULL, "larb11", NULL, "larb13", "larb14",
NULL, "larb16", "larb17", NULL, "larb19", "larb20", NULL, NULL, NULL };
static const struct mtk_mmqos_desc mmqos_desc_mt6853 = {
.nodes = node_descs_mt6853,
.num_nodes = ARRAY_SIZE(node_descs_mt6853),
.comm_muxes = comm_muxes_mt6853,
.comm_icc_path_names = comm_icc_path_names_mt6853,
.comm_icc_hrt_path_names = comm_icc_hrt_path_names_mt6853,
.larb_icc_path_names = larb_icc_path_names_mt6853,
.max_ratio = 40,
.hrt_LPDDR4 = {
.hrt_bw = {3344, 0, 0},
.hrt_total_bw = 8532, /* Todo: Use DRAMC API */
.md_speech_bw = { 3344, 3344},
.hrt_ratio = {1000, 1000, 1000, 1000},
.blocking = true,
.emi_ratio = 1000,
},
.comm_port_channels = {
{ 0x1, 0x2, 0x2, 0x1, 0x2, 0x2, 0x1, 0x2, 0x3 }
},
.comm_port_hrt_types = {
{ HRT_MAX_BWL, HRT_MAX_BWL, HRT_NONE, HRT_NONE, HRT_NONE,
HRT_NONE, HRT_CAM, HRT_CAM, HRT_DISP },
},
};
static const struct of_device_id mtk_mmqos_mt6853_of_ids[] = {
{
.compatible = "mediatek,mt6853-mmqos",
.data = &mmqos_desc_mt6853,
},
{}
};
MODULE_DEVICE_TABLE(of, mtk_mmqos_mt6853_of_ids);
static struct platform_driver mtk_mmqos_mt6853_driver = {
.probe = mtk_mmqos_probe,
.remove = mtk_mmqos_remove,
.driver = {
.name = "mtk-mt6853-mmqos",
.of_match_table = mtk_mmqos_mt6853_of_ids,
},
};
module_platform_driver(mtk_mmqos_mt6853_driver);
MODULE_LICENSE("GPL v2");
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