mirror of
https://github.com/physwizz/a155-U-u1.git
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744 lines
18 KiB
C
744 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <mt-plat/mtk_gpu_utility.h>
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#include <mtk_gpufreq.h>
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unsigned int (*mtk_get_gpu_memory_usage_fp)(void) = NULL;
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static int gpu_pmu_flag;
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EXPORT_SYMBOL(mtk_get_gpu_memory_usage_fp);
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bool mtk_get_gpu_memory_usage(unsigned int *pMemUsage)
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{
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if (mtk_get_gpu_memory_usage_fp != NULL) {
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if (pMemUsage) {
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*pMemUsage = mtk_get_gpu_memory_usage_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_memory_usage);
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unsigned int (*mtk_get_gpu_loading_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_loading_fp);
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bool mtk_get_gpu_loading(unsigned int *pLoading)
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{
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if (mtk_get_gpu_loading_fp != NULL) {
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if (pLoading) {
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*pLoading = mtk_get_gpu_loading_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_loading);
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unsigned int (*mtk_get_gpu_block_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_block_fp);
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bool mtk_get_gpu_block(unsigned int *pBlock)
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{
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if (mtk_get_gpu_block_fp != NULL) {
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if (pBlock) {
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*pBlock = mtk_get_gpu_block_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_block);
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unsigned int (*mtk_get_gpu_idle_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_idle_fp);
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bool mtk_get_gpu_idle(unsigned int *pIdle)
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{
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if (mtk_get_gpu_idle_fp != NULL) {
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if (pIdle) {
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*pIdle = mtk_get_gpu_idle_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_idle);
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void (*mtk_set_bottom_gpu_freq_fp)(unsigned int) = NULL;
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EXPORT_SYMBOL(mtk_set_bottom_gpu_freq_fp);
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bool mtk_set_bottom_gpu_freq(unsigned int ui32FreqLevel)
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{
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if (mtk_set_bottom_gpu_freq_fp != NULL) {
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mtk_set_bottom_gpu_freq_fp(ui32FreqLevel);
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_set_bottom_gpu_freq);
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/* -------------------------------------------------------------------------- */
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unsigned int (*mtk_get_bottom_gpu_freq_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_bottom_gpu_freq_fp);
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bool mtk_get_bottom_gpu_freq(unsigned int *pui32FreqLevel)
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{
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if ((mtk_get_bottom_gpu_freq_fp != NULL) && (pui32FreqLevel)) {
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*pui32FreqLevel = mtk_get_bottom_gpu_freq_fp();
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_bottom_gpu_freq);
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/* -------------------------------------------------------------------------- */
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unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_custom_get_gpu_freq_level_count_fp);
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bool mtk_custom_get_gpu_freq_level_count(unsigned int *pui32FreqLevelCount)
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{
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if (mtk_custom_get_gpu_freq_level_count_fp != NULL) {
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if (pui32FreqLevelCount) {
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*pui32FreqLevelCount =
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mtk_custom_get_gpu_freq_level_count_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_custom_get_gpu_freq_level_count);
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/* -------------------------------------------------------------------------- */
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unsigned long (*mtk_get_custom_boost_gpu_freq_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_custom_boost_gpu_freq_fp);
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bool mtk_get_custom_boost_gpu_freq(unsigned long *pulFreq)
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{
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if (mtk_get_custom_boost_gpu_freq_fp != NULL) {
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if (pulFreq) {
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*pulFreq = mtk_get_custom_boost_gpu_freq_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_custom_boost_gpu_freq);
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/* -------------------------------------------------------------------------- */
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void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel) = NULL;
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EXPORT_SYMBOL(mtk_custom_boost_gpu_freq_fp);
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bool mtk_custom_boost_gpu_freq(unsigned int ui32FreqLevel)
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{
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if (mtk_custom_boost_gpu_freq_fp != NULL) {
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mtk_custom_boost_gpu_freq_fp(ui32FreqLevel);
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_custom_boost_gpu_freq);
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/* -------------------------------------------------------------------------- */
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unsigned long (*mtk_get_custom_upbound_gpu_freq_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_custom_upbound_gpu_freq_fp);
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bool mtk_get_custom_upbound_gpu_freq(unsigned long *pulFreq)
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{
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if (mtk_get_custom_upbound_gpu_freq_fp != NULL) {
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if (pulFreq) {
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*pulFreq = mtk_get_custom_upbound_gpu_freq_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_custom_upbound_gpu_freq);
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/* -------------------------------------------------------------------------- */
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void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel) = NULL;
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EXPORT_SYMBOL(mtk_custom_upbound_gpu_freq_fp);
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bool mtk_custom_upbound_gpu_freq(unsigned int ui32FreqLevel)
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{
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if (mtk_custom_upbound_gpu_freq_fp != NULL) {
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mtk_custom_upbound_gpu_freq_fp(ui32FreqLevel);
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_custom_upbound_gpu_freq);
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/* -------------------------------------------------------------------------- */
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bool (*mtk_dump_gpu_memory_usage_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_dump_gpu_memory_usage_fp);
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bool mtk_dump_gpu_memory_usage(void)
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{
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if (mtk_dump_gpu_memory_usage_fp != NULL) {
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mtk_dump_gpu_memory_usage_fp();
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_dump_gpu_memory_usage);
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/* -------------------------------------------------------------------------- */
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unsigned long (*mtk_get_gpu_bottom_freq_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_bottom_freq_fp);
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bool mtk_get_gpu_bottom_freq(unsigned long *pulFreq)
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{
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if (mtk_get_gpu_bottom_freq_fp != NULL) {
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if (pulFreq) {
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*pulFreq = mtk_get_gpu_bottom_freq_fp();
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_bottom_freq);
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/* -------------------------------------------------------------------------- */
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#if defined(CONFIG_MTK_GPUFREQ_V2)
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int (*mtk_get_gpu_limit_index_fp)(enum gpufreq_target target,
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enum gpuppm_limit_type limit) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_limit_index_fp);
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bool mtk_get_gpu_floor_index(int *piIndex)
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{
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if (mtk_get_gpu_limit_index_fp != NULL) {
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if (piIndex) {
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*piIndex = mtk_get_gpu_limit_index_fp(
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TARGET_DEFAULT, GPUPPM_FLOOR);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_floor_index);
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bool mtk_get_gpu_ceiling_index(int *piIndex)
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{
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if (mtk_get_gpu_limit_index_fp != NULL) {
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if (piIndex) {
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*piIndex = mtk_get_gpu_limit_index_fp(
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TARGET_DEFAULT, GPUPPM_CEILING);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_ceiling_index);
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/* -------------------------------------------------------------------------- */
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unsigned int (*mtk_get_gpu_limiter_fp)(enum gpufreq_target target,
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enum gpuppm_limit_type limit) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_limiter_fp);
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bool mtk_get_gpu_floor_limiter(unsigned int *puiLimiter)
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{
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if (mtk_get_gpu_limiter_fp != NULL) {
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if (puiLimiter) {
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*puiLimiter = mtk_get_gpu_limiter_fp(
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TARGET_DEFAULT, GPUPPM_FLOOR);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_floor_limiter);
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bool mtk_get_gpu_ceiling_limiter(unsigned int *puiLimiter)
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{
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if (mtk_get_gpu_limiter_fp != NULL) {
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if (puiLimiter) {
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*puiLimiter = mtk_get_gpu_limiter_fp(
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TARGET_DEFAULT, GPUPPM_CEILING);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_ceiling_limiter);
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/* -------------------------------------------------------------------------- */
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unsigned int (*mtk_get_gpu_cur_freq_fp)(enum gpufreq_target target) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_cur_freq_fp);
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bool mtk_get_gpu_cur_freq(unsigned int *puiFreq)
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{
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if (mtk_get_gpu_cur_freq_fp != NULL) {
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if (puiFreq) {
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*puiFreq = mtk_get_gpu_cur_freq_fp(TARGET_DEFAULT);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_cur_freq);
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/* -------------------------------------------------------------------------- */
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int (*mtk_get_gpu_cur_oppidx_fp)(enum gpufreq_target target) = NULL;
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EXPORT_SYMBOL(mtk_get_gpu_cur_oppidx_fp);
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bool mtk_get_gpu_cur_oppidx(int *piIndex)
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{
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if (mtk_get_gpu_cur_oppidx_fp != NULL) {
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if (piIndex) {
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*piIndex = mtk_get_gpu_cur_oppidx_fp(TARGET_DEFAULT);
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_cur_oppidx);
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/* -------------------------------------------------------------------------- */
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#else /* CONFIG_MTK_GPUFREQ_V2 */
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bool mtk_get_gpu_floor_index(int *piIndex)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_floor_index);
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bool mtk_get_gpu_ceiling_index(int *piIndex)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_ceiling_index);
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bool mtk_get_gpu_floor_limiter(unsigned int *puiLimiter)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_floor_limiter);
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bool mtk_get_gpu_ceiling_limiter(unsigned int *puiLimiter)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_ceiling_limiter);
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bool mtk_get_gpu_cur_freq(unsigned int *puiFreq)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_cur_freq);
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bool mtk_get_gpu_cur_oppidx(int *piIndex)
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{
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_cur_oppidx);
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#endif /* CONFIG_MTK_GPUFREQ_V2 */
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/* -------------------------------------------------------------------------- */
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int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus, int pmuSize, int *retSize);
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EXPORT_SYMBOL(mtk_get_gpu_pmu_init_fp);
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bool mtk_get_gpu_pmu_init(struct GPU_PMU *pmus, int pmu_size, int *ret_size)
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{
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if (mtk_get_gpu_pmu_init_fp != NULL)
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return mtk_get_gpu_pmu_init_fp(pmus, pmu_size, ret_size) == 0;
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_pmu_init);
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/* -------------------------------------------------------------------------- */
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int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
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EXPORT_SYMBOL(mtk_get_gpu_pmu_swapnreset_fp);
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bool mtk_get_gpu_pmu_swapnreset(struct GPU_PMU *pmus, int pmu_size)
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{
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if (mtk_get_gpu_pmu_swapnreset_fp != NULL) {
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gpu_pmu_flag = 1;
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return mtk_get_gpu_pmu_swapnreset_fp(pmus, pmu_size) == 0;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_pmu_swapnreset);
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/* -------------------------------------------------------------------------- */
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struct sGpuPowerChangeEntry {
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void (*callback)(int power_on);
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char name[128];
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struct list_head sList;
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};
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static struct {
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struct mutex lock;
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struct list_head listen;
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} g_power_change = {
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.lock = __MUTEX_INITIALIZER(g_power_change.lock),
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.listen = LIST_HEAD_INIT(g_power_change.listen),
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};
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bool mtk_register_gpu_power_change(const char *name,
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void (*callback)(int power_on))
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{
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struct sGpuPowerChangeEntry *entry = NULL;
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entry = kmalloc(sizeof(struct sGpuPowerChangeEntry), GFP_KERNEL);
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if (entry == NULL)
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return false;
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entry->callback = callback;
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strncpy(entry->name, name, sizeof(entry->name) - 1);
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entry->name[sizeof(entry->name) - 1] = 0;
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INIT_LIST_HEAD(&entry->sList);
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mutex_lock(&g_power_change.lock);
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list_add(&entry->sList, &g_power_change.listen);
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mutex_unlock(&g_power_change.lock);
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return true;
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}
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EXPORT_SYMBOL(mtk_register_gpu_power_change);
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bool mtk_unregister_gpu_power_change(const char *name)
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{
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struct list_head *pos, *head;
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struct sGpuPowerChangeEntry *entry = NULL;
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mutex_lock(&g_power_change.lock);
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head = &g_power_change.listen;
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list_for_each(pos, head) {
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entry = list_entry(pos, struct sGpuPowerChangeEntry, sList);
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if (strncmp(entry->name, name, sizeof(entry->name) - 1) == 0)
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break;
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entry = NULL;
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}
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if (entry) {
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list_del(&entry->sList);
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kfree(entry);
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}
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mutex_unlock(&g_power_change.lock);
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return true;
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}
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EXPORT_SYMBOL(mtk_unregister_gpu_power_change);
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void mtk_notify_gpu_power_change(int power_on)
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{
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struct list_head *pos, *head;
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struct sGpuPowerChangeEntry *entry = NULL;
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if (!gpu_pmu_flag) {
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mutex_lock(&g_power_change.lock);
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head = &g_power_change.listen;
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list_for_each(pos, head) {
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entry = list_entry(pos,
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struct sGpuPowerChangeEntry,
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sList);
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entry->callback(power_on);
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}
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mutex_unlock(&g_power_change.lock);
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}
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}
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EXPORT_SYMBOL(mtk_notify_gpu_power_change);
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int (*mtk_get_gpu_pmu_deinit_fp)(void);
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EXPORT_SYMBOL(mtk_get_gpu_pmu_deinit_fp);
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bool mtk_get_gpu_pmu_deinit(void)
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{
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if (mtk_get_gpu_pmu_deinit_fp != NULL)
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return mtk_get_gpu_pmu_deinit_fp() == 0;
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_pmu_deinit);
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int (*mtk_get_gpu_pmu_swapnreset_stop_fp)(void);
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EXPORT_SYMBOL(mtk_get_gpu_pmu_swapnreset_stop_fp);
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bool mtk_get_gpu_pmu_swapnreset_stop(void)
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{
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if (mtk_get_gpu_pmu_swapnreset_stop_fp != NULL) {
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gpu_pmu_flag = 0;
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return mtk_get_gpu_pmu_swapnreset_stop_fp() == 0;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_get_gpu_pmu_swapnreset_stop);
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/* ------------------------------------------------------------------------ */
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void (*mtk_dvfs_margin_value_fp)(int i32MarginValue) = NULL;
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EXPORT_SYMBOL(mtk_dvfs_margin_value_fp);
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bool mtk_dvfs_margin_value(int i32MarginValue)
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{
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if (mtk_dvfs_margin_value_fp != NULL) {
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mtk_dvfs_margin_value_fp(i32MarginValue);
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return true;
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}
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return false;
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}
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EXPORT_SYMBOL(mtk_dvfs_margin_value);
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int (*mtk_get_dvfs_margin_value_fp)(void) = NULL;
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EXPORT_SYMBOL(mtk_get_dvfs_margin_value_fp);
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bool mtk_get_dvfs_margin_value(int *pi32MarginValue)
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|
{
|
|
if ((mtk_get_dvfs_margin_value_fp != NULL) &&
|
|
(pi32MarginValue != NULL)) {
|
|
|
|
*pi32MarginValue = mtk_get_dvfs_margin_value_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_get_dvfs_margin_value);
|
|
|
|
/* -------------------------------------------------------------------------*/
|
|
void (*mtk_loading_base_dvfs_step_fp)(int i32StepValue) = NULL;
|
|
EXPORT_SYMBOL(mtk_loading_base_dvfs_step_fp);
|
|
|
|
bool mtk_loading_base_dvfs_step(int i32StepValue)
|
|
{
|
|
if (mtk_loading_base_dvfs_step_fp != NULL) {
|
|
mtk_loading_base_dvfs_step_fp(i32StepValue);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_loading_base_dvfs_step);
|
|
|
|
int (*mtk_get_loading_base_dvfs_step_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_get_loading_base_dvfs_step_fp);
|
|
|
|
bool mtk_get_loading_base_dvfs_step(int *pi32StepValue)
|
|
{
|
|
if ((mtk_get_loading_base_dvfs_step_fp != NULL) &&
|
|
(pi32StepValue != NULL)) {
|
|
*pi32StepValue = mtk_get_loading_base_dvfs_step_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_get_loading_base_dvfs_step);
|
|
/* ------------------------------------------------------------------------ */
|
|
void (*mtk_timer_base_dvfs_margin_fp)(int i32MarginValue) = NULL;
|
|
EXPORT_SYMBOL(mtk_timer_base_dvfs_margin_fp);
|
|
|
|
bool mtk_timer_base_dvfs_margin(int i32MarginValue)
|
|
{
|
|
if (mtk_timer_base_dvfs_margin_fp != NULL) {
|
|
mtk_timer_base_dvfs_margin_fp(i32MarginValue);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_timer_base_dvfs_margin);
|
|
|
|
int (*mtk_get_timer_base_dvfs_margin_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_get_timer_base_dvfs_margin_fp);
|
|
|
|
bool mtk_get_timer_base_dvfs_margin(int *pi32MarginValue)
|
|
{
|
|
if ((mtk_get_timer_base_dvfs_margin_fp != NULL) &&
|
|
(pi32MarginValue != NULL)) {
|
|
|
|
*pi32MarginValue = mtk_get_timer_base_dvfs_margin_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_get_timer_base_dvfs_margin);
|
|
/* ------------------------------------------------------------------------ */
|
|
void (*mtk_dvfs_loading_mode_fp)(int i32LoadingMode) = NULL;
|
|
EXPORT_SYMBOL(mtk_dvfs_loading_mode_fp);
|
|
|
|
bool mtk_dvfs_loading_mode(int i32LoadingMode)
|
|
{
|
|
if (mtk_dvfs_loading_mode_fp != NULL) {
|
|
mtk_dvfs_loading_mode_fp(i32LoadingMode);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_dvfs_loading_mode);
|
|
|
|
int (*mtk_get_dvfs_loading_mode_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_get_dvfs_loading_mode_fp);
|
|
|
|
bool mtk_get_dvfs_loading_mode(unsigned int *pui32LoadingMode)
|
|
{
|
|
if ((mtk_get_dvfs_loading_mode_fp != NULL) &&
|
|
(pui32LoadingMode != NULL)) {
|
|
|
|
*pui32LoadingMode = mtk_get_dvfs_loading_mode_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_get_dvfs_loading_mode);
|
|
|
|
void (*mtk_set_fastdvfs_mode_fp)(unsigned int u32Mode) = NULL;
|
|
EXPORT_SYMBOL(mtk_set_fastdvfs_mode_fp);
|
|
|
|
bool mtk_set_fastdvfs_mode(unsigned int u32Mode)
|
|
{
|
|
if (mtk_set_fastdvfs_mode_fp != NULL) {
|
|
mtk_set_fastdvfs_mode_fp(u32Mode);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_set_fastdvfs_mode);
|
|
|
|
unsigned int (*mtk_get_fastdvfs_mode_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_get_fastdvfs_mode_fp);
|
|
|
|
bool mtk_get_fastdvfs_mode(unsigned int *pui32Mode)
|
|
{
|
|
if (pui32Mode == NULL)
|
|
return false;
|
|
|
|
if ((mtk_get_fastdvfs_mode_fp != NULL) &&
|
|
(pui32Mode != NULL)) {
|
|
|
|
*pui32Mode = mtk_get_fastdvfs_mode_fp();
|
|
return true;
|
|
}
|
|
|
|
*pui32Mode = 0;
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_get_fastdvfs_mode);
|
|
|
|
/* -----------------------------gpu pmu fp--------------------------------- */
|
|
void (*mtk_ltr_gpu_pmu_start_fp)(unsigned int interval_ns) = NULL;
|
|
EXPORT_SYMBOL(mtk_ltr_gpu_pmu_start_fp);
|
|
|
|
bool mtk_ltr_gpu_pmu_start(unsigned int interval_ns)
|
|
{
|
|
if (mtk_ltr_gpu_pmu_start_fp != NULL) {
|
|
mtk_ltr_gpu_pmu_start_fp(interval_ns);
|
|
return true;
|
|
}
|
|
return false;
|
|
|
|
}
|
|
EXPORT_SYMBOL(mtk_ltr_gpu_pmu_start);
|
|
|
|
void (*mtk_swpm_gpu_pm_start_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_swpm_gpu_pm_start_fp);
|
|
|
|
bool mtk_swpm_gpu_pm_start(void)
|
|
{
|
|
if (mtk_swpm_gpu_pm_start_fp != NULL) {
|
|
mtk_swpm_gpu_pm_start_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
|
|
}
|
|
EXPORT_SYMBOL(mtk_swpm_gpu_pm_start);
|
|
|
|
void (*mtk_ltr_gpu_pmu_stop_fp)(void) = NULL;
|
|
EXPORT_SYMBOL(mtk_ltr_gpu_pmu_stop_fp);
|
|
|
|
bool mtk_ltr_gpu_pmu_stop(void)
|
|
{
|
|
if (mtk_ltr_gpu_pmu_stop_fp != NULL) {
|
|
mtk_ltr_gpu_pmu_stop_fp();
|
|
return true;
|
|
}
|
|
return false;
|
|
|
|
}
|
|
EXPORT_SYMBOL(mtk_ltr_gpu_pmu_stop);
|
|
|
|
/* -----------------------------set gpu idle time--------------------------------- */
|
|
|
|
void (*mtk_set_gpu_idle_fp)(unsigned int val) = NULL;
|
|
EXPORT_SYMBOL(mtk_set_gpu_idle_fp);
|
|
|
|
bool mtk_set_gpu_idle(unsigned int val)
|
|
{
|
|
if (mtk_set_gpu_idle_fp != NULL) {
|
|
mtk_set_gpu_idle_fp(val);
|
|
return true;
|
|
}
|
|
return false;
|
|
|
|
}
|
|
EXPORT_SYMBOL(mtk_set_gpu_idle);
|
|
|
|
|
|
/* ----------------------gpufreq change notify fp-------------------------- */
|
|
void (*mtk_notify_gpu_freq_change_fp)(u32 clk_idx, u32 gpufreq) = NULL;
|
|
EXPORT_SYMBOL(mtk_notify_gpu_freq_change_fp);
|
|
|
|
bool mtk_notify_gpu_freq_change(u32 clk_idx, u32 gpufreq)
|
|
{
|
|
if (mtk_notify_gpu_freq_change_fp != NULL) {
|
|
mtk_notify_gpu_freq_change_fp(clk_idx, gpufreq);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
EXPORT_SYMBOL(mtk_notify_gpu_freq_change);
|
|
|
|
/* ------------------------------------------------------------------------ */
|
|
|
|
/* ----------------------gpu fence debug fp-------------------------- */
|
|
void (*mtk_gpu_fence_debug_dump_fp)(int fd, int pid, int type, int timeouts) = NULL;
|
|
EXPORT_SYMBOL(mtk_gpu_fence_debug_dump_fp);
|
|
|
|
void mtk_gpu_fence_debug_dump(int fd, int pid, int type, int timeouts)
|
|
{
|
|
if (mtk_gpu_fence_debug_dump_fp != NULL)
|
|
mtk_gpu_fence_debug_dump_fp(fd, pid, type, timeouts);
|
|
}
|
|
EXPORT_SYMBOL(mtk_gpu_fence_debug_dump);
|
|
|
|
static int mtk_gpu_hal_init(void)
|
|
{
|
|
/*Do Nothing*/
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_gpu_hal_exit(void)
|
|
{
|
|
/*Do Nothing*/
|
|
;
|
|
}
|
|
|
|
arch_initcall(mtk_gpu_hal_init);
|
|
module_exit(mtk_gpu_hal_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("MediaTek GPU HAL");
|
|
MODULE_AUTHOR("MediaTek Inc.");
|
|
|