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https://github.com/physwizz/a155-U-u1.git
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121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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/**
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* @file mtk_gpu_dfd.c
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* @brief GPU DFD
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*/
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/**
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* ===============================================
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* SECTION : Include files
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* ===============================================
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*/
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#include <linux/seq_file.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <gpufreq_v2.h>
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#include <gpu_misc.h>
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#include <gpudfd_mt6789.h>
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#include <gpufreq_debug.h>
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/**
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* ===============================================
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* Local variables definition
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* ===============================================
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*/
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static void __iomem *g_mfg_top_base;
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static struct gpufreq_platform_fp *gpufreq_fp;
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static unsigned int g_dfd_force_dump_mode;
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static struct gpudfd_platform_fp platform_fp = {
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.get_dfd_force_dump_mode = __gpudfd_get_dfd_force_dump_mode,
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.set_dfd_force_dump_mode = __gpudfd_set_dfd_force_dump_mode,
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.config_dfd = __gpudfd_config_dfd,
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};
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void __gpudfd_set_dfd_force_dump_mode(unsigned int mode)
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{
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/*
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* mode = 0, disable force dump
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* mode = 1, enable force dump
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*/
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g_dfd_force_dump_mode = mode;
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}
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unsigned int __gpudfd_get_dfd_force_dump_mode(void)
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{
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return g_dfd_force_dump_mode;
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}
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void __gpudfd_config_dfd(unsigned int enable)
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{
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#if GPUDFD_ENABLE
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if (enable) {
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if (__gpudfd_get_dfd_force_dump_mode() == 1)
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writel(MFG_DEBUGMON_CON_00_ENABLE, MFG_DEBUGMON_CON_00);
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writel(MFG_DFD_CON_0_ENABLE, MFG_DFD_CON_0);
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writel(MFG_DFD_CON_1_ENABLE, MFG_DFD_CON_1);
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writel(MFG_DFD_CON_2_ENABLE, MFG_DFD_CON_2);
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writel(MFG_DFD_CON_3_ENABLE, MFG_DFD_CON_3);
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writel(MFG_DFD_CON_4_ENABLE, MFG_DFD_CON_4);
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writel(MFG_DFD_CON_5_ENABLE, MFG_DFD_CON_5);
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writel(MFG_DFD_CON_6_ENABLE, MFG_DFD_CON_6);
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writel(MFG_DFD_CON_7_ENABLE, MFG_DFD_CON_7);
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writel(MFG_DFD_CON_8_ENABLE, MFG_DFD_CON_8);
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writel(MFG_DFD_CON_9_ENABLE, MFG_DFD_CON_9);
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writel(MFG_DFD_CON_10_ENABLE, MFG_DFD_CON_10);
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writel(MFG_DFD_CON_11_ENABLE, MFG_DFD_CON_11);
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} else {
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writel(MFG_DFD_CON_0_DISABLE, MFG_DFD_CON_0);
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writel(MFG_DFD_CON_1_DISABLE, MFG_DFD_CON_1);
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writel(MFG_DFD_CON_2_DISABLE, MFG_DFD_CON_2);
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writel(MFG_DFD_CON_3_DISABLE, MFG_DFD_CON_3);
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writel(MFG_DFD_CON_4_DISABLE, MFG_DFD_CON_4);
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writel(MFG_DFD_CON_5_DISABLE, MFG_DFD_CON_5);
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writel(MFG_DFD_CON_6_DISABLE, MFG_DFD_CON_6);
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writel(MFG_DFD_CON_7_DISABLE, MFG_DFD_CON_7);
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writel(MFG_DFD_CON_8_DISABLE, MFG_DFD_CON_8);
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writel(MFG_DFD_CON_9_DISABLE, MFG_DFD_CON_9);
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writel(MFG_DFD_CON_10_DISABLE, MFG_DFD_CON_10);
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writel(MFG_DFD_CON_11_DISABLE, MFG_DFD_CON_11);
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writel(MFG_DEBUGMON_CON_00_DISABLE, MFG_DEBUGMON_CON_00);
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}
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#else
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(void)(enable);
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#endif
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}
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unsigned int gpudfd_init(struct platform_device *pdev)
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{
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struct device *gpufreq_dev = &pdev->dev;
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struct resource *res;
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int ret = GPUFREQ_SUCCESS;
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/* 0x13FBF000 */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mfg_top_config");
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if (unlikely(!res)) {
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GPUFREQ_LOGE("fail to get resource MFG_TOP_CONFIG");
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goto done;
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}
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g_mfg_top_base = devm_ioremap(gpufreq_dev, res->start, resource_size(res));
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if (unlikely(!g_mfg_top_base)) {
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GPUFREQ_LOGE("fail to ioremap MFG_TOP_CONFIG: 0x%llx", res->start);
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goto done;
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}
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/* register gpudfd platform function to misc */
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gpu_misc_register_gpudfd_fp(&platform_fp);
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done:
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return ret;
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}
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