mirror of
https://github.com/physwizz/a155-U-u1.git
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642 lines
16 KiB
C
Executable File
642 lines
16 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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#include <linux/backlight.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_modes.h>
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#include <linux/delay.h>
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#include <drm/drm_device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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#include <video/of_videomode.h>
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#include <video/videomode.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#define CONFIG_MTK_PANEL_EXT
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#if defined(CONFIG_MTK_PANEL_EXT)
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#include "../mediatek/mediatek_v2/mtk_panel_ext.h"
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#include "../mediatek/mediatek_v2/mtk_drm_graphics_base.h"
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#endif
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struct lcm {
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struct device *dev;
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struct drm_panel panel;
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struct backlight_device *backlight;
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struct gpio_desc *reset_gpio;
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struct gpio_desc *bias_pos, *bias_neg;
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bool prepared;
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bool enabled;
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int error;
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};
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#define lcm_dcs_write_seq(ctx, seq...) \
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({\
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const u8 d[] = { seq };\
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BUILD_BUG_ON_MSG(ARRAY_SIZE(d) > 64, "DCS sequence too big for stack");\
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lcm_dcs_write(ctx, d, ARRAY_SIZE(d));\
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})
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#define lcm_dcs_write_seq_static(ctx, seq...) \
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({\
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static const u8 d[] = { seq };\
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lcm_dcs_write(ctx, d, ARRAY_SIZE(d));\
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})
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static inline struct lcm *panel_to_lcm(struct drm_panel *panel)
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{
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return container_of(panel, struct lcm, panel);
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}
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static void lcm_dcs_write(struct lcm *ctx, const void *data, size_t len)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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ssize_t ret;
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char *addr;
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if (ctx->error < 0)
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return;
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addr = (char *)data;
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if ((int)*addr < 0xB0)
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ret = mipi_dsi_dcs_write_buffer(dsi, data, len);
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else
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ret = mipi_dsi_generic_write(dsi, data, len);
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if (ret < 0) {
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dev_info(ctx->dev, "error %zd writing seq: %ph\n", ret, data);
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ctx->error = ret;
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}
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}
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#ifdef PANEL_SUPPORT_READBACK
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static int lcm_dcs_read(struct lcm *ctx, u8 cmd, void *data, size_t len)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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ssize_t ret;
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if (ctx->error < 0)
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return 0;
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ret = mipi_dsi_dcs_read(dsi, cmd, data, len);
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if (ret < 0) {
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dev_info(ctx->dev, "error %d reading dcs seq:(%#x)\n", ret, cmd);
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ctx->error = ret;
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}
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return ret;
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}
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static void lcm_panel_get_data(struct lcm *ctx)
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{
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u8 buffer[3] = {0};
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static int ret;
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if (ret == 0) {
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ret = lcm_dcs_read(ctx, 0x0A, buffer, 1);
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dev_info(ctx->dev, "return %d data(0x%08x) to dsi engine\n",
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ret, buffer[0] | (buffer[1] << 8));
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}
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}
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#endif
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static void lcm_panel_init(struct lcm *ctx)
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{
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ctx->reset_gpio =
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devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_HIGH);
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if (IS_ERR(ctx->reset_gpio)) {
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dev_info(ctx->dev, "%s: cannot get reset_gpio %ld\n",
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__func__, PTR_ERR(ctx->reset_gpio));
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return;
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}
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gpiod_set_value(ctx->reset_gpio, 0);
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mdelay(20);
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gpiod_set_value(ctx->reset_gpio, 1);
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mdelay(5);
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gpiod_set_value(ctx->reset_gpio, 0);
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mdelay(1);
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gpiod_set_value(ctx->reset_gpio, 1);
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mdelay(20);
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devm_gpiod_put(ctx->dev, ctx->reset_gpio);
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/* Sleep Out */
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lcm_dcs_write_seq_static(ctx, 0x11, 0x00);
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mdelay(90);
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/* Common Setting */
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/* 4.1.1 Global Para. Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xF2,
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0x00, 0x05, 0x0E, 0x58, 0x54, 0x01, 0x0C, 0x00,
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0x04, 0x27, 0x16, 0x27, 0x16, 0x0C, 0x09, 0x74,
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0x27, 0x16, 0x0C, 0x00, 0x04, 0x10, 0x00, 0x10,
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0x26, 0xA8, 0x10, 0x00, 0x10, 0x10, 0x34, 0x10,
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0x00, 0x40, 0x30, 0xC8, 0x00, 0xC8, 0x00, 0x00,
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0xCE);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.2 TE(Vsync) ON/OFF */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0x35, 0x00);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.3 PAGE ADDRESS SET */
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lcm_dcs_write_seq_static(ctx, 0x2A, 0x00, 0x00, 0x04, 0x37);
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lcm_dcs_write_seq_static(ctx, 0x2B, 0x00, 0x00, 0x09, 0x5F);
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/* 4.1.4 FFC SET */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xFC, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x2A, 0xC5);
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lcm_dcs_write_seq_static(ctx, 0xC5, 0x0D, 0x10, 0x80, 0x45);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x2E, 0xC5);
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lcm_dcs_write_seq_static(ctx, 0xC5, 0x53, 0xC7);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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lcm_dcs_write_seq_static(ctx, 0xFC, 0xA5, 0xA5);
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/* 4.1.5 ERR_FG Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xE5, 0x05);
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lcm_dcs_write_seq_static(ctx, 0xED, 0x44, 0x4C, 0x20);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.6 Vsync Setting*/
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x04, 0xF2);
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lcm_dcs_write_seq_static(ctx, 0xF2, 0x54);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.7 PCD Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xCD, 0x5C, 0x51);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.8 ACL Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x03, 0xB3, 0x65);
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lcm_dcs_write_seq_static(ctx, 0x65,
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0x55, 0x00, 0xB0, 0x51, 0x66, 0x98, 0x15, 0x55,
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0x55, 0x55, 0x08, 0xF1, 0xC6, 0x48, 0x40, 0x00,
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0x20, 0x10, 0x09);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.9 DSC Setting */
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lcm_dcs_write_seq_static(ctx, 0x9D, 0x01);
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lcm_dcs_write_seq_static(ctx, 0x9E,
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0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x09, 0x60,
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0x04, 0x38, 0x00, 0x28, 0x02, 0x1C, 0x02, 0x1C,
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0x02, 0x00, 0x02, 0x0E, 0x00, 0x20, 0x03, 0xDD,
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0x00, 0x07, 0x00, 0x0C, 0x02, 0x77, 0x02, 0x8B,
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0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
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0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
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0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
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0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
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0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
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0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
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0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4,
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0x00);
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/* 4.1.10 Freq. Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x27, 0xF2);
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lcm_dcs_write_seq_static(ctx, 0xF2, 0x00);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.11 Porch Clock Set */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x2E, 0xF2);
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lcm_dcs_write_seq_static(ctx, 0xF2, 0x55);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.1.12 ASWIRE Pulse Off Setting */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x0A, 0xB5);
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lcm_dcs_write_seq_static(ctx, 0xB5, 0x00);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* Brightness Setting */
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/* 4.2.1 Max. & Dimming */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0x60, 0x00, 0x00);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x91, 0x63);
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lcm_dcs_write_seq_static(ctx, 0x63, 0x60);
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lcm_dcs_write_seq_static(ctx, 0x53, 0x28);
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lcm_dcs_write_seq_static(ctx, 0x51, 0x03, 0xFF);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.2.2 HBM & Interpolation Dimming */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0x60, 0x00, 0x00);
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lcm_dcs_write_seq_static(ctx, 0xB0, 0x00, 0x91, 0x63);
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lcm_dcs_write_seq_static(ctx, 0x63, 0x20);
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lcm_dcs_write_seq_static(ctx, 0x53, 0xE0);
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lcm_dcs_write_seq_static(ctx, 0x51, 0x02, 0x40);
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lcm_dcs_write_seq_static(ctx, 0xF7, 0x0F);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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/* 4.2.3 ACL ON/OFF */
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lcm_dcs_write_seq_static(ctx, 0xF0, 0x5A, 0x5A);
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lcm_dcs_write_seq_static(ctx, 0x55, 0x03);
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lcm_dcs_write_seq_static(ctx, 0xF0, 0xA5, 0xA5);
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mdelay(40);
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lcm_dcs_write_seq_static(ctx, 0x29, 0x00);
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}
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static int lcm_disable(struct drm_panel *panel)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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if (!ctx->enabled)
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return 0;
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if (ctx->backlight) {
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ctx->backlight->props.power = FB_BLANK_POWERDOWN;
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backlight_update_status(ctx->backlight);
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}
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ctx->enabled = false;
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return 0;
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}
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static int lcm_unprepare(struct drm_panel *panel)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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if (!ctx->prepared)
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return 0;
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lcm_dcs_write_seq_static(ctx, 0x28);
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msleep(50);
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lcm_dcs_write_seq_static(ctx, 0x10);
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msleep(120);
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ctx->error = 0;
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ctx->prepared = false;
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ctx->reset_gpio =
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devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_HIGH);
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if (IS_ERR(ctx->reset_gpio)) {
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dev_info(ctx->dev, "%s: cannot get reset_gpio %ld\n",
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__func__, PTR_ERR(ctx->reset_gpio));
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return PTR_ERR(ctx->reset_gpio);
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}
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gpiod_set_value(ctx->reset_gpio, 0);
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devm_gpiod_put(ctx->dev, ctx->reset_gpio);
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return 0;
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}
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static int lcm_prepare(struct drm_panel *panel)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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int ret;
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pr_info("%s\n", __func__);
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if (ctx->prepared)
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return 0;
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lcm_panel_init(ctx);
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ret = ctx->error;
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if (ret < 0)
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lcm_unprepare(panel);
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ctx->prepared = true;
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#if defined(CONFIG_MTK_PANEL_EXT)
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mtk_panel_tch_rst(panel);
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#endif
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#ifdef PANEL_SUPPORT_READBACK
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lcm_panel_get_data(ctx);
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#endif
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return ret;
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}
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static int lcm_enable(struct drm_panel *panel)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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if (ctx->enabled)
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return 0;
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if (ctx->backlight) {
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ctx->backlight->props.power = FB_BLANK_UNBLANK;
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backlight_update_status(ctx->backlight);
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}
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ctx->enabled = true;
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return 0;
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}
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#define HFP (370)
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#define HSA (10)
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#define HBP (22)
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#define VFP (54)
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#define VSA (8)
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#define VBP (10)
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#define VAC (2400)
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#define HAC (1080)
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static const struct drm_display_mode default_mode = {
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.clock = 330782,
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.hdisplay = HAC,
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.hsync_start = HAC + HFP,
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.hsync_end = HAC + HFP + HSA,
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.htotal = HAC + HFP + HSA + HBP,
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.vdisplay = VAC,
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.vsync_start = VAC + VFP,
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.vsync_end = VAC + VFP + VSA,
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.vtotal = VAC + VFP + VSA + VBP,
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};
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#if defined(CONFIG_MTK_PANEL_EXT)
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static int panel_ext_reset(struct drm_panel *panel, int on)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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ctx->reset_gpio =
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devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_HIGH);
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if (IS_ERR(ctx->reset_gpio)) {
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dev_info(ctx->dev, "%s: cannot get reset_gpio %ld\n",
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__func__, PTR_ERR(ctx->reset_gpio));
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return PTR_ERR(ctx->reset_gpio);
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}
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gpiod_set_value(ctx->reset_gpio, on);
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devm_gpiod_put(ctx->dev, ctx->reset_gpio);
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return 0;
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}
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static int panel_ata_check(struct drm_panel *panel)
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{
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struct lcm *ctx = panel_to_lcm(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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unsigned char data[3] = {0x00, 0x00, 0x00};
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unsigned char id[3] = {0x00, 0x80, 0x00};
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ssize_t ret;
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ret = mipi_dsi_dcs_read(dsi, 0x4, data, 3);
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if (ret < 0) {
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pr_info("%s error\n", __func__);
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return 0;
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}
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pr_info("ATA read data %x %x %x\n", data[0], data[1], data[2]);
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if (data[0] == id[0] &&
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data[1] == id[1] &&
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data[2] == id[2])
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return 1;
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pr_info("ATA expect read data is %x %x %x\n",
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id[0], id[1], id[2]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int lcm_setbacklight_cmdq(void *dsi, dcs_write_gce cb,
|
|
void *handle, unsigned int level)
|
|
{
|
|
char bl_tb0[] = {0x51, 0xFF};
|
|
|
|
bl_tb0[1] = level;
|
|
|
|
if (!cb)
|
|
return -1;
|
|
|
|
cb(dsi, handle, bl_tb0, ARRAY_SIZE(bl_tb0));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct mtk_panel_params ext_params = {
|
|
.pll_clk = 403,
|
|
.vfp_low_power = 1294,
|
|
.cust_esd_check = 0,
|
|
.esd_check_enable = 0,
|
|
.lcm_esd_check_table[0] = {
|
|
.cmd = 0x0a,
|
|
.count = 1,
|
|
.para_list[0] = 0x9c,
|
|
},
|
|
|
|
.output_mode = MTK_PANEL_DSC_SINGLE_PORT,
|
|
.dsc_params = {
|
|
.enable = 1,
|
|
.ver = 17,
|
|
.slice_mode = 1,
|
|
.rgb_swap = 0,
|
|
.dsc_cfg = 34,
|
|
.rct_on = 1,
|
|
.bit_per_channel = 8,
|
|
.dsc_line_buf_depth = 9,
|
|
.bp_enable = 1,
|
|
.bit_per_pixel = 128,
|
|
.pic_height = 2400,
|
|
.pic_width = 1080,
|
|
.slice_height = 40,
|
|
.slice_width = 540,
|
|
.chunk_size = 540,
|
|
.xmit_delay = 512,
|
|
.dec_delay = 526,
|
|
.scale_value = 32,
|
|
.increment_interval = 989,
|
|
.decrement_interval = 7,
|
|
.line_bpg_offset = 12,
|
|
.nfl_bpg_offset = 631,
|
|
.slice_bpg_offset = 651,
|
|
.initial_offset = 6144,
|
|
.final_offset = 4336,
|
|
.flatness_minqp = 3,
|
|
.flatness_maxqp = 12,
|
|
.rc_model_size = 8192,
|
|
.rc_edge_factor = 6,
|
|
.rc_quant_incr_limit0 = 11,
|
|
.rc_quant_incr_limit1 = 11,
|
|
.rc_tgt_offset_hi = 3,
|
|
.rc_tgt_offset_lo = 3,
|
|
},
|
|
.data_rate = 806,
|
|
};
|
|
|
|
static struct mtk_panel_funcs ext_funcs = {
|
|
.reset = panel_ext_reset,
|
|
.set_backlight_cmdq = lcm_setbacklight_cmdq,
|
|
.ata_check = panel_ata_check,
|
|
};
|
|
#endif
|
|
|
|
struct panel_desc {
|
|
const struct drm_display_mode *modes;
|
|
unsigned int num_modes;
|
|
|
|
unsigned int bpc;
|
|
|
|
struct {
|
|
unsigned int width;
|
|
unsigned int height;
|
|
} size;
|
|
|
|
struct {
|
|
unsigned int prepare;
|
|
unsigned int enable;
|
|
unsigned int disable;
|
|
unsigned int unprepare;
|
|
} delay;
|
|
};
|
|
|
|
static int lcm_get_modes(struct drm_panel *panel, struct drm_connector *connector)
|
|
{
|
|
struct drm_display_mode *mode;
|
|
|
|
mode = drm_mode_duplicate(connector->dev, &default_mode);
|
|
if (!mode) {
|
|
dev_info(connector->dev->dev, "failed to add mode %ux%ux@%u\n",
|
|
default_mode.hdisplay, default_mode.vdisplay,
|
|
drm_mode_vrefresh(&default_mode));
|
|
return -ENOMEM;
|
|
}
|
|
|
|
drm_mode_set_name(mode);
|
|
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
connector->display_info.width_mm = 64;
|
|
connector->display_info.height_mm = 129;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static const struct drm_panel_funcs lcm_drm_funcs = {
|
|
.disable = lcm_disable,
|
|
.unprepare = lcm_unprepare,
|
|
.prepare = lcm_prepare,
|
|
.enable = lcm_enable,
|
|
.get_modes = lcm_get_modes,
|
|
};
|
|
|
|
static int lcm_probe(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct device *dev = &dsi->dev;
|
|
struct lcm *ctx;
|
|
int ret;
|
|
struct device_node *dsi_node, *remote_node = NULL, *endpoint = NULL;
|
|
|
|
dsi_node = of_get_parent(dev->of_node);
|
|
if (dsi_node) {
|
|
endpoint = of_graph_get_next_endpoint(dsi_node, NULL);
|
|
if (endpoint) {
|
|
remote_node = of_graph_get_remote_port_parent(endpoint);
|
|
if (!remote_node) {
|
|
pr_info("No panel connected,skip probe lcm\n");
|
|
return -ENODEV;
|
|
}
|
|
pr_info("device node name:%s\n", remote_node->name);
|
|
}
|
|
}
|
|
if (remote_node != dev->of_node) {
|
|
pr_info("%s+ skip probe due to not current lcm\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ctx = devm_kzalloc(dev, sizeof(struct lcm), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
mipi_dsi_set_drvdata(dsi, ctx);
|
|
|
|
ctx->dev = dev;
|
|
dsi->lanes = 4;
|
|
dsi->format = MIPI_DSI_FMT_RGB888;
|
|
dsi->mode_flags = MIPI_DSI_MODE_LPM |
|
|
MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_CLOCK_NON_CONTINUOUS;
|
|
|
|
ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
|
|
if (IS_ERR(ctx->reset_gpio)) {
|
|
dev_info(dev, "%s: cannot get reset-gpios %ld\n",
|
|
__func__, PTR_ERR(ctx->reset_gpio));
|
|
return PTR_ERR(ctx->reset_gpio);
|
|
}
|
|
devm_gpiod_put(dev, ctx->reset_gpio);
|
|
|
|
ctx->prepared = true;
|
|
ctx->enabled = true;
|
|
|
|
drm_panel_init(&ctx->panel, dev, &lcm_drm_funcs, DRM_MODE_CONNECTOR_DSI);
|
|
ctx->panel.dev = dev;
|
|
ctx->panel.funcs = &lcm_drm_funcs;
|
|
|
|
drm_panel_add(&ctx->panel);
|
|
|
|
ret = mipi_dsi_attach(dsi);
|
|
if (ret < 0)
|
|
drm_panel_remove(&ctx->panel);
|
|
|
|
#if defined(CONFIG_MTK_PANEL_EXT)
|
|
mtk_panel_tch_handle_reg(&ctx->panel);
|
|
ret = mtk_panel_ext_create(dev, &ext_params, &ext_funcs, &ctx->panel);
|
|
if (ret < 0)
|
|
return ret;
|
|
#endif
|
|
|
|
pr_info("%s-s6e3fc3\n", __func__);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int lcm_remove(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct lcm *ctx = mipi_dsi_get_drvdata(dsi);
|
|
|
|
mipi_dsi_detach(dsi);
|
|
drm_panel_remove(&ctx->panel);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id lcm_of_match[] = {
|
|
{ .compatible = "s6e3fc3,s2dos15,cmd", },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, lcm_of_match);
|
|
|
|
static struct mipi_dsi_driver lcm_driver = {
|
|
.probe = lcm_probe,
|
|
.remove = lcm_remove,
|
|
.driver = {
|
|
.name = "panel-s6e3fc3-s2dos15-cmd",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = lcm_of_match,
|
|
},
|
|
};
|
|
|
|
module_mipi_dsi_driver(lcm_driver);
|
|
|
|
MODULE_AUTHOR("Rio Moon <Rio.Moon@mediatek.com>");
|
|
MODULE_DESCRIPTION("s6e3fc3 FHDP CMD LCD Panel Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
|