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https://github.com/physwizz/a155-U-u1.git
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60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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#ifndef _CC_LLI_DEFS_H_
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#define _CC_LLI_DEFS_H_
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#include <linux/types.h>
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/* Max DLLI size
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* AKA CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE
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*/
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#define DLLI_SIZE_BIT_SIZE 0x18
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#define CC_MAX_MLLI_ENTRY_SIZE 0xFFFF
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#define LLI_MAX_NUM_OF_DATA_ENTRIES 128
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#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 8
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#define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */
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#define MAX_NUM_OF_BUFFERS_IN_MLLI 4
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#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \
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(2 * LLI_MAX_NUM_OF_DATA_ENTRIES + \
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LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)
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/* Size of entry */
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#define LLI_ENTRY_WORD_SIZE 2
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#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32))
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/* Word0[31:0] = ADDR[31:0] */
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#define LLI_WORD0_OFFSET 0
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#define LLI_LADDR_BIT_OFFSET 0
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#define LLI_LADDR_BIT_SIZE 32
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/* Word1[31:16] = ADDR[47:32]; Word1[15:0] = SIZE */
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#define LLI_WORD1_OFFSET 1
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#define LLI_SIZE_BIT_OFFSET 0
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#define LLI_SIZE_BIT_SIZE 16
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#define LLI_HADDR_BIT_OFFSET 16
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#define LLI_HADDR_BIT_SIZE 16
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#define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET)
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#define LLI_HADDR_MASK GENMASK( \
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(LLI_HADDR_BIT_OFFSET + LLI_HADDR_BIT_SIZE - 1),\
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LLI_HADDR_BIT_OFFSET)
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static inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr)
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{
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lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK;
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lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 32));
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#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
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}
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static inline void cc_lli_set_size(u32 *lli_p, u16 size)
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{
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lli_p[LLI_WORD1_OFFSET] &= ~LLI_SIZE_MASK;
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lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_SIZE_MASK, size);
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}
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#endif /*_CC_LLI_DEFS_H_*/
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