mirror of
https://github.com/physwizz/a155-U-u1.git
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427 lines
10 KiB
C
427 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/time64.h>
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#include <linux/timekeeping.h>
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#include <linux/sched/clock.h>
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#include "clk-mtk.h"
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#include "clk-mux.h"
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static unsigned long long profile_time[4];
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static bool is_registered;
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static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_mux, hw);
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}
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static int mtk_clk_mux_enable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = BIT(mux->data->gate_shift);
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return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
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mask, ~mask);
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}
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static void mtk_clk_mux_disable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = BIT(mux->data->gate_shift);
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regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
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}
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static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_write(mux->regmap, mux->data->clr_ofs,
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BIT(mux->data->gate_shift));
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/*
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* If mux setting restore after vcore resume, it will
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* not be effective yet. Set the update bit to ensure the mux gets
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* updated.
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*/
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regmap_write(mux->regmap, mux->data->upd_ofs,
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BIT(mux->data->upd_shift));
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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regmap_write(mux->regmap, mux->data->set_ofs,
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BIT(mux->data->gate_shift));
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}
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static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val = 0;
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if (!is_registered)
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return 0;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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return (val & BIT(mux->data->gate_shift)) == 0;
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}
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static int mtk_clk_hwv_mux_is_enabled(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val = 0;
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if (!is_registered)
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return 0;
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regmap_read(mux->hwv_regmap, mux->data->hwv_set_ofs, &val);
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return (val & BIT(mux->data->gate_shift)) != 0;
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}
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static int mtk_clk_hwv_mux_is_done(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val = 0;
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regmap_read(mux->hwv_regmap, mux->data->hwv_sta_ofs, &val);
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return (val & BIT(mux->data->gate_shift)) != 0;
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}
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static int mtk_clk_hwv_mux_enable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val, val2;
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int i = 0, j = 0;
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profile_time[2] = 0;
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profile_time[3] = 0;
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/* dummy read to clr idle signal of hw voter bus */
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regmap_read(mux->hwv_regmap, mux->data->hwv_set_ofs, &val);
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regmap_write(mux->hwv_regmap, mux->data->hwv_set_ofs,
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BIT(mux->data->gate_shift));
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profile_time[0] = sched_clock();
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while (!mtk_clk_hwv_mux_is_enabled(hw)) {
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if (i < MTK_WAIT_HWV_PREPARE_CNT)
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udelay(MTK_WAIT_HWV_PREPARE_US);
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else
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goto hwv_prepare_fail;
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i++;
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}
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profile_time[1] = sched_clock();
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i = 0;
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while (1) {
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regmap_read(mux->hwv_regmap, mux->data->hwv_sta_ofs, &val);
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if ((profile_time[2] == 0) && (val & BIT(mux->data->gate_shift)) != 0)
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profile_time[2] = sched_clock();
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else {
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regmap_read(mux->regmap, mux->data->mux_ofs, &val2);
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if ((val2 & BIT(mux->data->gate_shift)) == 0) {
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profile_time[3] = sched_clock();
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break;
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} else if (j > MTK_WAIT_HWV_STA_CNT)
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goto hwv_sta_fail;
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else
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j++;
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}
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if (i < MTK_WAIT_HWV_DONE_CNT && j < MTK_WAIT_HWV_STA_CNT)
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udelay(MTK_WAIT_HWV_DONE_US);
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else
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goto hwv_done_fail;
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i++;
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}
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return 0;
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hwv_sta_fail:
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mtk_clk_notify(mux->regmap, mux->hwv_regmap, NULL,
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mux->data->mux_ofs, (mux->data->hwv_set_ofs / MTK_HWV_ID_OFS),
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mux->data->gate_shift, CLK_EVT_LONG_BUS_LATENCY);
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hwv_done_fail:
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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regmap_read(mux->hwv_regmap, mux->data->hwv_sta_ofs, &val2);
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pr_err("%s mux enable timeout(%x %x)\n", clk_hw_get_name(hw), val, val2);
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hwv_prepare_fail:
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regmap_read(mux->regmap, mux->data->hwv_sta_ofs, &val);
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pr_err("%s mux prepare timeout(%x)\n", clk_hw_get_name(hw), val);
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for (i = 0; i < 4; i++)
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pr_err("[%d]%lld us", i, profile_time[i]);
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mtk_clk_notify(mux->regmap, mux->hwv_regmap, NULL,
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mux->data->mux_ofs, (mux->data->hwv_set_ofs / MTK_HWV_ID_OFS),
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mux->data->gate_shift, CLK_EVT_HWV_CG_TIMEOUT);
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return -EBUSY;
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}
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static void mtk_clk_hwv_mux_disable(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val;
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int i = 0;
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/* dummy read to clr idle signal of hw voter bus */
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regmap_read(mux->hwv_regmap, mux->data->hwv_clr_ofs, &val);
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regmap_write(mux->hwv_regmap, mux->data->hwv_clr_ofs,
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BIT(mux->data->gate_shift));
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while (mtk_clk_hwv_mux_is_enabled(hw)) {
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if (i < MTK_WAIT_HWV_PREPARE_CNT)
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udelay(MTK_WAIT_HWV_PREPARE_US);
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else
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goto hwv_prepare_fail;
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i++;
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}
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i = 0;
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while (!mtk_clk_hwv_mux_is_done(hw)) {
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if (i < MTK_WAIT_HWV_DONE_CNT)
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udelay(MTK_WAIT_HWV_DONE_US);
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else
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goto hwv_done_fail;
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i++;
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}
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return;
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hwv_done_fail:
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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pr_err("%s mux disable timeout(%dus)(%x)\n", clk_hw_get_name(hw),
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i * MTK_WAIT_HWV_DONE_US, val);
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hwv_prepare_fail:
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pr_err("%s mux unprepare timeout(%dus)\n", clk_hw_get_name(hw),
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i * MTK_WAIT_HWV_PREPARE_US);
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mtk_clk_notify(mux->regmap, mux->hwv_regmap, clk_hw_get_name(hw),
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mux->data->mux_ofs, (mux->data->hwv_set_ofs / MTK_HWV_ID_OFS),
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mux->data->gate_shift, CLK_EVT_HWV_CG_TIMEOUT);
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return;
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}
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static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val = 0;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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val = (val >> mux->data->mux_shift) & mask;
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return val;
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}
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static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
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index << mux->data->mux_shift);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val = 0, orig = 0;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
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val = (orig & ~(mask << mux->data->mux_shift))
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| (index << mux->data->mux_shift);
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if (val != orig) {
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regmap_write(mux->regmap, mux->data->clr_ofs,
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mask << mux->data->mux_shift);
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regmap_write(mux->regmap, mux->data->set_ofs,
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index << mux->data->mux_shift);
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if (mux->data->upd_shift >= 0)
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regmap_write(mux->regmap, mux->data->upd_ofs,
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BIT(mux->data->upd_shift));
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}
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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const struct clk_ops mtk_mux_ops = {
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_lock,
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};
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EXPORT_SYMBOL(mtk_mux_ops);
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const struct clk_ops mtk_mux_clr_set_upd_ops = {
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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EXPORT_SYMBOL(mtk_mux_clr_set_upd_ops);
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const struct clk_ops mtk_mux_gate_ops = {
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.enable = mtk_clk_mux_enable,
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.disable = mtk_clk_mux_disable,
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.is_enabled = mtk_clk_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_lock,
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};
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EXPORT_SYMBOL(mtk_mux_gate_ops);
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const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
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.enable = mtk_clk_mux_enable_setclr,
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.disable = mtk_clk_mux_disable_setclr,
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.is_enabled = mtk_clk_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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EXPORT_SYMBOL(mtk_mux_gate_clr_set_upd_ops);
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const struct clk_ops mtk_hwv_mux_ops = {
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.enable = mtk_clk_hwv_mux_enable,
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.disable = mtk_clk_hwv_mux_disable,
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.is_enabled = mtk_clk_hwv_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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EXPORT_SYMBOL(mtk_hwv_mux_ops);
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static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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struct regmap *hw_voter_regmap,
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spinlock_t *lock)
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{
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struct mtk_clk_mux *clk_mux;
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struct clk_init_data init = {};
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struct clk *clk;
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clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
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if (!clk_mux)
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return ERR_PTR(-ENOMEM);
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init.name = mux->name;
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init.flags = mux->flags | CLK_SET_RATE_PARENT;
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init.parent_names = mux->parent_names;
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init.num_parents = mux->num_parents;
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init.ops = mux->ops;
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clk_mux->regmap = regmap;
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clk_mux->hwv_regmap = hw_voter_regmap;
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clk_mux->data = mux;
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clk_mux->lock = lock;
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clk_mux->hw.init = &init;
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clk = clk_register(NULL, &clk_mux->hw);
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if (IS_ERR(clk)) {
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kfree(clk_mux);
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return clk;
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}
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return clk;
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}
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_onecell_data *clk_data)
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{
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struct regmap *regmap, *hw_voter_regmap;
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struct clk *clk;
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int i;
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is_registered = false;
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regmap = syscon_node_to_regmap(node);
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if (IS_ERR(regmap)) {
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pr_err("Cannot find regmap for %pOF: %ld\n", node,
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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hw_voter_regmap = syscon_regmap_lookup_by_phandle(node, "hw-voter-regmap");
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if (IS_ERR(hw_voter_regmap))
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hw_voter_regmap = NULL;
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for (i = 0; i < num; i++) {
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const struct mtk_mux *mux = &muxes[i];
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if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
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clk = mtk_clk_register_mux(mux, regmap, hw_voter_regmap, lock);
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if (IS_ERR(clk)) {
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pr_err("Failed to register clk %s: %ld\n",
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mux->name, PTR_ERR(clk));
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continue;
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}
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clk_data->clks[mux->id] = clk;
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}
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}
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is_registered = true;
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return 0;
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}
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EXPORT_SYMBOL(mtk_clk_register_muxes);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("MediaTek MUX");
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MODULE_AUTHOR("MediaTek Inc.");
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