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https://github.com/physwizz/a155-U-u1.git
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96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2020 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs msdc_top_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate msdc_top_clks[] = {
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GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p",
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"aes_msdcfde_sel", 0),
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p",
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"infra_msdc0_src", 1),
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p",
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"infra_msdc1_src", 2),
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GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p",
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"infra_msdc2_src", 3),
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0",
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"axi_sel", 4),
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1",
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"axi_sel", 5),
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2",
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"axi_sel", 6),
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GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg",
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"axi_sel", 7),
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GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8),
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p",
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"infra_msdc0", 9),
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p",
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"infra_msdc1", 10),
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GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p",
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"infra_msdc2", 11),
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GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m",
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"clk26m", 12),
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GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k",
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"clk32k", 13),
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GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi",
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"axi_sel", 14),
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};
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static int clk_mt8192_msdc_top_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_MSDC_TOP_NR_CLK);
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mtk_clk_register_gates(node, msdc_top_clks, ARRAY_SIZE(msdc_top_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id of_match_clk_mt8192_msdc_top[] = {
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{ .compatible = "mediatek,mt8192-msdc_top", },
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{}
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};
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static struct platform_driver clk_mt8192_msdc_top_drv = {
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.probe = clk_mt8192_msdc_top_probe,
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.driver = {
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.name = "clk-mt8192-msdc_top",
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.of_match_table = of_match_clk_mt8192_msdc_top,
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},
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};
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static int __init clk_mt8192_msdc_top_init(void)
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{
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return platform_driver_register(&clk_mt8192_msdc_top_drv);
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}
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static void __exit clk_mt8192_msdc_top_exit(void)
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{
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platform_driver_unregister(&clk_mt8192_msdc_top_drv);
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}
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arch_initcall(clk_mt8192_msdc_top_init);
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module_exit(clk_mt8192_msdc_top_exit);
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MODULE_LICENSE("GPL");
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