mirror of
https://github.com/physwizz/a155-U-u1.git
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532 lines
12 KiB
C
532 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Yu-Chang Wang <Yu-Chang.Wang@mediatek.com>
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include "clk-fhctl.h"
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#include "clk-fhctl-pll.h"
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#include "clk-fhctl-util.h"
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#include <linux/soc/mediatek/mtk_tinysys_ipi.h>
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#include <include/mcupm_ipi_id.h>
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#define FHCTL_TARGET FHCTL_MCUPM
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#define IPI_TIMEOUT_MS 10
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#define IPI_TIMEOUT_LONG_MS 3000
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struct match {
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char *name;
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struct fh_hdlr *hdlr;
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int (*init)(struct pll_dts *array
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, struct match *match);
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};
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struct id_map {
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char *name;
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int base;
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};
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struct hdlr_data_v1 {
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struct pll_dts *array;
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spinlock_t *lock;
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struct fh_pll_domain *domain;
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u8 tr_id;
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void __iomem *reg_tr;
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struct id_map *map;
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};
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struct freqhopping_ioctl {
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unsigned int pll_id;
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struct freqhopping_ssc {
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unsigned int idx_pattern; /* idx_pattern: Deprecated Field */
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unsigned int dt;
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unsigned int df;
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unsigned int upbnd;
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unsigned int lowbnd;
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unsigned int dds; /* dds: Deprecated Field */
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} ssc_setting; /* used only when user-define */
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int result;
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};
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struct fhctl_ipi_data {
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unsigned int cmd;
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union {
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struct freqhopping_ioctl fh_ctl;
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unsigned int args[8];
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} u;
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};
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enum FH_DEVCTL_CMD_ID {
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FH_DCTL_CMD_SSC_ENABLE = 0x1004,
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FH_DCTL_CMD_SSC_DISABLE = 0x1005,
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FH_DCTL_CMD_GENERAL_DFS = 0x1006,
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FH_DCTL_CMD_ARM_DFS = 0x1007,
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FH_DCTL_CMD_SSC_TBL_CONFIG = 0x100A,
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FH_DCTL_CMD_PLL_PAUSE = 0x100E,
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FH_DCTL_CMD_MAX,
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FH_DBG_CMD_TR_BEGIN64_LOW = 0x2001,
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FH_DBG_CMD_TR_BEGIN64_HIGH = 0x2002,
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FH_DBG_CMD_TR_END64_LOW = 0x2003,
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FH_DBG_CMD_TR_END64_HIGH = 0x2004,
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FH_DBG_CMD_TR_ID = 0x2005,
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FH_DBG_CMD_TR_VAL = 0x2006,
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FH_DBG_CMD_TR_BEGIN32 = 0x2007,
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FH_DBG_CMD_TR_END32 = 0x2008,
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};
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#define FHCTL_D_LEN (sizeof(struct fhctl_ipi_data)/\
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sizeof(unsigned int))
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static unsigned int ack_data;
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static int id_to_mcupm(struct id_map *map, char *domain, int fh_id) {
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if (!map)
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return fh_id;
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while ( map->name != NULL ) {
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if (strcmp(map->name,
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domain) == 0) {
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return (map->base + fh_id);
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}
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map++;
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}
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return fh_id;
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}
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static void ipi_get_data(unsigned int cmd)
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{
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struct fhctl_ipi_data ipi_data;
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int ret;
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FHDBG("cmd<%x>\n", cmd);
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memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
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ipi_data.cmd = cmd;
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/* 3 sec for debug */
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ret = mtk_ipi_send_compl(get_mcupm_ipidev(), CH_S_FHCTL,
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IPI_SEND_POLLING, &ipi_data,
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FHCTL_D_LEN, 3000);
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FHDBG("ret<%d>, ack_data<%x>\n",
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ret, ack_data);
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}
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static void dump_hw(struct fh_pll_regs *regs,
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struct fh_pll_data *data)
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{
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FHDBG("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
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readl(regs->reg_hp_en), readl(regs->reg_clk_con),
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readl(regs->reg_slope0), readl(regs->reg_slope1));
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FHDBG("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
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readl(regs->reg_cfg), readl(regs->reg_updnlmt),
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readl(regs->reg_dds), readl(regs->reg_dvfs),
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readl(regs->reg_mon));
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FHDBG("pcw<%x>\n",
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readl(regs->reg_con_pcw));
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}
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static int mcupm_hopping_v1(void *priv_data, char *domain_name, int fh_id,
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unsigned int new_dds, int postdiv)
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{
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int ret;
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struct fhctl_ipi_data ipi_data;
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struct hdlr_data_v1 *d = (struct hdlr_data_v1 *)priv_data;
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spinlock_t *lock = d->lock;
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ktime_t ktime;
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u64 time_ns;
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u8 tr_id_local;
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struct fh_pll_domain *domain;
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struct fh_pll_regs *regs;
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struct fh_pll_data *data;
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unsigned int con_pcw;
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bool has_err = false;
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unsigned long flags = 0;
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spin_lock_irqsave(lock, flags);
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memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
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ipi_data.cmd = FH_DCTL_CMD_GENERAL_DFS;
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ipi_data.u.args[0] = id_to_mcupm(d->map, domain_name, fh_id);
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ipi_data.u.args[1] = new_dds;
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ipi_data.u.args[2] = postdiv;
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ktime = ktime_get();
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time_ns = ktime_to_ns(ktime);
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d->tr_id ^= (((u8)time_ns) | 0x1);
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ipi_data.u.args[7] = d->tr_id;
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tr_id_local = d->tr_id;
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/* make sure tr_id_local is set before send ipi */
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mb();
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ret = mtk_ipi_send_compl(get_mcupm_ipidev(), CH_S_FHCTL,
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IPI_SEND_POLLING, &ipi_data,
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FHCTL_D_LEN, IPI_TIMEOUT_MS);
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domain = d->domain;
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regs = &domain->regs[fh_id];
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data = &domain->data[fh_id];
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con_pcw = readl(regs->reg_con_pcw);
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con_pcw &= data->dds_mask;
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if (con_pcw != new_dds)
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has_err |= true;
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if (ret != 0)
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has_err |= true;
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if (ack_data != d->tr_id)
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has_err |= true;
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if (has_err) {
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u32 val;
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FHDBG("---------------------------\n");
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FHDBG("domain<%s>, fh_id<%d>\n",
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domain_name, fh_id);
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FHDBG("ret<%d>, ack<%x>, tr<%x>\n",
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ret, ack_data, d->tr_id);
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FHDBG("con_pcw<%x>, new_dds<%x>\n",
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con_pcw, new_dds);
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/* dump HW */
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dump_hw(regs, data);
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/* tr/time via HW */
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FHDBG("time_ns<%lx>\n", time_ns);
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if (d->reg_tr) {
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val = readl(d->reg_tr);
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FHDBG("reg_tr<%x>\n", val);
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}
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/* time via SW */
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ipi_get_data(FH_DBG_CMD_TR_BEGIN64_LOW);
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ipi_get_data(FH_DBG_CMD_TR_BEGIN64_HIGH);
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ipi_get_data(FH_DBG_CMD_TR_END64_LOW);
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ipi_get_data(FH_DBG_CMD_TR_END64_HIGH);
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ipi_get_data(FH_DBG_CMD_TR_ID);
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ipi_get_data(FH_DBG_CMD_TR_VAL);
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ipi_get_data(FH_DBG_CMD_TR_BEGIN32);
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ipi_get_data(FH_DBG_CMD_TR_END32);
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FHDBG("tr_id_local<%x>\n",
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++tr_id_local);
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FHDBG("---------------------------\n");
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/* notify user that err */
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mb();
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notify_err();
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ret = -1;
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} else
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ret = 0;
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spin_unlock_irqrestore(lock, flags);
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return ret;
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}
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static int mcupm_ssc_enable_v1(void *priv_data,
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char *domain_name, int fh_id, int rate)
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{
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struct freqhopping_ioctl fh_ctl;
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struct fhctl_ipi_data ipi_data;
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int ret;
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struct hdlr_data_v1 *d = (struct hdlr_data_v1 *)priv_data;
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spinlock_t *lock = d->lock;
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struct pll_dts *array = d->array;
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struct fh_pll_data *data = d->domain->data;
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unsigned long flags = 0;
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spin_lock_irqsave(lock, flags);
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FHDBG("rate<%d>\n", rate);
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fh_ctl.pll_id = id_to_mcupm(d->map, domain_name, fh_id);
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fh_ctl.result = 0;
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fh_ctl.ssc_setting.dt = data->dt_val;
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fh_ctl.ssc_setting.df = data->df_val;
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fh_ctl.ssc_setting.upbnd = 0;
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fh_ctl.ssc_setting.lowbnd = rate;
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memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
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memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
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sizeof(struct freqhopping_ioctl));
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ipi_data.cmd = FH_DCTL_CMD_SSC_ENABLE;
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ret = mtk_ipi_send_compl(get_mcupm_ipidev(), CH_S_FHCTL,
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IPI_SEND_POLLING, &ipi_data,
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FHCTL_D_LEN, IPI_TIMEOUT_LONG_MS);
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FHDBG("ret<%d>\n", ret);
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array->ssc_rate = rate;
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spin_unlock_irqrestore(lock, flags);
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return 0;
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}
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static int mcupm_ssc_disable_v1(void *priv_data,
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char *domain_name, int fh_id)
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{
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struct freqhopping_ioctl fh_ctl;
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struct fhctl_ipi_data ipi_data;
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int ret;
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struct hdlr_data_v1 *d = (struct hdlr_data_v1 *)priv_data;
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spinlock_t *lock = d->lock;
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struct pll_dts *array = d->array;
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unsigned long flags = 0;
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spin_lock_irqsave(lock, flags);
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FHDBG("\n");
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fh_ctl.pll_id = id_to_mcupm(d->map, domain_name, fh_id);
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fh_ctl.result = 0;
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memset(&ipi_data, 0, sizeof(struct fhctl_ipi_data));
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memcpy(&ipi_data.u.fh_ctl, &fh_ctl,
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sizeof(struct freqhopping_ioctl));
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ipi_data.cmd = FH_DCTL_CMD_SSC_DISABLE;
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ret = mtk_ipi_send_compl(get_mcupm_ipidev(), CH_S_FHCTL,
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IPI_SEND_POLLING, &ipi_data,
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FHCTL_D_LEN, IPI_TIMEOUT_LONG_MS);
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FHDBG("ret<%d>\n", ret);
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array->ssc_rate = 0;
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spin_unlock_irqrestore(lock, flags);
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return 0;
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}
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static int mcupm_init_v1(struct pll_dts *array, struct match *match)
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{
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static bool ipi_inited;
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static DEFINE_SPINLOCK(lock);
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struct hdlr_data_v1 *priv_data, *match_data;
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struct fh_hdlr *hdlr;
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FHDBG("array<%lx>, %s\n",
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(unsigned long)array,
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array->pll_name);
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if (!ipi_inited) {
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int ret;
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ret = mtk_ipi_register(get_mcupm_ipidev(), CH_S_FHCTL, NULL,
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NULL, (void *)&ack_data);
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if (ret) {
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FHDBG("[MCUPM] ipi_register fail, ret %d\n", ret);
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return -1;
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}
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ipi_inited = true;
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FHDBG("\n");
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}
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priv_data = kzalloc(sizeof(*priv_data), GFP_KERNEL);
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hdlr = kzalloc(sizeof(*hdlr), GFP_KERNEL);
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init_fh_domain(array->domain,
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array->comp,
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array->fhctl_base,
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array->apmixed_base);
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priv_data->array = array;
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priv_data->lock = &lock;
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priv_data->domain = get_fh_domain(array->domain);
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match_data = match->hdlr->data;
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if (match_data->reg_tr) {
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priv_data->reg_tr = array->fhctl_base
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+ (unsigned long)match_data->reg_tr;
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}
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priv_data->map = match_data->map;
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/* hook to array */
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hdlr->data = priv_data;
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hdlr->ops = match->hdlr->ops;
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/* hook hdlr to array is the last step */
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mb();
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array->hdlr = hdlr;
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/* do SSC */
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if (array->ssc_rate) {
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struct fh_hdlr *hdlr;
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hdlr = array->hdlr;
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hdlr->ops->ssc_enable(hdlr->data,
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array->domain,
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array->fh_id,
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array->ssc_rate);
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}
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return 0;
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}
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static struct fh_operation mcupm_ops_v1 = {
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.hopping = mcupm_hopping_v1,
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.ssc_enable = mcupm_ssc_enable_v1,
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.ssc_disable = mcupm_ssc_disable_v1,
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};
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struct hdlr_data_v1 hdlr_data_6853 = {
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.reg_tr = (void __iomem *)(0xC8 + 0x4),
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};
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static struct fh_hdlr mcupm_hdlr_6853 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6853,
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};
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static struct match mt6853_match = {
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.name = "mediatek,mt6853-fhctl",
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.hdlr = &mcupm_hdlr_6853,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6855 = {
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.reg_tr = (void __iomem *)(0x90), /* MEMPL Up/Down Limit */
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};
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static struct fh_hdlr mcupm_hdlr_6855 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6855,
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};
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static struct match mt6855_match = {
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.name = "mediatek,mt6855-fhctl",
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.hdlr = &mcupm_hdlr_6855,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6879 = {
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.reg_tr = (void __iomem *)(0x90), /* MEMPL Up/Down Limit */
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};
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static struct fh_hdlr mcupm_hdlr_6879 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6879,
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};
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static struct match mt6879_match = {
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.name = "mediatek,mt6879-fhctl",
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.hdlr = &mcupm_hdlr_6879,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6877 = {
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.reg_tr = (void __iomem *)(0x90), /* MEMPL Up/Down Limit */
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};
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static struct fh_hdlr mcupm_hdlr_6877 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6877,
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};
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static struct match mt6877_match = {
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.name = "mediatek,mt6877-fhctl",
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.hdlr = &mcupm_hdlr_6877,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6873 = {
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.reg_tr = NULL,
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};
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static struct fh_hdlr mcupm_hdlr_6873 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6873,
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};
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static struct match mt6873_match = {
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.name = "mediatek,mt6873-fhctl",
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.hdlr = &mcupm_hdlr_6873,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6885 = {
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.reg_tr = NULL,
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};
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static struct fh_hdlr mcupm_hdlr_6885 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6885,
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};
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static struct match mt6885_match = {
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.name = "mediatek,mt6885-fhctl",
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.hdlr = &mcupm_hdlr_6885,
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.init = &mcupm_init_v1,
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};
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struct hdlr_data_v1 hdlr_data_6895 = {
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.reg_tr = (void __iomem *)(0x90), /* MEMPL Up/Down Limit */
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};
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static struct fh_hdlr mcupm_hdlr_6895 = {
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.ops = &mcupm_ops_v1,
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.data = &hdlr_data_6895,
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};
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static struct match mt6895_match = {
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.name = "mediatek,mt6895-fhctl",
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.hdlr = &mcupm_hdlr_6895,
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.init = &mcupm_init_v1,
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};
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static struct id_map map_6983[] = {
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{"mcu0", 1000},
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{"mcu1", 2000},
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{"mcu2", 3000},
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{"mcu3", 4000},
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{}
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};
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struct hdlr_data_v1 hdlr_data_6983 = {
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.reg_tr = NULL,
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.map = map_6983,
|
|
};
|
|
static struct fh_hdlr mcupm_hdlr_6983 = {
|
|
.ops = &mcupm_ops_v1,
|
|
.data = &hdlr_data_6983,
|
|
};
|
|
static struct match mt6983_match = {
|
|
.name = "mediatek,mt6983-fhctl",
|
|
.hdlr = &mcupm_hdlr_6983,
|
|
.init = &mcupm_init_v1,
|
|
};
|
|
|
|
static struct match *matches[] = {
|
|
&mt6853_match,
|
|
&mt6855_match,
|
|
&mt6879_match,
|
|
&mt6877_match,
|
|
&mt6873_match,
|
|
&mt6885_match,
|
|
&mt6895_match,
|
|
&mt6983_match,
|
|
NULL,
|
|
};
|
|
|
|
int fhctl_mcupm_init(struct pll_dts *array)
|
|
{
|
|
int i;
|
|
int num_pll;
|
|
struct match **match;
|
|
|
|
FHDBG("\n");
|
|
match = matches;
|
|
num_pll = array->num_pll;
|
|
|
|
/* find match by compatible */
|
|
while (*match != NULL) {
|
|
char *comp = (*match)->name;
|
|
char *target = array->comp;
|
|
|
|
if (strcmp(comp,
|
|
target) == 0) {
|
|
break;
|
|
}
|
|
match++;
|
|
}
|
|
|
|
if (*match == NULL) {
|
|
FHDBG("no match!\n");
|
|
return -1;
|
|
}
|
|
|
|
/* init flow for every pll */
|
|
for (i = 0; i < num_pll ; i++, array++) {
|
|
char *method = array->method;
|
|
|
|
if (strcmp(method,
|
|
FHCTL_TARGET) == 0) {
|
|
(*match)->init(array, *match);
|
|
}
|
|
}
|
|
|
|
FHDBG("\n");
|
|
return 0;
|
|
}
|