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a155-U-u1/kernel-5.10/arch/arm64/boot/dts/mediatek/mt6873.dtsi
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2024-03-11 06:53:12 +11:00

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2020 MediaTek Inc.
* Author: Seiya Wang <seiya.wang@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt6873-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt6873-pinfunc.h>
#include <dt-bindings/power/mt6873-power.h>
#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
#include <dt-bindings/gce/mt6873-gce.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/interconnect/mtk,mmqos.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/mediatek,boot-mode.h>
/ {
model = "MediaTek MT6873";
compatible = "mediatek,mt6873";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
ovl0 = &disp_ovl0;
ovl3 = &disp_ovl0_2l;
ovl5 = &disp_ovl2_2l;
rdma0 = &disp_rdma0;
rdma4 = &disp_rdma4;
dsi0 = &dsi0;
};
/* ATF logger */
atf_logger {
compatible = "mediatek,atf_logger";
};
/* chosen */
chosen: chosen {
bootargs = "console=tty0 root=/dev/ram vmalloc=400M \
rcupdate.rcu_expedited=1 swiotlb=noforce \
firmware_class.path=/vendor/firmware page_owner=on \
loop.max_part=7 snd-usb-audio.use_vmalloc=0";
kaslr-seed = <0 0>;
};
memory {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
clocks {
clk_null: clk_null {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
clk26m: clk26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk13m: clk13m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
};
clk12m: clk12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk32k: clk32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp0 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <1000000>;
opp-level = <0>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp1 {
opp-hz = /bits/ 64 <1895000000>;
opp-microvolt = <968750>;
opp-level = <1>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp2 {
opp-hz = /bits/ 64 <1833000000>;
opp-microvolt = <943750>;
opp-level = <2>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp3 {
opp-hz = /bits/ 64 <1750000000>;
opp-microvolt = <918750>;
opp-level = <3>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp4 {
opp-hz = /bits/ 64 <1666000000>;
opp-microvolt = <893750>;
opp-level = <4>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp5 {
opp-hz = /bits/ 64 <1583000000>;
opp-microvolt = <862500>;
opp-level = <5>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp6 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <837500>;
opp-level = <6>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp7 {
opp-hz = /bits/ 64 <1393000000>;
opp-microvolt = <806250>;
opp-level = <7>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp8 {
opp-hz = /bits/ 64 <1287000000>;
opp-microvolt = <775000>;
opp-level = <8>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp9 {
opp-hz = /bits/ 64 <1181000000>;
opp-microvolt = <750000>;
opp-level = <9>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp10 {
opp-hz = /bits/ 64 <1101000000>;
opp-microvolt = <725000>;
opp-level = <10>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp11 {
opp-hz = /bits/ 64 <1021000000>;
opp-microvolt = <706250>;
opp-level = <11>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp12 {
opp-hz = /bits/ 64 <889000000>;
opp-microvolt = <668750>;
opp-level = <12>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp13 {
opp-hz = /bits/ 64 <809000000>;
opp-microvolt = <643750>;
opp-level = <13>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp14 {
opp-hz = /bits/ 64 <729000000>;
opp-microvolt = <625000>;
opp-level = <14>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp15 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <600000>;
opp-level = <15>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp16 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <600000>;
opp-level = <16>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp0 {
opp-hz = /bits/ 64 <2500000000>;
opp-microvolt = <1000000>;
opp-level = <0>;
opp-supported-hw = <0x200 0xf0 0xf0>;
};
opp1 {
opp-hz = /bits/ 64 <2375000000>;
opp-microvolt = <968750>;
opp-level = <1>;
opp-supported-hw = <0x200 0xf0 0xf0>;
};
opp2 {
opp-hz = /bits/ 64 <2300000000>;
opp-microvolt = <943750>;
opp-level = <2>;
opp-supported-hw = <0x200 0xf0 0xf0>;
};
opp3 {
opp-hz = /bits/ 64 <2250000000>;
opp-microvolt = <931250>;
opp-level = <3>;
opp-supported-hw = <0x200 0xf0 0xf0>;
};
opp4 {
opp-hz = /bits/ 64 <2200000000>;
opp-microvolt = <918750>;
opp-level = <4>;
opp-supported-hw = <0x300 0xf0 0xf0>;
};
opp5 {
opp-hz = /bits/ 64 <2100000000>;
opp-microvolt = <893750>;
opp-level = <5>;
opp-supported-hw = <0x300 0xf0 0xf0>;
};
opp6 {
opp-hz = /bits/ 64 <2025000000>;
opp-microvolt = <868750>;
opp-level = <6>;
opp-supported-hw = <0x300 0xf0 0xf0>;
};
opp7 {
opp-hz = /bits/ 64 <1975000000>;
opp-microvolt = <856250>;
opp-level = <7>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp8 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <837500>;
opp-level = <8>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp9 {
opp-hz = /bits/ 64 <1831000000>;
opp-microvolt = <825000>;
opp-level = <9>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp10 {
opp-hz = /bits/ 64 <1762000000>;
opp-microvolt = <806250>;
opp-level = <10>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp11 {
opp-hz = /bits/ 64 <1659000000>;
opp-microvolt = <787500>;
opp-level = <11>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp12 {
opp-hz = /bits/ 64 <1487000000>;
opp-microvolt = <750000>;
opp-level = <12>;
opp-supported-hw = <0x311 0xf0 0xf0>;
};
opp13 {
opp-hz = /bits/ 64 <1384000000>;
opp-microvolt = <725000>;
opp-level = <13>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp14 {
opp-hz = /bits/ 64 <1281000000>;
opp-microvolt = <706250>;
opp-level = <14>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp15 {
opp-hz = /bits/ 64 <1143000000>;
opp-microvolt = <675000>;
opp-level = <15>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp16 {
opp-hz = /bits/ 64 <1075000000>;
opp-microvolt = <662500>;
opp-level = <16>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp17 {
opp-hz = /bits/ 64 <1006000000>;
opp-microvolt = <643750>;
opp-level = <17>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp18 {
opp-hz = /bits/ 64 <903000000>;
opp-microvolt = <625000>;
opp-level = <18>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
opp19 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <600000>;
opp-level = <19>;
opp-supported-hw = <0x311 0xf1 0xf1>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@000 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <365>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu1: cpu@001 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <365>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu2: cpu@002 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <365>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu3: cpu@003 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <365>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0400>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0500>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0600>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0700>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff
&system_mem &system_pll &system_bus
&s2idle>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "arm,psci";
cpuoff_l: cpuoff_l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <1600>;
};
cpuoff_b: cpuoff_b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010002>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <1400>;
};
clusteroff_l: clusteroff_l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010101>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <250>;
min-residency-us = <2100>;
};
clusteroff_b: clusteroff_b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010102>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <250>;
min-residency-us = <1900>;
};
mcusysoff: mcusysoff {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010701>;
local-timer-stop;
entry-latency-us = <450>;
exit-latency-us = <600>;
min-residency-us = <4000>;
};
system_mem: system_mem {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010f01>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <850>;
min-residency-us = <4000>;
};
system_pll: system_pll {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010f02>;
local-timer-stop;
entry-latency-us = <800>;
exit-latency-us = <950>;
min-residency-us = <4000>;
};
system_bus: system_bus {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010f03>;
local-timer-stop;
entry-latency-us = <1300>;
exit-latency-us = <2800>;
min-residency-us = <4000>;
};
s2idle: s2idle {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01011f01>;
local-timer-stop;
entry-latency-us = <10000>;
exit-latency-us = <10000>;
min-residency-us = <4294967295>;
};
};
};
gic: interrupt-controller {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <2>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, // distributor
<0 0x0c040000 0 0x200000>; // redistributor
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
};
};
dcm: dcm@10001000 {
compatible = "mediatek,mt6873-dcm";
reg = <0 0x10001000 0 0x1000>,
<0 0x10002000 0 0x1000>,
<0 0x10022000 0 0x1000>,
<0 0x10219000 0 0x1000>,
<0 0x10230000 0 0x2000>,
<0 0x10235000 0 0x1000>,
<0 0x10238000 0 0x1000>,
<0 0x10240000 0 0x2000>,
<0 0x10248000 0 0x1000>,
<0 0x10400000 0 0x1000>,
<0 0x11210000 0 0x1000>,
<0 0xc538000 0 0x5000>,
<0 0xc53a800 0 0x1000>;
reg-names = "infracfg_ao",
"infracfg_ao_mem",
"infra_ao_bcrm",
"emi",
"dramc_ch0_top0",
"chn0_emi",
"dramc_ch0_top5",
"dramc_ch1_top0",
"dramc_ch1_top5",
"sspm",
"audio",
"mp_cpusys_top",
"cpccfg_reg";
};
gpio: gpio@10005000 {
compatible = "mediatek,gpio";
reg = <0 0x10005000 0 0x1000>;
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserve-memory-mcupm_share {
compatible = "mediatek,reserve-memory-mcupm_share";
no-map;
status = "okay";
size = <0 0x610000>; /* 6M + 64K */
alignment = <0 0x10000>;
alloc-ranges = <0 0x40000000 0 0x60000000>;
};
reserve-memory-sspm_share {
compatible = "mediatek,reserve-memory-sspm_share";
no-map;
status = "okay";
size = <0 0x510000>; /* 5M + 64K */
alignment = <0 0x10000>;
alloc-ranges = <0 0x40000000 0 0x60000000>;
};
reserve-memory-adsp_share {
compatible = "mediatek,reserve-memory-adsp_share";
no-map;
size = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x40000000>;
alignment = <0 0x10000>; /* EMI 64KB Align */
};
reserve-memory-scp_share {
compatible = "mediatek,reserve-memory-scp_share";
no-map;
size = <0 0x00300000>; /*3 MB share mem size */
alignment = <0 0x1000000>;
alloc-ranges = <0 0x50000000 0 0x40000000>;
};
ssmr_cma_mem: ssmr-reserved-cma_memory {
compatible = "shared-dma-pool";
reusable;
size = <0 0x10000000>;
alignment = <0 0x1000000>;
alloc-range = <0 0xc0000000 0 0x10000000>;
};
consys_mem: consys-reserve-memory {
compatible = "mediatek,consys-reserve-memory";
no-map;
size = <0 0x400000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
wifi_mem: wifi-reserve-memory {
compatible = "shared-dma-pool";
no-map;
size = <0 0x600000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
};
cache_parity {
compatible = "mediatek,mt6873-cache-parity";
arm_dsu_ecc_hwirq = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
};
memory_ssmr_features: memory-ssmr-features {
compatible = "mediatek,memory-ssmr-features";
svp-region-based-size = <0 0x10000000>;
2d_fr-size = <0 0x8000000>;
tui-size = <0 0x4000000>;
wfd-size = <0 0x4000000>;
prot-region-based-size = <0 0x8000000>;
ta-elf-size = <0 0x1000000>;
ta-stack-heap-size = <0 0x6000000>;
sdsp-tee-sharedmem-size = <0 0x1000000>;
sdsp-firmware-size = <0 0x1000000>;
};
ssmr {
compatible = "mediatek,trusted_mem";
memory-region = <&ssmr_cma_mem>;
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
hwrng: hwrng {
compatible = "arm,sec-rng";
methods = "smc";
method-fid = /bits/ 16 <0x26a>;
quality = /bits/ 16 <900>;
};
pwrap: pwrap@10026000 {
compatible = "mediatek,mt6873-pwrap", "syscon";
reg = <0 0x10026000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_PMIC_AP>,
<&infracfg CLK_INFRA_PMIC_TMR>,
<&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>,
<&topckgen CLK_TOP_OSC_D10>;
clock-names = "spi", "wrap", "ulposc", "ulposc_osc";
};
thermal_zones: thermal-zones {
soc_max {
polling-delay = <100>; /* milliseconds */
polling-delay-passive = <5>; /* milliseconds */
thermal-sensors = <&lvts 0>;
sustainable-power = <3000>; /* milliwatts */
trips {
threshold: trip-point@0 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point@1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_max_crit: soc_max_crit@0 {
temperature = <117000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <2048>;
};
map1 {
trip = <&target>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map2 {
trip = <&target>;
cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
cpu_big1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 1>;
};
cpu_big2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 2>;
};
cpu_big3 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 3>;
};
cpu_big4 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 4>;
};
cci1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 5>;
};
cci2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 6>;
};
cpu_little1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 7>;
};
cpu_little2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 8>;
};
apu {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 9>;
};
mlda {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 10>;
};
gpu1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 11>;
};
gpu2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 12>;
};
infra {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 13>;
};
camsys {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 14>;
};
md1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 15>;
};
md2{
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 16>;
};
md3 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 17>;
};
consys {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&consys>;
trips {
consys_crit: consys_crit@0 {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
thermal_ipi: thermal-ipi {
compatible = "mediatek,thermal-ipi";
target-bitmask = <0x2>; /* MCUPM */
};
eemgpu_fsm: eemgpu_fsm@1100b000 {
compatible = "mediatek,eemgpu_fsm";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
eemg-status = <1>;
eemg-initmon-gpu = <0xf>;
eemg-clamp-gpu = <0>;
eemg-offset-gpu = <0xff>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
infracfg = <&infracfg>;
devinfo-idx = <0xc8 0xcc 0xd0 0xd4 0xd8 0xdc 0xe0 0xe4 0xe8
0xec 0xf0 0xf4 0xF8 0xFC 0x100 0x104 0x108 0x10c>;
devinfo-mcl50 = <0x00000001 0x0 0x5a1e242A 0x57142476
0x49172454 0x0 0x0 0x4d152457 0x00000000 0x56ec00dc
0x081800a6 0x6f572444 0x725c244d 0x1b031b03 0x1b031b03
0x00000000 0x1b031b03 0x1b031b03>;
devinfo = <0x0 0x94132424 0xb1e92424 0x42122446 0x63122424 0x0
0x0 0x62122424 0x51152498 0x46ea0098 0x37170054
0xc3990089 0xdc910089 0x1b031b03 0x1b031b03 0x0
0x1b031b03 0x1b031b03>;
devinfo-fake = <1>;
devinfo-fake-ignore = <0x9860>;
golden-temp = <0x1d0>;
golden-temp-mask = <0xff000000>;
golden-temp-default = <50>;
gpu-vb = <0>;
eemg_detectors = "EEMG_DET_GPU", "EEMG_DET_GPU_HI";
EEMG_DET_GPU {
ctrl_id = <0>;
features = <0x2>;
max_freq_khz = <688000>;
VBOOT = <0x38>;
VMAX = <0x60>;
VMIN = <0x114 0x30>;
VMIN-idx = <0x1a 0x1e 0x1a 0x1a>;
eemg_v_base = <40000>;
eemg_step = <625>;
pmic_step = <0>;
pmic_base = <625>;
DETWINDOW = <0xa28>;
DTHI = <0x01>;
DTLO = <0xfe>;
DETMAX = <0xffff>;
AGECONFIG = <0x555555>;
AGEM = <0x0>;
DVTFIXED = <0x1>;
loo_role = <1>;
loo_couple = <1>;
turn_pt = <6>;
VCO = <0x18>;
DCONFIG = <1>;
EEMCTL0 = <0x00540003>;
low_temp_off = <4>;
extra_low_temp_off = <7>;
high_temp_off = <0>;
volt_policy = <1>;
DCMDET = <17 0x0000ff00>;
DCBDET = <17 0x000000ff>;
MTDES = <10 0x000000ff>;
EEMINITEN = <10 0x00000100>;
EEMMONEN = <10 0x00000200>;
SPEC = <10 0x0000e000>;
BDES = <10 0x00ff0000>;
MDES = <10 0xff000000>;
};
EEMG_DET_GPU_HI {
ctrl_id = <1>;
features = <0x3>;
max_freq_khz = <902000>;
VBOOT = <0x38>;
VMAX = <0x60>;
VMIN = <0x114 0x30>;
VMIN-idx = <0x1a 0x1e 0x1a 0x1a>;
eemg_v_base = <40000>;
eemg_step = <625>;
pmic_base = <0>;
pmic_step = <625>;
DETWINDOW = <0xa28>;
DTHI = <0x01>;
DTLO = <0xfe>;
DETMAX = <0xffff>;
AGECONFIG = <0x555555>;
AGEM = <0x0>;
DVTFIXED = <0x6>;
loo_role = <2>;
loo_couple = <0>;
turn_pt = <6>;
VCO = <0x18>;
DCONFIG = <1>;
EEMCTL0 = <0x00540003>;
low_temp_off = <4>;
extra_low_temp_off = <7>;
high_temp_off = <0>;
volt_policy = <1>;
DCMDET = <17 0xff000000>;
DCBDET = <17 0x00ff0000>;
MTDES = <9 0x000000ff>;
EEMINITEN = <9 0x00000100>;
EEMMONEN = <9 0x00000200>;
SPEC = <9 0x0000e000>;
BDES = <9 0x00ff0000>;
MDES = <9 0xff000000>;
};
};
leakage {
compatible = "mediatek,mtk-static-power";
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
domain = "LL", "L", "CCI", "GPU", "VCORE", "MODEM", "VPU","VSRAM_PROC12",
"VSRAM_PROC11", "VSRAM_OTHERS", "NR", "MDLA", "ADSP", "VSRAM_GPU",
"VSRAM_VPU_MDLA", "VSRAM_MODEM", "VCORE_OFF";
LL = <0x0224 0xff 900 30 4 0>;
L = <0x0224 0xff00 900 30 4 0>;
CCI = <0x0220 0xff000000 900 30 1 0>;
GPU = <0x021c 0xff000000 800 30 1 0>;
VCORE = <0x021c 0xff0000 725 30 1 0>;
MODEM = <0x021c 0xff 825 30 1 0>;
NR = <0x021c 0xff00 825 30 1 0>;
VPU = <0x0220 0xff00 775 30 1 0>;
MDLA = <0x0220 0xff 800 30 1 0>;
VSRAM_PROC12 = <0x0228 0xff000000 900 30 1 0>;
VSRAM_PROC11 = <0x0228 0xff0000 900 30 1 0>;
VSRAM_OTHERS = <0x0224 0xff000000 750 30 1 0>;
ADSP = <0x0220 0xff0000 750 30 1 0>;
VSRAM_GPU = <0x0228 0xff00 800 30 1 0>;
VSRAM_VPU_MDLA = <0x0228 0xff 850 30 1 0>;
VSRAM_MODEM = <0x022c 0xff 825 30 1 0>;
VCORE_OFF = <0x0224 0xff0000 550 30 1 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
performance: performance-controller@0011bc00 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
dvfsp: dvfsp@0011bc00 {
compatible = "mediatek,mt6873-mcupm-dvfs";
reg = <0 0x0011bc00 0 0x1400>,
<0 0x00115c00 0 0x400>;
nvmem-cells = <&efuse_segment &cpu_version>;
nvmem-cell-names = "seg_code","level_code1";
};
qos:qos@0011bb00 {
compatible = "mediatek,mt6873-qos";
reg = <0 0x0011bb00 0 0x100>;
};
cm_mgr: cm_mgr@0c530000 {
compatible = "mediatek,mt6873-cm_mgr";
reg = <0 0x0c530000 0 0x9000>;
reg-names = "cm_mgr_base";
interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
interconnect-names = "cm-perf-bw";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>,
<&dvfsrc_freq_opp2>,
<&dvfsrc_freq_opp3>,
<&dvfsrc_freq_opp4>,
<&dvfsrc_freq_opp5>,
<&dvfsrc_freq_opp6>;
cm_mgr,cp_down = <100 100 100 100 100>;
cm_mgr,cp_up = <140 100 140 100 140>;
cm_mgr,dt_down = <3 0 0 0 0>;
cm_mgr,dt_up = <0 0 0 0 0>;
cm_mgr,vp_down = <100 100 100 100 100>;
cm_mgr,vp_up = <100 100 100 100 100>;
/* use_bcpu_weight = "enable"; */
/* cpu_power_bcpu_weight_max = <100>; */
/* cpu_power_bcpu_weight_min = <100>; */
/* use_cpu_to_dram_map = "enable"; */
/* cm_mgr_cpu_opp_to_dram = <0 0 0 0 1 1 1 1 */
/* 1 2 2 2 2 2 2 2>; */
/* use_cpu_to_dram_map_new = "enable"; */
};
fpsgo: fpsgo {
compatible = "mediatek,fpsgo";
interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
interconnect-names = "fpsgo-perf-bw";
required-opps = <&dvfsrc_freq_opp0>;
gcc_enable = <1>;
fbt_cpu_mask = <255 128 15 127>;
};
mcupm: mcupm@0c540000 {
compatible = "mediatek,mcupm";
reg = <0 0x0c540000 0 0x22000>,
<0 0x0c55fb00 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fba0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fc40 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fce0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fd80 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fe20 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55fec0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>,
<0 0x0c55ff60 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c560074 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c560078 0 0x4>;
reg-names = "mcupm_base",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_send",
"mbox0_recv",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_send",
"mbox1_recv",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_send",
"mbox2_recv",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_send",
"mbox3_recv",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_send",
"mbox4_recv",
"mbox5_base",
"mbox5_set",
"mbox5_clr",
"mbox5_send",
"mbox5_recv",
"mbox6_base",
"mbox6_set",
"mbox6_clr",
"mbox6_send",
"mbox6_recv",
"mbox7_base",
"mbox7_set",
"mbox7_clr",
"mbox7_send",
"mbox7_recv";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4",
"mbox5",
"mbox6",
"mbox7";
};
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8192-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x120 0 0x124 0 0 0
(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
0x730 12 0x734 12 0 0
(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
>;
};
};
infracfg_ao_mem@10002000 {
compatible = "mediatek,infracfg_ao_mem";
reg = <0 0x10002000 0 0x1000>;
};
pericfg: pericfg@10003000 {
compatible = "mediatek,mt8192-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
eint: apirq@1000b000 {
compatible = "mediatek,mtk-eint";
reg = <0 0x1000b000 0 0x1000>;
reg-name = "eint";
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,total-pin-number = <224>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6873-pinctrl", "syscon";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d40000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
mediatek,eint = <&eint>;
};
scpsys: power-controller@10006000 {
compatible = "mediatek,mt6873-scpsys", "syscon";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
<&topckgen CLK_TOP_IMG1_SEL>,
<&topckgen CLK_TOP_IMG2_SEL>,
<&topckgen CLK_TOP_IPE_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_MDP_SEL>,
<&topckgen CLK_TOP_DISP_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_INFRA_AUDIO_26M_B>,
<&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_ADSP_SEL>,
<&topckgen CLK_TOP_CAM_SEL>,
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>,
<&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_GALS>,
<&ipesys CLK_IPE_LARB19>,
<&ipesys CLK_IPE_LARB20>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_GALS>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_LARB1>,
<&vencsys CLK_VENC_SET1_VENC>,
<&mdpsys CLK_MDP_SMI0>,
<&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_IOMMU>,
<&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_CCU_GALS>,
<&camsys CLK_CAM_CAM2MM_GALS>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_rawc CLK_CAM_RAWC_LARBX>;
clock-names = "mfg", "isp", "isp2", "ipe",
"vdec", "venc", "mdp", "disp",
"audio", "audio1", "audio2", "adsp",
"cam", "isp-0", "isp-1", "isp2-0",
"isp2-1", "ipe-0", "ipe-1", "ipe-2",
"ipe-3", "vdec-0", "vdec-1", "vdec-2",
"vdec2-0", "vdec2-1", "vdec2-2", "venc-0",
"mdp-0", "disp-0", "disp-1", "disp-2",
"disp-3", "cam-0", "cam-1", "cam-2",
"cam-3", "cam_rawa-0", "cam_rawb-0",
"cam_rawc-0";
infracfg = <&infracfg>;
};
scp_infra: scp_infra@10001000 {
compatible = "mediatek,scpinfra";
reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */
<0 0x10006000 0 0x1000>, /* spm */
<0 0x10000000 0 0x1000>; /* topckgen */
#clock-cells = <1>;
};
sleep: sleep@10006000 {
compatible = "mediatek,sleep", "syscon";
reg = <0 0x10006000 0 0x1000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
};
srclken-ctrl@10006500 {
compatible = "mediatek,srclken-spm";
reg = <0 0x10006500 0 0x100>,
<0 0x10006E00 0 0x100>;
reg-names = "cfg", "sta";
cfg-ext = "central-4", "sw-con", "protocol-chk",
"dbg-cfg";
sta-ext = "timer-l-sta", "timer-m-sta";
trace-l-offset = <0x0 0x4 0x4 0x8 0x8 0x8 0x8 0x8>;
trace-m-offset = <0x0 0x4 0x8 0x8 0x8 0x8 0x8 0x8>;
};
srclken: srclken@10006500 {
compatible = "mediatek,srclken";
reg = <0 0x105c4000 0 0x1000>,
<0 0x10005000 0 0x1000>;
reg-names = "scpdvfs", "gpio";
mediatek,bring-up = "disable";
srclken-mode = "full-set";
subsys = "SUSPEND", "RF", "DPIDLE",
"MD", "GPS", "BT",
"WIFI", "MCU", "COANT",
"NFC", "UFS", "SCP",
"RSV";
scp-vreq-cfg = <0x54>;
scp-rc-vreq-bit = <27 28>;
gpio-dir-cfg = <0x0>;
gpio-dout-cfg = <0x100>;
gpio-pull-bit = <6>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6873-wdt",
"mediatek,mt6589-wdt",
"syscon", "simple-mfd";
mediatek,rg_dfd_timeout = <0xea60>;
reg = <0 0x10007000 0 0x100>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x24>;
mask = <0xf>;
mode-charger = <BOOT_CHARGER>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_BOOTLOADER>;
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
mode-kpoc = <BOOT_KPOC>;
mode-ddr-reserve = <BOOT_DDR_RSVD>;
mode-meta = <BOOT_META>;
mode-rpmbpk = <BOOT_RPMBPK>;
};
};
apxgpt: apxgpt@10008000 {
compatible = "mediatek,apxgpt";
reg = <0 0x10008000 0 0x1000>;
};
apmixedsys: apmixedsys@1000c000 {
compatible = "mediatek,mt8192-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
fhctl: fhctl@1000ce00 {
compatible = "mediatek,mt6873-fhctl";
reg = <0 0x1000ce00 0 0x200>;
mediatek,apmixed = <&apmixedsys>;
armpll_ll {
mediatek,fh-id = <0>;
mediatek,fh-cpu-pll;
};
armpll_bl0 {
mediatek,fh-id = <1>;
mediatek,fh-cpu-pll;
};
armpll_bl1 {
mediatek,fh-id = <2>;
mediatek,fh-cpu-pll;
};
armpll_bl2 {
mediatek,fh-id = <3>;
mediatek,fh-cpu-pll;
};
armpll_bl3 {
mediatek,fh-id = <4>;
mediatek,fh-cpu-pll;
};
ccipll {
mediatek,fh-id = <5>;
mediatek,fh-cpu-pll;
};
mfgpll {
mediatek,fh-id = <6>;
mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
};
mpll {
mediatek,fh-id = <8>;
};
mmpll {
mediatek,fh-id = <9>;
};
mainpll {
mediatek,fh-id = <10>;
mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
};
msdcpll {
mediatek,fh-id = <11>;
mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
};
adsppll {
mediatek,fh-id = <12>;
mediatek,fh-pll-id = <CLK_APMIXED_ADSPPLL>;
};
apupll {
mediatek,fh-id = <13>;
mediatek,fh-pll-id = <CLK_APMIXED_APUPLL>;
};
tvdpll {
mediatek,fh-id = <14>;
mediatek,fh-pll-id = <CLK_APMIXED_TVDPLL>;
};
};
drm:drm@1000d000 {
compatible = "mediatek,dbgtop-drm";
reg = <0 0x1000d000 0 0x1000>;
};
keypad: kp@10010000 {
compatible = "mediatek,kp";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>;
mediatek,key-debounce-ms = <1024>;
mediatek,hw-map-num = <72>;
mediatek,hw-init-map = <114 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0>;
clocks = <&clk26m>;
clock-names = "kpd";
};
dvfsrc: dvfsrc@10012000 {
compatible = "mediatek,mt6873-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
reg-names = "dvfsrc";
#interconnect-cells = <1>;
dvfsrc_vcore: dvfsrc-vcore {
regulator-name = "dvfsrc-vcore";
regulator-min-microvolt = <575000>;
regulator-max-microvolt = <725000>;
regulator-always-on;
};
dvfsrc_vscp: dvfsrc-vscp {
regulator-name = "dvfsrc-vscp";
regulator-min-microvolt = <575000>;
regulator-max-microvolt = <725000>;
regulator-always-on;
};
dvfsrc_freq_opp6: opp6 {
opp-peak-KBps = <0>;
};
dvfsrc_freq_opp5: opp5 {
opp-peak-KBps = <2500000>;
};
dvfsrc_freq_opp4: opp4 {
opp-peak-KBps = <3800000>;
};
dvfsrc_freq_opp3: opp3 {
opp-peak-KBps = <5100000>;
};
dvfsrc_freq_opp2: opp2 {
opp-peak-KBps = <5900000>;
};
dvfsrc_freq_opp1: opp1 {
opp-peak-KBps = <7600000>;
};
dvfsrc_freq_opp0: opp0 {
opp-peak-KBps = <10200000>;
};
dvfsrc-helper {
compatible = "mediatek,dvfsrc-helper";
vcore-supply = <&mt6359p_vgpu11_reg>;
rc-vcore-supply = <&dvfsrc_vcore>;
rc-vscp-supply = <&dvfsrc_vscp>;
interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>,
<&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>,
<&dvfsrc MT6873_MASTER_HRT_DBGIF &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>;
interconnect-names = "icc-bw", "icc-perf-bw", "icc-hrt-bw";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>,
<&dvfsrc_freq_opp2>,
<&dvfsrc_freq_opp3>,
<&dvfsrc_freq_opp4>,
<&dvfsrc_freq_opp5>,
<&dvfsrc_freq_opp6>;
};
dvfsrc-met {
compatible = "mediatek,dvfsrc-met";
};
};
dpmaif:dpmaif@10014000 {
compatible = "mediatek,dpmaif";
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
<0 0x1022d000 0 0x1000>, /*PD_UL*/
<0 0x1022c000 0 0x1000>, /*PD_MD_MISC*/
<0 0x1022e000 0 0x1000>; /*SRAM*/
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,dpmaif_capability = <6>;
clocks = <&infracfg CLK_INFRA_DPMAIF_MAIN>,
<&infracfg CLK_INFRA_CLDMA_B>;
clock-names = "infra-dpmaif-clk",
"infra-dpmaif-blk-clk";
interconnects = <&dvfsrc MT6873_MASTER_NETSYS &dvfsrc MT6873_SLAVE_DDR_EMI>;
interconnect-names = "icc-dpmaif-bw";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>;
net_spd_ver = <2>;
mediatek,ap_plat_info = <6873>;
};
systimer: systimer@10017000 {
compatible = "mediatek,mt6873-timer",
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk13m>;
};
spmi: spmi@10027000 {
compatible = "mediatek,mt6873-spmi";
reg = <0 0x10027000 0 0x000e00>,
<0 0x10029000 0 0x000100>;
reg-names = "pmif", "spmimst";
clocks = <&infracfg CLK_INFRA_PMIC_AP>,
<&infracfg CLK_INFRA_PMIC_TMR>,
<&topckgen CLK_TOP_SPMI_MST_SEL>;
clock-names = "pmif_sys_ck",
"pmif_tmr_ck",
"spmimst_clk_mux";
assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
devapc: devapc@10207000 {
compatible = "mediatek,mt6873-devapc";
reg = <0 0x10207000 0 0x1000>,
<0 0x10274000 0 0x1000>,
<0 0x10275000 0 0x1000>,
<0 0x11020000 0 0x1000>,
<0 0x10030000 0 0x1000>,
<0 0x1020e000 0 0x1000>,
<0 0x10033000 0 0x1000>,
<0 0x0010c000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
clock-names = "devapc-infra-clock";
};
ccifdriver:ccifdriver@10209000 {
compatible = "mediatek,ccci_ccif";
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
mediatek,sram_size = <512>;
/*CCIF0 174/206, CCIF0 175/207*/
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_CCIF_AP>,
<&infracfg CLK_INFRA_CCIF_MD>,
<&infracfg CLK_INFRA_CCIF1_AP>,
<&infracfg CLK_INFRA_CCIF1_MD>,
<&infracfg CLK_INFRA_CCIF4_MD>,
<&infracfg CLK_INFRA_CCIF5_MD>;
clock-names = "infra-ccif-ap",
"infra-ccif-md",
"infra-ccif1-ap",
"infra-ccif1-md",
"infra-ccif4-md",
"infra-ccif5-md";
ccif-pericfg = <&pericfg>;
};
mddriver:mddriver {
compatible = "mediatek,mddriver";
/* bit0~3: CLDMA|CCIF|DPMAIF */
mediatek,mdhif_type = <6>;
mediatek,md_id = <0>;
mediatek,ap_plat_info = <6873>;
mediatek,md_generation = <6297>;
mediatek,offset_epon_md1 = <0x2844>;
mediatek,cldma_capability = <14>;
/* bit0~1: srcclkena|srclken_o1_on */
mediatek,power_flow_config = <3>;
/* srclken_o1 set value |= 1<<21 */
mediatek,srclken_o1 = <0x200000>;
/* MDWDT; CCIF0 194/226; CCIF0 195/227 */
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING 0>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
/* md_vmodem-supply = <&mt6315_3_vbuck1>; move mt6873.dts */
/* md_vsram-supply = <&mt6315_3_vbuck4>; move mt6873.dts */
/* md_vnr-supply = <&mt6315_3_vbuck3>; move mt6873.dts */
/* md_vdigrf-supply = <&mt6359p_vpu_reg>; move mt6873.dts */
power-domains = <&scpsys MT6873_POWER_DOMAIN_MD>;
ccci-infracfg = <&infracfg>;
ccci_spmsleep = <&sleep>;
};
md_auxadc:md_auxadc {
compatible = "mediatek,md_auxadc";
io-channels = <&auxadc 2>;
io-channel-names = "md-channel",
"md-battery";
};
md_ccci_rtc:md_ccci_rtc {
compatible = "mediatek,md_ccci_rtc";
nvmem-cells = <&ext_32k>;
nvmem-cell-names = "external-32k";
};
ccci_scp:ccci_scp {
compatible = "mediatek,ccci_md_scp";
clocks = <&infracfg CLK_INFRA_CCIF2_AP>,
<&infracfg CLK_INFRA_CCIF2_MD>;
clock-names = "infra-ccif2-ap",
"infra-ccif2-md";
};
gpio_usage_mapping:gpio {
compatible = "mediatek,gpio_usage_mapping";
};
md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
};
md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
};
cqdma: cq_dma@10212000 {
compatible = "mediatek,mt6765-cqdma";
reg = <0 0x10212000 0 0x80>,
<0 0x10212100 0 0x80>,
<0 0x10212200 0 0x80>,
<0 0x10212300 0 0x80>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <4>;
dma-channel-mask = <63>;
clocks = <&infracfg CLK_INFRA_CQ_DMA>;
clock-names = "cqdma";
};
apdma: dma-controller@10217a80 {
compatible = "mediatek,mt6779-uart-dma";
reg = <0 0x10217a80 0 0x80>,
<0 0x10217b00 0 0x80>,
<0 0x10217b80 0 0x80>,
<0 0x10217c00 0 0x80>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "apdma";
dma-requests = <4>;
#dma-cells = <1>;
};
emicen: emicen@10219000 {
compatible = "mediatek,mt6873-emicen",
"mediatek,common-emicen";
reg = <0 0x10219000 0 0x1000>;
mediatek,emi-reg = <&emichn>;
};
emiisu: emiisu {
compatible = "mediatek,mt6873-emiisu",
"mediatek,common-emiisu";
ctrl_intf = <1>;
};
device_mpu_low@1021a000 {
compatible = "mediatek,device_mpu_low";
reg = <0 0x1021a000 0 0x1000>;
prot-base = <0x0 0x40000000>;
prot-size = <0x4 0x00000000>;
page-size = <0x200000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
};
ktf-cmdq-test {
compatible = "mediatek,ktf-cmdq-test";
mediatek,gce = <&gce>;
mmsys_config = <&mmsys>;
mboxes = <&gce 8 0 CMDQ_THR_PRIO_1>,
<&gce 9 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
<&gce 10 0 CMDQ_THR_PRIO_1>;
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
};
cmdq-test {
compatible = "mediatek,cmdq-test";
mediatek,gce = <&gce>;
mmsys_config = <&mmsys>;
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
};
emimpu:emimpu@10226000 {
compatible = "mediatek,mt6873-emimpu",
"mediatek,common-emimpu";
reg = <0 0x10226000 0 0x1000>;
mediatek,emi-reg = <&emicen>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
region_cnt = <32>;
domain_cnt = <16>;
addr_align = <16>;
ap_region = <31>;
ap_apc = <0 5 5 5 0 0 6 5>,
<0 0 5 0 0 1 5 5>;
dump = <0x1f0 0x1f8 0x1fc>;
clear = <0x160 0xffffffff 16>,
<0x200 0x00000003 16>,
<0x1f0 0x80000000 1>;
clear_md = <0x1fc 0x80000000 1>;
ctrl_intf = <1>;
slverr = <0>;
};
gce: mailbox@10228000 {
compatible = "mediatek,mt6873-gce";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
clocks = <&infracfg CLK_INFRA_GCE>,
<&infracfg CLK_INFRA_GCE_26M>;
clock-names = "gce", "gce-timer";
gce-gctl-sw = "true";
};
dramc: dramc@10230000 {
compatible = "mediatek,mt6873-dramc",
"mediatek,common-dramc";
reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
<0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
<0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
<0 0x10006000 0 0x1000>; /* SLEEP BASE */
mr4_version = <1>;
mr4_rg = <0x0090 0x0000ffff 0>;
fmeter_version = <1>;
crystal_freq = <52>;
pll_id = <0x050c 0x00000100 8>;
shu_lv = <0x050c 0x00030000 16>;
shu_of = <0x700>;
sdmpcw = <0x0704 0xffff0000 16>,
<0x0724 0xffff0000 16>;
prediv = <0x0708 0x000c0000 18>,
<0x0728 0x000c0000 18>;
posdiv = <0x0708 0x00000007 0>,
<0x0728 0x00000007 0>;
ckdiv4 = <0x0874 0x00000004 2>,
<0x0874 0x00000004 2>;
pll_md = <0x0744 0x00000100 8>,
<0x0744 0x00000100 8>;
cldiv2 = <0x08b4 0x00000002 1>,
<0x08b4 0x00000002 1>;
fbksel = <0x070c 0x00000040 6>,
<0x070c 0x00000040 6>;
dqopen = <0x0870 0x00100000 20>,
<0x0870 0x00100000 20>;
dqsopen = <0x0870 0x00100000 20>,
<0x0870 0x00100000 20>;
ckdiv4_ca = <0x0b74 0x00000004 2>,
<0x0b74 0x00000004 2>;
};
emichn: emichn@10235000 {
compatible = "mediatek,mt6873-emichn",
"mediatek,common-emichn";
reg = <0 0x10235000 0 0x1000>,
<0 0x10245000 0 0x1000>;
};
md_ccif4@1024d000 {
compatible = "mediatek,md_ccif4";
reg = <0 0x1024d000 0 0x1000>;
};
device_mpu_acp@1030d000 {
compatible = "mediatek,device_mpu_acp";
reg = <0 0x1030d000 0 0x1000>;
prot-base = <0x0 0x40000000>;
prot-size = <0x4 0x00000000>;
page-size = <0x200000>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>;
};
sspm@10400000 {
compatible = "mediatek,sspm";
reg = <0 0x10400000 0 0x28000>,
<0 0x10440000 0 0x10000>,
<0 0x10450000 0 0x100>,
<0 0x10451000 0 0x4>,
<0 0x10451004 0 0x4>,
<0 0x10460000 0 0x100>,
<0 0x10461000 0 0x4>,
<0 0x10461004 0 0x4>,
<0 0x10470000 0 0x100>,
<0 0x10471000 0 0x4>,
<0 0x10471004 0 0x4>,
<0 0x10480000 0 0x100>,
<0 0x10481000 0 0x4>,
<0 0x10481004 0 0x4>,
<0 0x10490000 0 0x100>,
<0 0x10491000 0 0x4>,
<0 0x10491004 0 0x4>;
reg-names = "sspm_base",
"cfgreg",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox4_base",
"mbox4_set",
"mbox4_clr";
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "ipc",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
};
scp_adsp: scp_adsp@10720000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
#clock-cells = <1>;
};
scp: scp@10700000 {
compatible = "mediatek,scp";
status = "okay";
reg = <0 0x10500000 0 0x100000>, /* tcm */
<0 0x10724000 0 0x1000>, /* cfg */
<0 0x10721000 0 0x1000>, /* clk*/
<0 0x10730000 0 0x1000>, /* cfg core0 */
<0 0x10740000 0 0x1000>, /* cfg core1 */
<0 0x10752000 0 0x1000>, /* bus tracker */
<0 0x10760000 0 0x40000>, /* llc */
<0 0x107a5000 0 0x4>, /* cfg_sec */
<0 0x107fb000 0 0x100>, /* mbox0 base */
<0 0x107fb100 0 0x4>, /* mbox0 set */
<0 0x107fb10c 0 0x4>, /* mbox0 clr */
<0 0x107a5020 0 0x4>, /* mbox0 init */
<0 0x107fc000 0 0x100>, /* mbox1 base */
<0 0x107fc100 0 0x4>, /* mbox1 set */
<0 0x107fc10c 0 0x4>, /* mbox1 clr */
<0 0x107a5024 0 0x4>, /* mbox1 init */
<0 0x107fd000 0 0x100>, /* mbox2 base */
<0 0x107fd100 0 0x4>, /* mbox2 set */
<0 0x107fd10c 0 0x4>, /* mbox2 clr */
<0 0x107a5028 0 0x4>, /* mbox2 init */
<0 0x107fe000 0 0x100>, /* mbox3 base */
<0 0x107fe100 0 0x4>, /* mbox3 set */
<0 0x107fe10c 0 0x4>, /* mbox3 clr */
<0 0x107a502c 0 0x4>, /* mbox3 init */
<0 0x107ff000 0 0x100>, /* mbox4 base */
<0 0x107ff100 0 0x4>, /* mbox4 set */
<0 0x107ff10c 0 0x4>, /* mbox4 clr */
<0 0x107a5030 0 0x4>; /* mbox4 init */
reg-names = "scp_sram_base",
"scp_cfgreg",
"scp_clkreg",
"scp_cfgreg_core0",
"scp_cfgreg_core1",
"scp_bus_tracker",
"scp_l1creg",
"scp_cfgreg_sec",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_init",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_init",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_init",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_init",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_init";
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "ipc0",
"ipc1",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
core_0 = "enable";
scp_sramSize = <0x00100000>;
core_nums = <2>; /* core number */
twohart = <0>; /* two hart arch */
mbox_count = <5>;
/* id, mbox, send_size*/
send_table =
< 0 0 9>,/* IPI_OUT_AUDIO_VOW_1 */
< 3 1 2>,/* IPI_OUT_APCCCI_0 */
< 4 1 1>,/* IPI_OUT_DVFS_SET_FREQ_0 */
< 5 1 2>,/* IPI_OUT_C_SLEEP_0 */
< 6 1 1>,/* IPI_OUT_TEST_0 */
<26 1 9>,/* IPI_OUT_AUDIO_ULTRA_SND_0 */
<11 2 34>,/* IPI_OUT_SCP_MPOOL_0 */
<14 3 1>,/* IPI_OUT_DVFS_SET_FREQ_1 */
<15 3 2>,/* IPI_OUT_C_SLEEP_1 */
<16 3 1>,/* IPI_OUT_TEST_1 */
<17 3 6>,/* IPI_OUT_LOGGER_CTRL */
<18 3 2>,/* IPI_OUT_SCPCTL_1 */
<24 4 34>;/* IPI_OUT_SCP_MPOOL_1 */
/* id, mbox, recv_size, recv_opt */
recv_table =
< 1 0 2 0>,/* IPI_IN_AUDIO_VOW_ACK_1 */
< 2 0 26 0>,/* IPI_IN_AUDIO_VOW_1 */
< 7 1 2 0>,/* IPI_IN_APCCCI_0 */
< 8 1 10 0>,/* IPI_IN_SCP_ERROR_INFO_0 */
< 9 1 1 0>,/* IPI_IN_SCP_READY_0 */
<10 1 2 0>,/* IPI_IN_SCP_RAM_DUMP_0 */
<27 1 2 0>,/* IPI_IN_AUDIO_ULTRA_SND_ACK_0 */
<28 1 5 0>,/* IPI_IN_AUDIO_ULTRA_SND_0 */
< 5 1 1 1>,/* IPI_OUT_C_SLEEP_0 */
<12 2 30 0>,/* IPI_IN_SCP_MPOOL_0 */
<20 3 10 0>,/* IPI_IN_SCP_ERROR_INFO_1 */
<21 3 6 0>,/* IPI_IN_LOGGER_CTRL */
<22 3 1 0>,/* IPI_IN_SCP_READY_1 */
<23 3 2 0>,/* IPI_IN_SCP_RAM_DUMP_1 */
<15 3 1 1>,/* IPI_OUT_C_SLEEP_1 */
<25 4 30 0>;/* IPI_IN_SCP_MPOOL_1 */
legacy_table = <11>, /* out_id_0 IPI_OUT_SCP_MPOOL_0 */
<24>, /* out_id_1 IPI_OUT_SCP_MPOOL_1 */
<12>, /* in_id_0 IPI_IN_SCP_MPOOL_0 */
<12>, /* in_id_1 IPI_IN_SCP_MPOOL_0 */
<34>, /* out_size */
<30>; /* in_size */
/* feature, frequecy, coreid */
scp_feature_tbl = < 0 5 1>, /* vow */
< 1 29 0>, /* sensor */
< 2 26 0>, /* flp */
< 3 0 0>, /* rtos */
< 4 200 1>, /* speaker */
< 5 0 0>, /* vcore */
< 6 135 1>, /* barge in */
< 7 10 1>, /* vow dump */
< 8 80 1>, /* vow vendor M */
< 9 43 1>, /* vow vendor A */
<10 22 1>, /* vow vendor G */
<11 20 1>, /* vow dual mic */
<12 100 1>, /* vow dual mic barge in */
<13 200 0>; /* ultrasound */
secure_dump = "disable"; /* disabled in default */
secure_dump_size = <0>;
scp_mem_key = "mediatek,reserve-memory-scp_share";
/* feature ID, size, alignment */
scp_mem_tbl = <0 0x0 0x0>, /* secure dump,*/
/*its size is in secure_dump_size */
<1 0x4A700 0x0>, /* vow */
<2 0x100000 0x0>, /* sensor */
<3 0x180000 0x0>, /* logger */
<4 0x19000 0x0>; /* audio */
memorydump =
<0x100000>, /* l2tcm */
<0x03c000>, /* l1c */
<0x003f00>, /* regdump */
<0x000100>, /* trace buffer */
<0x100000>; /* dram */
};
scp_clk_ctrl: scp_clk_ctrl@10721000 {
compatible = "mediatek,scp_clk_ctrl", "syscon";
reg = <0 0x10721000 0 0x1000>; /* clk*/
};
scp_dvfs {
compatible = "mediatek,scp_dvfs";
clocks = <&topckgen CLK_TOP_SCP_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_UNIVPLL_D5>,
<&topckgen CLK_TOP_MAINPLL_D6_D2>,
<&topckgen CLK_TOP_MAINPLL_D6>,
<&topckgen CLK_TOP_UNIVPLL_D6>,
<&topckgen CLK_TOP_MAINPLL_D4_D2>,
<&topckgen CLK_TOP_MAINPLL_D5_D2>,
<&topckgen CLK_TOP_UNIVPLL_D4_D2>;
clock-names = "clk_mux",
"clk_pll_0",
"clk_pll_1",
"clk_pll_2",
"clk_pll_3",
"clk_pll_4",
"clk_pll_5",
"clk_pll_6",
"clk_pll_7";
vow-lp-en-gear = <2>;
scp-cores = <2>;
dvfs-opp =
/* vcore vsram opp spm freq mux resource */
< 575000 750000 0x0 0x8 196 2 0>,
< 600000 750000 0x1 0x104 260 5 0>,
< 650000 750000 0x2 0x202 280 7 0>,
< 725000 750000 0x3 0x301 360 3 0>,
< 725000 750000 0x3 0x301 416 4 0x3>;
pmic = <&pmic>;
pmic-sshub-support;
gpio-base = <&pio>;
gpio-vreq-mode = <1>;
gpio-vreq = <0x410 0x7 24>;
dvfsrc-vscp-supply = <&dvfsrc_vscp>;
sshub-vcore-supply = <&mt6359p_vcore_sshub_reg>;
sshub-vsram-supply = <&mt6359p_vsram_others_sshub_ldo>;
do-ulposc-cali;
fmeter_clksys = <&topckgen>;
ulposc_clksys = <&apmixedsys>;
scp_clk_ctrl = <&scp_clk_ctrl>;
scp-clk-hw-ver = "v1";
ulposc-cali-ver = "v1";
ulposc-cali-num = <3>;
ulposc-cali-target = <196 280 360>;
ulposc-cali-config =
/* con0 con1 con2 */
<0x5aa940 0x3002900 0x40>,
<0x3ca940 0x2900 0x40>,
<0x52a940 0x2900 0x40>;
clk-dbg-ver = "v1";
};
adsp_common: adsp_common@10800000 {
compatible = "mediatek,adsp_common";
reg = <0 0x1080b000 0 0x50>, /* CFG SECURE */
<0 0x10806000 0 0x100>, /* MBOX0 base */
<0 0x10806100 0 0x4>, /* MBOX0 set */
<0 0x1080610c 0 0x4>, /* MBOX0 clr */
<0 0x1080b050 0 0x4>, /* MBOX0 init */
<0 0x10807000 0 0x100>, /* MBOX1 base */
<0 0x10807100 0 0x4>, /* MBOX1 set */
<0 0x1080710c 0 0x4>, /* MBOX1 clr */
<0 0x1080b054 0 0x4>, /* MBOX1 init */
<0 0x10808000 0 0x100>, /* MBOX2 base */
<0 0x10808100 0 0x4>, /* MBOX2 set */
<0 0x1080810c 0 0x4>, /* MBOX2 clr */
<0 0x1080b058 0 0x4>, /* MBOX2 init */
<0 0x10809000 0 0x100>, /* MBOX3 base */
<0 0x10809100 0 0x4>, /* MBOX3 set */
<0 0x1080910c 0 0x4>, /* MBOX3 clr */
<0 0x1080b05c 0 0x4>; /* MBOX3 init */
reg-names = "cfg_secure",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_init",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_init",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_init",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_init";
interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX0 */
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX1 */
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH 0>, /* MBOX2 */
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH 0>; /* MBOX3 */
interrupt-names = "mbox0",
"mbox1",
"mbox2",
"mbox3";
#mbox-cells = <1>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_ADSP>;
clocks = <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_ADSPPLL>,
<&topckgen CLK_TOP_SCP_SEL>;
clock-names = "clk_adsp_ck_cg",
"clk_top_adsp_sel",
"clk_top_clk26m",
"clk_top_adsppll",
"clk_top_scp_sel";
adsp-rsv-ipidma-a = <0x100000>;
adsp-rsv-ipidma-b = <0x100000>;
adsp-rsv-logger-a = <0x80000>;
adsp-rsv-logger-b = <0x80000>;
adsp-rsv-c2c = <0x40000>;
adsp-rsv-dbg-dump-a = <0x80000>;
adsp-rsv-dbg-dump-b = <0x80000>;
adsp-rsv-core-dump-a = <0x400>;
adsp-rsv-core-dump-b = <0x400>;
adsp-rsv-audio = <0x5c0000>;
};
adsp_core0: adsp_core0@10820000 {
compatible = "mediatek,adsp_core_0";
reg = <0 0x10800000 0 0x6000>, /* CFG */
<0 0x10840000 0 0x9000>, /* ITCM */
<0 0x10820000 0 0x8000>; /* DTCM */
system = <0 0x56000000 0 0x700000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH 0>;
mboxes = <&adsp_common 0>, /*channel 0*/
<&adsp_common 1>; /*channel 1*/
feature_control_bits = <0x303FF>;
};
adsp_core1: adsp_core1@10850000 {
compatible = "mediatek,adsp_core_1";
reg = <0 0x10800000 0 0x6000>, /* CFG */
<0 0x10870000 0 0x9000>, /* ITCM */
<0 0x10850000 0 0x8000>; /* DTCM */
system = <0 0x56700000 0 0x700000>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH 0>;
mboxes = <&adsp_common 2>, /*channel 2*/
<&adsp_common 3>; /*channel 3*/
feature_control_bits = <0x18F00F>;
};
auxadc: auxadc@11001000 {
compatible = "mediatek,mt6765-auxadc";
reg = <0 0x11001000 0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING 0>;
clocks = <&infracfg CLK_INFRA_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
/* Auxadc efuse calibration */
/* 1. Auxadc cali on/off bit shift */
mediatek,cali-en-bit = <20>;
/* 2. Auxadc cali ge bits shift */
mediatek,cali-ge-bit = <10>;
/* 3. Auxadc cali oe bits shift */
mediatek,cali-oe-bit = <0>;
/* 4. Auxadc cali efuse reg offset */
mediatek,cali-efuse-reg-offset = <0x1c4>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
};
uart0: serial@11002000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0 &apdma 1>;
dma-names = "tx", "rx";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0 &apdma 1>;
dma-names = "tx", "rx";
};
imp_iic_wrap_c: imp_iic_wrap_c@11007000 {
compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon";
reg = <0 0x11007000 0 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
lvts: lvts@1100b000 {
compatible = "mediatek,mt6873-lvts";
#thermal-sensor-cells = <1>;
reg = <0 0x1100b000 0 0x1000>,
<0 0x11278000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_THERM>;
clock-names = "lvts_clk";
resets = <&infracfg_rst 0>,
<&infracfg_rst 1>;
nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
nvmem-cell-names = "e_data1","e_data2";
};
btif@1100c000 {
compatible = "mediatek,btif";
/*btif base*/
reg = <0 0x1100c000 0 0x1000>,
/*btif tx dma base*/
<0 0x10217d80 0 0x80>,
/*btif rx dma base*/
<0 0x10217e00 0 0x80>;
/*btif irq, IRQS_Sync ID, btif_irq_b*/
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH 0>,
/*btif tx dma irq*/
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>,
/*btif rx dma irq*/
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_BTIF>,
/*btif clock*/
<&infracfg CLK_INFRA_AP_DMA>;
/*ap dma clock*/
clock-names = "btifc","apdmac";
};
disp_pwm: pwm@1100e000 {
compatible = "mediatek,disp_pwm0",
"mediatek,mt6873-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
clocks = <&infracfg CLK_INFRA_DISP_PWM>,
<&topckgen CLK_TOP_DISP_PWM_SEL>,
<&topckgen CLK_TOP_OSC_D4>;
clock-names = "main", "mm", "pwm_src";
};
spi1: spi@11010000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11010000 0 0x100>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi2: spi@11012000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11012000 0 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi3: spi@11013000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11013000 0 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
pwm_leds {
compatible = "pwm-leds";
backlight {
label = "lcd-backlight";
pwms = <&disp_pwm 0 39385>;
pwm-names = "lcd-backlight";
max-brightness = <255>;
};
};
i2c10: i2c@11015000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11015000 0 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_I2C10>;
clock-names = "main";
clock-div = <1>;
mediatek,fifo_only;
};
i2c11: i2c@11017000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11017000 0 0x1000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_I2C11>;
clock-names = "main";
clock-div = <1>;
mediatek,fifo_only;
};
spi4: spi@11018000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11018000 0 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi5: spi@11019000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11019000 0 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi6: spi@1101d000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1101d000 0 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI6>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi7: spi@1101e000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1101e000 0 0x100>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI7>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
ssusb: usb0@11201000 {
compatible = "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
vusb33-supply = <&mt6359p_vusb_reg>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
phy-cells = <1>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>;
clocks = <&infracfg CLK_INFRA_SSUSB>,
<&infracfg CLK_INFRA_SSUSB_XHCI>;
clock-names = "sys_ck","ref_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dr_mode = "otg";
maximum-speed = "high-speed";
mediatek,force-vbus;
mediatek,clk-mgr;
mediatek,usb3-drd;
usb-role-switch;
usb_host: xhci0@11200000 {
compatible = "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_SSUSB_XHCI>;
clock-names = "sys_ck";
mediatek,keep-clock-on;
status = "okay";
};
};
audsys: audsys@11210000 {
compatible = "mediatek,mt8192-audsys", "syscon";
reg = <0 0x11210000 0 0x2000>;
#clock-cells = <1>;
};
afe: mt6873-afe-pcm@11210000 {
compatible = "mediatek,mt6873-sound";
reg = <0 0x11210000 0 0x2000>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
topckgen = <&topckgen>;
apmixedsys = <&apmixedsys>;
infracfg = <&infracfg>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_AUDIO>;
clocks = <&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>,
<&audsys CLK_AUD_ADC>,
<&audsys CLK_AUD_ADDA6_ADC>,
<&audsys CLK_AUD_22M>,
<&audsys CLK_AUD_24M>,
<&audsys CLK_AUD_APLL_TUNER>,
<&audsys CLK_AUD_APLL2_TUNER>,
<&audsys CLK_AUD_TDM>,
<&audsys CLK_AUD_TML>,
<&audsys CLK_AUD_NLE>,
<&audsys CLK_AUD_DAC_HIRES>,
<&audsys CLK_AUD_ADC_HIRES>,
<&audsys CLK_AUD_ADC_HIRES_TML>,
<&audsys CLK_AUD_ADDA6_ADC_HIRES>,
<&audsys CLK_AUD_3RD_DAC>,
<&audsys CLK_AUD_3RD_DAC_PREDIS>,
<&audsys CLK_AUD_3RD_DAC_TML>,
<&audsys CLK_AUD_3RD_DAC_HIRES>,
<&infracfg CLK_INFRA_AUDIO>,
<&infracfg CLK_INFRA_AUDIO_26M_B>,
<&topckgen CLK_TOP_AUDIO_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen CLK_TOP_MAINPLL_D4_D4>,
<&topckgen CLK_TOP_AUD_1_SEL>,
<&topckgen CLK_TOP_APLL1>,
<&topckgen CLK_TOP_AUD_2_SEL>,
<&topckgen CLK_TOP_APLL2>,
<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
<&topckgen CLK_TOP_APLL1_D4>,
<&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
<&topckgen CLK_TOP_APLL2_D4>,
<&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
<&topckgen CLK_TOP_APLL12_DIV0>,
<&topckgen CLK_TOP_APLL12_DIV1>,
<&topckgen CLK_TOP_APLL12_DIV2>,
<&topckgen CLK_TOP_APLL12_DIV3>,
<&topckgen CLK_TOP_APLL12_DIV4>,
<&topckgen CLK_TOP_APLL12_DIVB>,
<&topckgen CLK_TOP_APLL12_DIV5>,
<&topckgen CLK_TOP_APLL12_DIV6>,
<&topckgen CLK_TOP_APLL12_DIV7>,
<&topckgen CLK_TOP_APLL12_DIV8>,
<&topckgen CLK_TOP_APLL12_DIV9>,
<&topckgen CLK_TOP_AUDIO_H_SEL>,
<&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
"aud_adc_clk",
"aud_adda6_adc_clk",
"aud_apll22m_clk",
"aud_apll24m_clk",
"aud_apll1_tuner_clk",
"aud_apll2_tuner_clk",
"aud_tdm_clk",
"aud_tml_clk",
"aud_nle",
"aud_dac_hires_clk",
"aud_adc_hires_clk",
"aud_adc_hires_tml",
"aud_adda6_adc_hires_clk",
"aud_3rd_dac_clk",
"aud_3rd_dac_predis_clk",
"aud_3rd_dac_tml",
"aud_3rd_dac_hires_clk",
"aud_infra_clk",
"aud_infra_26m_clk",
"top_mux_audio",
"top_mux_audio_int",
"top_mainpll_d4_d4",
"top_mux_aud_1",
"top_apll1_ck",
"top_mux_aud_2",
"top_apll2_ck",
"top_mux_aud_eng1",
"top_apll1_d4",
"top_mux_aud_eng2",
"top_apll2_d4",
"top_i2s0_m_sel",
"top_i2s1_m_sel",
"top_i2s2_m_sel",
"top_i2s3_m_sel",
"top_i2s4_m_sel",
"top_i2s5_m_sel",
"top_i2s6_m_sel",
"top_i2s7_m_sel",
"top_i2s8_m_sel",
"top_i2s9_m_sel",
"top_apll12_div0",
"top_apll12_div1",
"top_apll12_div2",
"top_apll12_div3",
"top_apll12_div4",
"top_apll12_divb",
"top_apll12_div5",
"top_apll12_div6",
"top_apll12_div7",
"top_apll12_div8",
"top_apll12_div9",
"top_mux_audio_h",
"top_clk26m_clk";
pinctrl-names = "aud_clk_mosi_off",
"aud_clk_mosi_on",
"aud_dat_mosi_off",
"aud_dat_mosi_on",
"aud_dat_mosi_ch34_off",
"aud_dat_mosi_ch34_on",
"aud_dat_miso0_off",
"aud_dat_miso0_on",
"aud_dat_miso1_off",
"aud_dat_miso1_on",
"aud_dat_miso2_off",
"aud_dat_miso2_on",
"vow_dat_miso_off",
"vow_dat_miso_on",
"vow_clk_miso_off",
"vow_clk_miso_on",
"aud_gpio_i2s0_off",
"aud_gpio_i2s0_on",
"aud_gpio_i2s1_off",
"aud_gpio_i2s1_on",
"aud_gpio_i2s2_off",
"aud_gpio_i2s2_on",
"aud_gpio_i2s3_off",
"aud_gpio_i2s3_on",
"aud_gpio_i2s5_off",
"aud_gpio_i2s5_on",
"aud_gpio_i2s6_off",
"aud_gpio_i2s6_on",
"aud_gpio_i2s7_off",
"aud_gpio_i2s7_on",
"aud_gpio_i2s8_off",
"aud_gpio_i2s8_on",
"aud_gpio_i2s9_off",
"aud_gpio_i2s9_on";
pinctrl-0 = <&aud_clk_mosi_off>;
pinctrl-1 = <&aud_clk_mosi_on>;
pinctrl-2 = <&aud_dat_mosi_off>;
pinctrl-3 = <&aud_dat_mosi_on>;
pinctrl-4 = <&aud_dat_mosi_ch34_off>;
pinctrl-5 = <&aud_dat_mosi_ch34_on>;
pinctrl-6 = <&aud_dat_miso0_off>;
pinctrl-7 = <&aud_dat_miso0_on>;
pinctrl-8 = <&aud_dat_miso1_off>;
pinctrl-9 = <&aud_dat_miso1_on>;
pinctrl-10 = <&aud_dat_miso2_off>;
pinctrl-11 = <&aud_dat_miso2_on>;
pinctrl-12 = <&vow_dat_miso_off>;
pinctrl-13 = <&vow_dat_miso_on>;
pinctrl-14 = <&vow_clk_miso_off>;
pinctrl-15 = <&vow_clk_miso_on>;
pinctrl-16 = <&aud_gpio_i2s0_off>;
pinctrl-17 = <&aud_gpio_i2s0_on>;
pinctrl-18 = <&aud_gpio_i2s1_off>;
pinctrl-19 = <&aud_gpio_i2s1_on>;
pinctrl-20 = <&aud_gpio_i2s2_off>;
pinctrl-21 = <&aud_gpio_i2s2_on>;
pinctrl-22 = <&aud_gpio_i2s3_off>;
pinctrl-23 = <&aud_gpio_i2s3_on>;
pinctrl-24 = <&aud_gpio_i2s5_off>;
pinctrl-25 = <&aud_gpio_i2s5_on>;
pinctrl-26 = <&aud_gpio_i2s6_off>;
pinctrl-27 = <&aud_gpio_i2s6_on>;
pinctrl-28 = <&aud_gpio_i2s7_off>;
pinctrl-29 = <&aud_gpio_i2s7_on>;
pinctrl-30 = <&aud_gpio_i2s8_off>;
pinctrl-31 = <&aud_gpio_i2s8_on>;
pinctrl-32 = <&aud_gpio_i2s9_off>;
pinctrl-33 = <&aud_gpio_i2s9_on>;
};
audio_sram@11212000 {
compatible = "mediatek,audio_sram";
reg = <0 0x11212000 0 0x18000>;
prefer_mode = <0>;
mode_size = <0x12000 0x18000>;
block_size = <0x1000>;
};
ufshci: ufshci@11270000 {
compatible = "mediatek,mt8183-ufshci";
reg = <0 0x11270000 0 0x2300>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_UFS>,
<&infracfg CLK_INFRA_UFS_TICK>,
<&infracfg CLK_INFRA_UFS_AXI>,
<&infracfg CLK_INFRA_UFS_MP_SAP_B>,
<&infracfg CLK_INFRA_UNIPRO_TICK>,
<&infracfg CLK_INFRA_UNIPRO_MBIST>,
<&infracfg CLK_INFRA_UNIPRO_SYS>,
<&infracfg CLK_INFRA_AES_UFSFDE>,
<&topckgen CLK_TOP_AES_UFSFDE_SEL>,
<&topckgen CLK_TOP_UNIVPLL_D6>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "ufs", "ufs_tick", "ufs_axi", "ufs_mp",
"unipro_tick", "unipro_mbist", "unipro_sys",
"crypt_infra", "crypt_mux",
"crypt_lp", "crypt_perf";
freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>,
<0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
vcc-supply = <&mt6359p_vemc_reg>;
mediatek,ufs-boost-crypt;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
boost-crypt-vcore-min = <600000>;
mediatek,ufs-disable-ah8;
/* Reference clock control mode */
/* SW mode: 0, Half-HW mode: 1, HW mode: 2 */
mediatek,refclk_ctrl = <1>;
};
efuse: efuse@11c10000 {
compatible = "mediatek,devinfo";
reg = <0 0x11c10000 0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
efuse_segment: segment@78 {
reg = <0x78 0x4>;
};
apu_pod19: apu_efuse2 {
reg = <0x114 0x4>;
};
lvts_e_data1: data1 {
reg = <0x1D0 0x10>;
};
lvts_e_data2: data2 {
reg = <0x2F8 0x48>;
};
apu_pod26: apu_efuse3 {
reg = <0x344 0x4>;
};
cpu_version: cpu_data {
reg = <0x234 0x4>;
};
};
regulator_vibrator {
compatible = "regulator-vibrator";
min-volt = <1200000>;
max-volt = <3300000>;
min-limit = <15>;
max-limit = <15000>;
vib-supply = <&mt6359p_vibr_reg>;
};
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
imp_iic_wrap_e: imp_iic_wrap_e@11cb1000 {
compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon";
reg = <0 0x11cb1000 0 0x1000>;
#clock-cells = <1>;
};
i2c7: i2c@11d00000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
i2c8: i2c@11d01000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
i2c9: i2c@11d02000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
imp_iic_wrap_s: imp_iic_wrap_s@11d03000 {
compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon";
reg = <0 0x11d03000 0 0x1000>;
#clock-cells = <1>;
};
i2c1: i2c@11d20000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
i2c2: i2c@11d21000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
i2c4: i2c@11d22000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
imp_iic_wrap_ws: imp_iic_wrap_ws@11d23000 {
compatible = "mediatek,mt8192-imp_iic_wrap_ws",
"syscon";
reg = <0 0x11d23000 0 0x1000>;
#clock-cells = <1>;
};
i2c5: i2c@11e00000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
<&infracfg CLK_INFRA_AP_DMA >;
clock-names = "main", "dma";
clock-div = <1>;
};
imp_iic_wrap_w: imp_iic_wrap_w@11e01000 {
compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon";
reg = <0 0x11e01000 0 0x1000>;
#clock-cells = <1>;
};
u3phy: usb0-phy@11e40000 {
compatible = "mediatek,generic-tphy-v2";
clocks = <&clk26m>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
u2port0: usb2-phy0@11e40000 {
reg = <0 0x11e40000 0 0x700>;
#phy-cells = <1>;
};
u3port0: usb3-phy0@11e40700 {
reg = <0 0x11e40700 0 0x900>;
#phy-cells = <1>;
};
};
i2c0: i2c@11f00000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
};
i2c6: i2c@11f01000 {
compatible = "mediatek,mt6873-i2c";
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
mediatek,use-open-drain;
i2c_lcd_bias_mtk:i2c_lcd_bias@3e {
compatible = "mediatek,i2c_lcd_bias";
reg = <0x3e>;
status = "okay";
};
};
imp_iic_wrap_n: imp_iic_wrap_n@11f02000 {
compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon";
reg = <0 0x11f02000 0 0x1000>;
#clock-cells = <1>;
};
msdc_top: msdc_top@11f10000 {
compatible = "mediatek,mt8192-msdc_top", "syscon";
reg = <0 0x11f10000 0 0x1000>;
#clock-cells = <1>;
};
msdc: msdc@11f60000 {
compatible = "mediatek,mt8192-msdc", "syscon";
reg = <0 0x11f60000 0 0x1000>;
#clock-cells = <1>;
};
mmc0: mmc@11f60000 {
compatible = "mediatek,mt6873-mmc", "mediatek,mt2712-mmc";
reg = <0 0x11f60000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&msdc_top CLK_MSDC_TOP_H_MST_0P>,
<&msdc_top CLK_MSDC_TOP_SRC_0P>,
<&msdc_top CLK_MSDC_TOP_P_MSDC0>,
<&msdc_top CLK_MSDC_TOP_AXI>,
<&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
clock-names = "source", "hclk", "source_cg",
"p_clk", "axi_clk", "ahb_clk";
};
mmc1: mmc@11f70000 {
compatible = "mediatek,mt6873-mmc", "mediatek,mt2712-mmc";
reg = <0 0x11f70000 0 0x1000>,
<0 0x11c70000 0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&msdc_top CLK_MSDC_TOP_H_MST_1P>,
<&msdc_top CLK_MSDC_TOP_SRC_1P>,
<&msdc_top CLK_MSDC_TOP_P_MSDC1>,
<&msdc_top CLK_MSDC_TOP_AXI>,
<&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
clock-names = "source", "hclk", "source_cg",
"p_clk", "axi_clk", "ahb_clk";
};
mali: mali@13000000 {
compatible = "mediatek,mali", "arm,mali-valhall";
reg = <0 0x13000000 0 0x4000>;
interrupts =
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names =
"GPU",
"MMU",
"JOB",
"EVENT",
"PWR";
operating-points-v2 = <&gpu_mali_opp>;
#cooling-cells = <2>;
ged-supply = <&ged>;
};
gpu_mali_opp: opp-table0 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <807000000>;
opp-microvolt = <725000>;
};
opp01 {
opp-hz = /bits/ 64 <795000000>;
opp-microvolt = <718750>;
};
opp02 {
opp-hz = /bits/ 64 <778300000>;
opp-microvolt = <712500>;
};
opp03 {
opp-hz = /bits/ 64 <772000000>;
opp-microvolt = <706250>;
};
opp04 {
opp-hz = /bits/ 64 <760000000>;
opp-microvolt = <700000>;
};
opp05 {
opp-hz = /bits/ 64 <748000000>;
opp-microvolt = <693750>;
};
opp06 {
opp-hz = /bits/ 64 <736000000>;
opp-microvolt = <687500>;
};
opp07 {
opp-hz = /bits/ 64 <724000000>;
opp-microvolt = <681250>;
};
opp08 {
opp-hz = /bits/ 64 <712000000>;
opp-microvolt = <675000>;
};
opp09 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <668750>;
};
opp10 {
opp-hz = /bits/ 64 <688000000>;
opp-microvolt = <662500>;
};
opp11 {
opp-hz = /bits/ 64 <667000000>;
opp-microvolt = <656250>;
};
opp12 {
opp-hz = /bits/ 64 <647000000>;
opp-microvolt = <650000>;
};
opp13 {
opp-hz = /bits/ 64 <626000000>;
opp-microvolt = <643750>;
};
opp14 {
opp-hz = /bits/ 64 <605000000>;
opp-microvolt = <637500>;
};
opp15 {
opp-hz = /bits/ 64 <585000000>;
opp-microvolt = <631250>;
};
opp16 {
opp-hz = /bits/ 64 <564000000>;
opp-microvolt = <625000>;
};
opp17 {
opp-hz = /bits/ 64 <543000000>;
opp-microvolt = <618750>;
};
opp18 {
opp-hz = /bits/ 64 <523000000>;
opp-microvolt = <612500>;
};
opp19 {
opp-hz = /bits/ 64 <502000000>;
opp-microvolt = <606250>;
};
opp20 {
opp-hz = /bits/ 64 <482000000>;
opp-microvolt = <600000>;
};
opp21 {
opp-hz = /bits/ 64 <461000000>;
opp-microvolt = <593750>;
};
opp22 {
opp-hz = /bits/ 64 <440000000>;
opp-microvolt = <587500>;
};
opp23 {
opp-hz = /bits/ 64 <420000000>;
opp-microvolt = <581250>;
};
opp24 {
opp-hz = /bits/ 64 <399000000>;
opp-microvolt = <575000>;
};
opp25 {
opp-hz = /bits/ 64 <378000000>;
opp-microvolt = <568750>;
};
opp26 {
opp-hz = /bits/ 64 <358000000>;
opp-microvolt = <562500>;
};
};
mali_dvfs_hint@13fbb000 {
compatible = "mediatek,mali_dvfs_hint", "syscon";
reg = <0 0x13fbb000 0 0x1000>;
#clock-cells = <1>;
};
g3d_secure_reg@13fbc000 {
compatible = "mediatek,g3d_secure_reg";
reg = <0 0x13fbc000 0 0x1000>;
};
g3d_testbench@13fbd000 {
compatible = "mediatek,g3d_testbench", "syscon";
reg = <0 0x13fbd000 0 0x1000>;
#clock-cells = <1>;
};
g3d_config: g3d_config@13fbf000 {
compatible = "mediatek,g3d_config", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
gpufreq: gpufreq {
compatible = "mediatek,gpufreq";
clocks =
<&topckgen CLK_TOP_MFG_PLL_SEL>,
<&apmixedsys CLK_APMIXED_MFGPLL>,
<&topckgen CLK_TOP_MFG_REF_SEL>,
<&mfgcfg CLK_MFG_BG3D>;
clock-names =
"clk_mux", /* switch main/sub */
"clk_main_parent", /* main pll freq */
"clk_sub_parent", /* default 218.4 MHz */
"subsys_bg3d";
nvmem-cells = <&efuse_segment &apu_pod19>;
nvmem-cell-names = "efuse_segment_cell", "efuse_pod19";
};
gpufreq_mfg2: gpufreq_mfg2 {
compatible = "mediatek,mt6873-mfg2",
"mediatek,gpufreq";
power-domains = <&scpsys MT6873_POWER_DOMAIN_MFG2>;
};
gpufreq_mfg3: gpufreq_mfg3 {
compatible = "mediatek,mt6873-mfg3",
"mediatek,gpufreq";
power-domains = <&scpsys MT6873_POWER_DOMAIN_MFG3>;
};
gpufreq_mfg4: gpufreq_mfg4 {
compatible = "mediatek,mt6873-mfg4",
"mediatek,gpufreq";
power-domains = <&scpsys MT6873_POWER_DOMAIN_MFG4>;
};
gpufreq_mfg5: gpufreq_mfg5 {
compatible = "mediatek,mt6873-mfg5",
"mediatek,gpufreq";
power-domains = <&scpsys MT6873_POWER_DOMAIN_MFG5>;
};
gpufreq_mfg6: gpufreq_mfg6 {
compatible = "mediatek,mt6873-mfg6",
"mediatek,gpufreq";
power-domains = <&scpsys MT6873_POWER_DOMAIN_MFG6>;
};
ged: ged {
compatible = "mediatek,ged";
gpufreq-supply = <&gpufreq>;
};
mfgcfg: mfgcfg@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
opp_table_disp: opp-table-disp {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <725000>;
};
};
opp_table_cam: opp-table-cam {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <392000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <499000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <725000>;
};
};
opp_table_img: opp-table-img {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <229000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <343000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <725000>;
};
};
opp_table_img2: opp-table-img2 {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <229000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <343000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <725000>;
};
};
opp_table_dpe: opp-table-dpe {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <249000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <364000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <725000>;
};
};
opp_table_ipe: opp-table-ipe {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <229000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <725000>;
};
};
opp_table_venc: opp-table-venc {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <249000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <364000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <725000>;
};
};
opp_table_vdec: opp-table-vdec {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <218000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <725000>;
};
};
opp_table_mdp: opp-table-mdp {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <229000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <343000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <725000>;
};
};
opp_table_ccu: opp-table-ccu {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <229000000>;
opp-microvolt = <575000>;
};
opp-1 {
opp-hz = /bits/ 64 <364000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <392000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <499000000>;
opp-microvolt = <725000>;
};
};
mmdvfs {
compatible = "mediatek,mmdvfs";
operating-points-v2 = <&opp_table_disp>;
mediatek,support_mux = "disp", "cam",
"img", "img2", "dpe",
"ipe","venc", "vdec",
"mdp", "ccu";
mediatek,mux_disp = "TOP_UNIVPLL_D6_D2",
"TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_MAINPLL_D4";
mediatek,mux_cam = "TOP_MAINPLL_D4_D2",
"TOP_MMPLL_D7", "TOP_UNIVPLL_D5",
"TOP_UNIVPLL_D4";
mediatek,mux_img = "TOP_MMPLL_D5_D2",
"TOP_MMPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_UNIVPLL_D4";
mediatek,mux_img2 = "TOP_MMPLL_D5_D2",
"TOP_MMPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_UNIVPLL_D4";
mediatek,mux_dpe = "TOP_UNIVPLL_D5_D2",
"TOP_MAINPLL_D6", "TOP_MMPLL_D6",
"TOP_MAINPLL_D4";
mediatek,mux_ipe = "TOP_MMPLL_D5_D2",
"TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_MAINPLL_D4";
mediatek,mux_venc = "TOP_UNIVPLL_D5_D2",
"TOP_MAINPLL_D6", "TOP_MMPLL_D6",
"TOP_UNIVPLL_D4";
mediatek,mux_vdec = "TOP_MAINPLL_D5_D2",
"TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_MAINPLL_D4";
mediatek,mux_mdp = "TOP_MMPLL_D5_D2",
"TOP_MMPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_TVDPLL_CK";
mediatek,mux_ccu = "TOP_MMPLL_D5_D2",
"TOP_MAINPLL_D6", "TOP_MMPLL_D7",
"TOP_UNIVPLL_D5";
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
mediatek,support_hopping = "clk_mmpll_ck";
mediatek,hopping_clk_mmpll_ck = <2290000000 2750000000
2750000000 2750000000>;
mediatek,action = <1>;
clocks = <&topckgen CLK_TOP_DISP_SEL>, /* 0 */
<&topckgen CLK_TOP_CAM_SEL>, /* 1 */
<&topckgen CLK_TOP_IMG1_SEL>, /* 2 */
<&topckgen CLK_TOP_IMG2_SEL>, /* 3 */
<&topckgen CLK_TOP_DPE_SEL>, /* 4 */
<&topckgen CLK_TOP_IPE_SEL>, /* 5 */
<&topckgen CLK_TOP_VENC_SEL>, /* 6 */
<&topckgen CLK_TOP_VDEC_SEL>, /* 7 */
<&topckgen CLK_TOP_MDP_SEL>, /* 8 */
<&topckgen CLK_TOP_CCU_SEL>, /* 9 */
<&topckgen CLK_TOP_MAINPLL_D4>, /* 10 */
<&topckgen CLK_TOP_UNIVPLL_D6>, /* 11 */
<&topckgen CLK_TOP_UNIVPLL_D4_D2>, /* 12 */
<&topckgen CLK_TOP_UNIVPLL_D6_D2>, /* 13 */
<&topckgen CLK_TOP_UNIVPLL_D4>, /* 14 */
<&topckgen CLK_TOP_UNIVPLL_D5>, /* 15 */
<&topckgen CLK_TOP_MMPLL_D7>, /* 16 */
<&topckgen CLK_TOP_MAINPLL_D4_D2>, /* 17 */
<&topckgen CLK_TOP_MMPLL_D4_D2>, /* 18 */
<&topckgen CLK_TOP_MMPLL_D5_D2>, /* 19 */
<&topckgen CLK_TOP_MMPLL_D6>, /* 20 */
<&topckgen CLK_TOP_MAINPLL_D6>, /* 21 */
<&topckgen CLK_TOP_UNIVPLL_D5_D2>, /* 22 */
<&topckgen CLK_TOP_MAINPLL_D5_D2>, /* 23 */
<&topckgen CLK_TOP_TVDPLL>, /* 24 */
<&apmixedsys CLK_APMIXED_MMPLL>;
clock-names = "disp", /* 0 */
"cam", /* 1 */
"img", /* 2 */
"img2", /* 3 */
"dpe", /* 4 */
"ipe", /* 5 */
"venc", /* 6 */
"vdec", /* 7 */
"mdp", /* 8 */
"ccu", /* 9 */
"TOP_MAINPLL_D4", /* 10 */
"TOP_UNIVPLL_D6", /* 11 */
"TOP_UNIVPLL_D4_D2", /* 12 */
"TOP_UNIVPLL_D6_D2", /* 13 */
"TOP_UNIVPLL_D4", /* 14 */
"TOP_UNIVPLL_D5", /* 15 */
"TOP_MMPLL_D7", /* 16 */
"TOP_MAINPLL_D4_D2", /* 17 */
"TOP_MMPLL_D4_D2", /* 18 */
"TOP_MMPLL_D5_D2", /* 19 */
"TOP_MMPLL_D6", /* 20 */
"TOP_MAINPLL_D6", /* 21 */
"TOP_UNIVPLL_D5_D2", /* 22 */
"TOP_MAINPLL_D5_D2", /* 23 */
"TOP_TVDPLL_CK", /* 24 */
"clk_mmpll_ck";
};
mmsys: mmsys@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
smi_common: smi@14002000 {
compatible = "mediatek,mt6873-smi-common", "syscon";
reg = <0 0x14002000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "apb", "smi", "gals0", "gals1";
};
larb0: larb@14003000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x14003000 0 0x1000>;
mediatek,larb-id = <0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>;
clock-names = "apb", "smi", "gals0";
};
larb1: larb@14004000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x14004000 0 0x1000>;
mediatek,larb-id = <1>;
init-power-on;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>;
clock-names = "apb", "smi", "gals0";
};
mmqos: interconnect {
compatible = "mediatek,mt6873-mmqos";
#interconnect-cells = <1>;
mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
&larb5 &larb7 &larb9 &larb11
&larb13 &larb14 &larb16 &larb17
&larb18 &larb19 &larb20>;
mediatek,commons = <&smi_common>;
clocks = <&topckgen CLK_TOP_DISP_SEL>;
clock-names = "mm";
interconnects = <&dvfsrc MT6873_MASTER_MMSYS &dvfsrc MT6873_SLAVE_DDR_EMI>,
<&dvfsrc MT6873_MASTER_HRT_MMSYS
&dvfsrc MT6873_SLAVE_HRT_DDR_EMI>,
<&mmqos MASTER_COMMON_PORT(0, 0) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 1) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 4) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 2) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 2) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 3) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 5) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 5) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 7) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 6) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 6) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 7) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 7) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 5) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_COMMON_PORT(0, 5) &mmqos SLAVE_COMMON(0)>;
interconnect-names = "icc-bw", "icc-hrt-bw", "larb0", "larb1", "larb2",
"larb4", "larb5", "larb7", "larb9", "larb11",
"larb13", "larb14", "larb16", "larb17", "larb18",
"larb19", "larb20";
};
mtk_iommu_debug {
compatible = "mediatek,mt6873-iommu-debug";
};
iommu0: iommu@1401d000 {
compatible = "mediatek,mt6873-m4u";
reg = <0 0x1401d000 0 0x1000>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,larbs = <&larb0 &larb1 &larb2
&larb4 &larb5 &larb7
&larb9 &larb11 &larb13
&larb14 &larb16 &larb17
&larb18 &larb19 &larb20>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "bclk";
#iommu-cells = <1>;
};
disp_smi_2x1_sub_common_u0@14022000 {
compatible = "mediatek,disp_smi_2x1_sub_common_u0",
"mediatek,mt6873-smi-common";
reg = <0 0x14022000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "apb", "smi", "gals0", "gals1";
};
disp_smi_2x1_sub_common_u1@14023000 {
compatible = "mediatek,disp_smi_2x1_sub_common_u1",
"mediatek,mt6873-smi-common";
reg = <0 0x14023000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "apb", "smi", "gals0", "gals1";
};
img0_smi_2x1_sub_common@14024000 {
compatible = "mediatek,img0_smi_2x1_sub_common",
"mediatek,mt6873-smi-common";
reg = <0 0x14024000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_GALS>;
clock-names = "apb", "smi", "gals0", "gals1";
};
img1_smi_2x1_sub_common@14025000 {
compatible = "mediatek,img1_smi_2x1_sub_common",
"mediatek,mt6873-smi-common";
reg = <0 0x14025000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_GALS>;
clock-names = "apb", "smi", "gals0", "gals1";
};
imgsys: imgsys@15020000 {
compatible = "mediatek,mt8192-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
imgsys_config: imgsys_config@15020000 {
compatible = "mediatek,imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
mediatek,larb = <&larb9>, <&larb11>;
iommus = <&iommu0 M4U_PORT_L9_IMG_IMGI_D1>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_D1>,
<&iommu0 M4U_PORT_L9_IMG_DMGI_D1>,
<&iommu0 M4U_PORT_L9_IMG_DEPI_D1>,
<&iommu0 M4U_PORT_L9_IMG_ICE_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_D2>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_D1>,
<&iommu0 M4U_PORT_L9_IMG_CRZO_D1>,
<&iommu0 M4U_PORT_L9_IMG_IMG3O_D1>,
<&iommu0 M4U_PORT_L9_IMG_VIPI_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_D5>,
<&iommu0 M4U_PORT_L9_IMG_TIMGO_D1>,
<&iommu0 M4U_PORT_L9_IMG_UFBC_W0>,
<&iommu0 M4U_PORT_L9_IMG_UFBC_R0>,
<&iommu0 M4U_PORT_L11_IMG_IMGI_D1>,
<&iommu0 M4U_PORT_L11_IMG_IMGBI_D1>,
<&iommu0 M4U_PORT_L11_IMG_DMGI_D1>,
<&iommu0 M4U_PORT_L11_IMG_DEPI_D1>,
<&iommu0 M4U_PORT_L11_IMG_ICE_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTI_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTO_D2>,
<&iommu0 M4U_PORT_L11_IMG_SMTO_D1>,
<&iommu0 M4U_PORT_L11_IMG_CRZO_D1>,
<&iommu0 M4U_PORT_L11_IMG_IMG3O_D1>,
<&iommu0 M4U_PORT_L11_IMG_VIPI_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTI_D5>,
<&iommu0 M4U_PORT_L11_IMG_TIMGO_D1>,
<&iommu0 M4U_PORT_L11_IMG_UFBC_W0>,
<&iommu0 M4U_PORT_L11_IMG_UFBC_R0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1>,
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_WPE_WDMA>;
clocks =
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_DIP>,
<&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_MSS>,
<&imgsys2 CLK_IMG2_MFB>;
clock-names =
"DIP_CG_IMG_LARB9",
"DIP_CG_IMG_DIP",
"DIP_CG_IMG_LARB11",
"DIP_CG_IMG_DIP_MSS",
"DIP_CG_IMG_MFB_DIP";
};
dip_a0@15021000 {
compatible = "mediatek,dip1";
reg = <0 0x15021000 0 0xc000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
};
dip_a1@15022000 {
compatible = "mediatek,dip_a1";
reg = <0 0x15022000 0 0x1000>;
};
dip_a2@15023000 {
compatible = "mediatek,dip_a2";
reg = <0 0x15023000 0 0x1000>;
};
dip_a3@15024000 {
compatible = "mediatek,dip_a3";
reg = <0 0x15024000 0 0x1000>;
};
dip_a4@15025000 {
compatible = "mediatek,dip_a4";
reg = <0 0x15025000 0 0x1000>;
};
dip_a5@15026000 {
compatible = "mediatek,dip_a5";
reg = <0 0x15026000 0 0x1000>;
};
dip_a6@15027000 {
compatible = "mediatek,dip_a6";
reg = <0 0x15027000 0 0x1000>;
};
dip_a7@15028000 {
compatible = "mediatek,dip_a7";
reg = <0 0x15028000 0 0x1000>;
};
dip_a8@15029000 {
compatible = "mediatek,dip_a8";
reg = <0 0x15029000 0 0x1000>;
};
dip_a9@1502a000 {
compatible = "mediatek,dip_a9";
reg = <0 0x1502a000 0 0x1000>;
};
larb9: larb@1502e000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1502e000 0 0x1000>;
mediatek,larb-id = <9>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_ISP>;
clocks = <&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_LARB9>;
clock-names = "apb", "smi";
};
mssdl@15812000 {
compatible = "mediatek,mssdl";
reg = <0 0x15812000 0 0x1000>;
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
};
msfdl@15810000 {
compatible = "mediatek,msfdl";
reg = <0 0x15810000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
};
msf_b@15810000 {
compatible = "mediatek,msf_b";
reg = <0 0x15810000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
mboxes = <&gce 18 0 CMDQ_THR_PRIO_1>;
msf_frame_done =
/bits/ 16 <CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC>;
msf_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_MSF>;
mediatek,larb = <&larb11>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_ISP2>;
clocks =
<&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_MSS>,
<&imgsys2 CLK_IMG2_MFB>,
<&imgsys2 CLK_IMG2_GALS>;
clock-names =
"MFB_CG_IMG2_LARB11",
"MFB_CG_IMG2_MSS",
"MFB_CG_IMG2_MFB",
"MFB_CG_IMG2_GALS";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus =
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1>;
};
wpe_a@15811000 {
compatible = "mediatek,wpe_a";
reg = <0 0x15811000 0 0x1000>;
mediatek,larb = <&larb11>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_ISP2>;
clocks =
<&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_WPE>;
clock-names =
"WPE_CLK_IMG_LARB9",
"WPE_CLK_IMG_WPE_A";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus =
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_WPE_WDMA>;
};
mss_b@15812000 {
compatible = "mediatek,mss_b";
reg = <0 0x15812000 0 0x1000>;
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
mboxes = <&gce 17 0 CMDQ_THR_PRIO_1>;
mss_frame_done =
/bits/ 16 <CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC>;
mss_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_MSS>;
};
imgsys_mfb_b@15820000 {
compatible = "mediatek,imgsys_mfb_b";
reg = <0 0x15820000 0 0x1000>;
};
imgsys2: imgsys2@15820000 {
compatible = "mediatek,mt8192-imgsys2", "syscon";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
imgsys2_config: imgsys2_config@15820000 {
compatible = "mediatek,imgsys2", "syscon";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
larb11: larb@1582e000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1582e000 0 0x1000>;
mediatek,larb-id = <11>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_ISP2>;
clocks = <&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_LARB11>;
clock-names = "apb", "smi";
};
vcu: vcu@16000000 {
compatible = "mediatek-vcu";
mediatek,vcuid = <0>;
mediatek,vcuname = "vcu";
reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */
<0 0x17020000 0 0x10000>, /* VENC_BASE */
<0 0x17820000 0 0x10000>; /* VENC_C1_BASE */
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
mediatek,mailbox-gce = <&gce>;
mediatek,dec_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/
mediatek,enc_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/
mboxes = <&gce 7 0 CMDQ_THR_PRIO_1>,
<&gce 12 0 CMDQ_THR_PRIO_1>;
gce-event-names = "venc_eof",
"venc_wp_2nd_done", "venc_wp_3nd_done",
"vdec_pic_start", "vdec_decode_done", "vdec_pause",
"vdec_dec_error", "vdec_mc_busy_overflow_timeout",
"vdec_all_dram_req_done", "vdec_ini_fetch_rdy",
"vdec_process_flag", "vdec_search_start_code_done",
"vdec_ref_reorder_done", "vdec_wp_tble_done",
"vdec_count_sram_clr_done", "vdec_gce_cnt_op_threshold",
"vdec_lat_pic_start", "vdec_lat_decode_done",
"vdec_lat_pause", "vdec_lat_dec_error",
"vdec_lat_mc_busy_overflow_timeout",
"vdec_lat_all_dram_req_done", "vdec_lat_ini_fetch_rdy",
"vdec_lat_process_flag",
"vdec_lat_search_start_code_done",
"vdec_lat_ref_reorder_done", "vdec_lat_wp_tble_done",
"vdec_lat_count_sram_clr_done",
"vdec_lat_gce_cnt_op_threshold";
gce-events = <&gce CMDQ_EVENT_VENC_CMDQ_FRAME_DONE>,
<&gce CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE>,
<&gce CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE>,
<&gce CMDQ_EVENT_VDEC_CORE0_SOF_0>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5>,
<&gce CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6>,
<&gce CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0>,
<&gce CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1>,
<&gce CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2>,
<&gce CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3>,
<&gce CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7>,
<&gce CMDQ_EVENT_VDEC_LAT_SOF_0>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5>,
<&gce CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6>,
<&gce CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0>,
<&gce CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1>,
<&gce CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2>,
<&gce CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3>,
<&gce CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7>;
gce-gpr = <GCE_GPR_R10>, <GCE_GPR_R11>;
};
vdec@16000000 {
compatible = "mediatek,mt6873-vcodec-dec";
mediatek,platform = "platform:mt6873";
mediatek,ipm = <2>;
reg = <0 0x16000000 0 0x1000>, /* VDEC_SYS */
<0 0x16020000 0 0x1000>, /* VDEC_VLD */
<0 0x16025000 0 0x4000>, /* VDEC_MISC */
<0 0x16010000 0 0x7000>, /* VDEC_LAT_MISC */
<0 0x16004000 0 0x1000>; /* VDEC_RACING_CTRL */
reg-names =
"VDEC_SYS",
"VDEC_VLD",
"VDEC_MISC",
"VDEC_LAT_MISC",
"VDEC_RACING_CTRL";
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
mediatek,larbs = <&larb4 &larb5>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VDEC>,
<&scpsys MT6873_POWER_DOMAIN_VDEC2>;
mediatek,vcu = <&vcu>;
clocks =
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys CLK_VDEC_VDEC>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_UNIVPLL_D4_D2>;
clock-names =
"CORE_MT_CG_SOC",
"CORE_MT_CG_VDEC0",
"LAT_MT_CG_VDEC1",
"MAIN_MT_CG_VDEC_SEL",
"MAIN_MT_VDEC_TOP";
//parent: MAIN_MT_VDEC_TOP child: MAIN_MT_CG_VDEC_SEL
mediatek,clock-parents = <4 3>;
operating-points-v2 = <&opp_table_vdec>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_MC_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_UFO_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PP_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_RD_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_WR_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PPWRAP_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_TILE_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD2_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_AVC_MV_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT)
&mmqos SLAVE_LARB(4)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_VLD_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_VLD2_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_TILE_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_WDMA_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT)
&mmqos SLAVE_LARB(5)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_VDEC_UFO_ENC_EXT)
&mmqos SLAVE_LARB(5)>;
interconnect-names = "path_vdec_mc", "path_vdec_ufo",
"path_vdec_pp", "path_vdec_pred_rd",
"path_vdec_pred_wr", "path_vdec_ppwrap",
"path_vdec_tile", "path_vdec_vld",
"path_vdec_vld2", "path_vdec_avc_mv",
"path_vdec_rg_ctrl_dma",
"path_lat0_vld", "path_lat0_vld2",
"path_lat0_avc_mv", "path_lat0_pred_rd",
"path_lat0_tile", "path_lat0_wdma",
"path_lat0_rg_ctrl", "path_vdec_ufo_enc";
};
vdec_smi_subcom@1600a000 {
compatible = "mediatek,vdec_smi_subcom",
"mediatek,mt6873-smi-common";
reg = <0 0x1600a000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi", "gals0", "gals1";
};
larb5: larb@1600d000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1600d000 0 0x1000>;
mediatek,larb-id = <5>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi";
};
vdecsys_soc: vdecsys_soc@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: vdecsys@1602f000 {
compatible = "mediatek,mt8192-vdecsys", "syscon";
reg = <0 0x1602f000 0 0x1000>;
#clock-cells = <1>;
};
larb4: larb@1602e000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1602e000 0 0x1000>;
mediatek,larb-id = <4>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_LARB1>;
clock-names = "apb", "smi";
};
vencsys: vencsys@17000000 {
compatible = "mediatek,mt8192-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
venc@17000000 {
compatible = "mediatek,mt6873-vcodec-enc";
mediatek,platform = "platform:mt6873";
mediatek,ipm = <2>;
reg = <0 0x17020000 0 0x2000>, /* VENC_SYS */
<0 0x17000000 0 0x10000>; /* VENC_C1_SYS */
reg-names =
"VENC_SYS",
"VENC_C1_SYS";
iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
<&iommu0 M4U_PORT_L7_VENC_REC>,
<&iommu0 M4U_PORT_L7_VENC_BSDMA>,
<&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
<&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
<&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
mediatek,larbs = <&larb7>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VENC>;
mediatek,vcu = <&vcu>;
clocks = <&vencsys CLK_VENC_SET1_VENC>;
clock-names =
"MT_CG_VENC0";
operating-points-v2 = <&opp_table_venc>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_R_LUMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_W_LUMA)
&mmqos SLAVE_LARB(7)>;
interconnect-names = "path_venc_rcpu", "path_venc_rec",
"path_venc_bsdma", "path_venc_sv_comv",
"path_venc_rd_comv", "path_venc_cur_luma",
"path_venc_cur_chroma", "path_venc_ref_luma",
"path_venc_ref_chroma", "path_venc_sub_r_luma",
"path_venc_sub_w_luma";
};
larb7: larb@17010000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x17010000 0 0x1000>;
mediatek,larb-id = <7>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_SET0_LARB>,
<&vencsys CLK_VENC_SET1_VENC>;
clock-names = "apb", "smi";
};
jpgenc@17030000 {
compatible = "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x10000>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_SET2_JPGENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT6873_POWER_DOMAIN_VENC>;
mediatek,larb = <&larb7>;
dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA>,
<&iommu0 M4U_PORT_L7_JPGENC_Q_RDMA>,
<&iommu0 M4U_PORT_L7_JPGENC_C_TABLE>,
<&iommu0 M4U_PORT_L7_JPGENC_BSDMA>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_RDMA)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_TABLE)
&mmqos SLAVE_LARB(7)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA)
&mmqos SLAVE_LARB(7)>;
interconnect-names = "path_jpegenc_y_rdma",
"path_jpegenc_c_rmda",
"path_jpegenc_q_table",
"path_jpegenc_bsdma";
operating-points-v2 = <&opp_table_venc>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
};
btcvsd_snd: mtk-btcvsd-snd@18050000 {
compatible = "mediatek,mtk-btcvsd-snd";
reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
<0 0x18080000 0 0x14000>; /*SRAM_BANK2*/
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,infracfg = <&infracfg>;
/*INFRA MISC, conn_bt_cvsd_mask*/
/*cvsd_mcu_read, write, packet_indicator*/
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
disable_write_silence = <1>;
};
iommu1: iommu@19010000 {
compatible = "mediatek,mt6873-apu-iommu";
reg = <0 0x19010000 0 0x1000>;
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,apu_power = <&apusys_power>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_APU>;
#iommu-cells = <1>;
};
apu_iommu_data: apu_iommu_data {
compatible = "mediatek,apu_iommu_data";
dma-ranges = <0x3 0x0 0x3 0x0 0x1 0x0>;
iommus = <&iommu1 M4U_PORT_L22_APU_DATA>;
};
apu_conn: apu_conn@19020000 {
compatible = "mediatek,mt8192-apu_conn", "syscon";
reg = <0 0x19020000 0 0x1000>;
#clock-cells = <1>;
};
apusys_reviser@19021000 {
compatible = "mediatek, mt6873-reviser";
reg = <0 0x19021000 0 0x1000>, /* apu_sctrl_reviser */
<0 0x1d800000 0 0x200000>, /* VLM */
<0 0x1d000000 0 0x100000>, /* TCM */
<0 0x19001000 0 0x1000>; /* apusys int */
interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>;
default-dram = <0x4000000>;
boundary = <0x3>;
dma-ranges = <0x3 0x0 0x3 0x0 0x1 0x0>;
iommus = <&iommu1 M4U_PORT_L22_APU_VLM>;
};
edma0: edma0@19027000 {
compatible = "mtk,edma-sub-v20";
reg = <0x0 0x19027000 0x0 0x1000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 0>;
};
edma: edma {
compatible = "mtk,edma";
sub_nr = <1>;
mediatek,edma-sub = <&edma0>;
};
apu_vcore: apu_vcore@19029000 {
compatible = "mediatek,mt8192-apu_vcore", "syscon";
reg = <0 0x19029000 0 0x1000>;
#clock-cells = <1>;
};
apu0: apu0@19030000 {
compatible = "mediatek,mt8192-apu0", "syscon";
reg = <0 0x19030000 0 0x1000>;
#clock-cells = <1>;
};
vpu_core0: vpu_core0@19030000 {
compatible = "mediatek,mt6873-vpu_core";
reg = <0 0x19030000 0 0x1000>,
<0 0x1d100000 0 0x40000>,
<0 0x1d140000 0 0x30000>,
<0 0x0d190000 0 0x4000>;
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>;
id = <0>;
reset-vector = <0x7da00000 0x00100000 0x0>;
main-prog = <0x7db00000 0x00300000 0x100000>;
kernel-lib = <0x7de00000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
dma-ranges = <0x3 0x0 0x3 0x0 0x1 0x0>;
iommus = <&iommu1 M4U_PORT_L22_APU_VPU>;
};
apu1: apu1@19031000 {
compatible = "mediatek,mt8192-apu1", "syscon";
reg = <0 0x19031000 0 0x1000>;
#clock-cells = <1>;
};
vpu_core1: vpu_core1@19031000 {
compatible = "mediatek,mt6873-vpu_core";
reg = <0 0x19031000 0 0x1000>,
<0 0x1d200000 0 0x40000>,
<0 0x1d240000 0 0x30000>,
<0 0x0d194000 0 0x4000>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>;
id = <1>;
reset-vector = <0x7e300000 0x00100000 0x400000>;
main-prog = <0x7e400000 0x00300000 0x500000>;
kernel-lib = <0x7e700000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
dma-ranges = <0x3 0x0 0x3 0x0 0x1 0x0>;
iommus = <&iommu1 M4U_PORT_L22_APU_VPU>;
};
apu_mdla0: apu_mdla0@19034000 {
compatible = "mediatek,mt8192-apu_mdla0", "syscon";
reg = <0 0x19034000 0 0x1000>;
#clock-cells = <1>;
};
mtk_mdla: mdla@19036000 {
compatible = "mediatek, mt6873-mdla";
core_num = <1>;
reg = <0 0x19034000 0 0x1000>, /* dla0 config */
<0 0x19036000 0 0x1000>, /* dla0 command */
<0 0x19035000 0 0x1000>, /* dla0 biu */
<0 0x1d000000 0 0x100000>, /* GSM,TODO */
<0 0x19020000 0 0x40000>; /* APU CONN */
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH 0>;
};
apusys_mnoc: apusys_mnoc {
compatible = "mediatek,mt6873-mnoc";
reg = <0 0x1906e000 0 0xa000>, /* mnoc reg */
<0 0x19001000 0 0x1000>, /* apusys int */
<0 0x19020000 0 0x1000>, /* apu_conn_config */
<0 0x10001000 0 0x1000>, /* slp prot 1 */
<0 0x10215000 0 0x1000>; /* slp prot 2 */
interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&dvfsrc MT6873_MASTER_VPUSYS
&dvfsrc MT6873_SLAVE_DDR_EMI>;
interconnect-names = "apu-bw";
};
apusys_devapc@19064000 {
compatible = "mediatek,mt6873-apusys_devapc";
reg = <0 0x19064000 0 0x1000>;
interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>;
};
apusys_debug: apusys_debug {
compatible = "mediatek,mt6873-debug";
};
apu_top: apu_top@0x190f0000 {
compatible = "mediatek,apu_top";
reg = <0 0x190f0000 0 0x1000>;
vvpu-supply = <&mt6359p_vproc1_reg>;
vsram_apu-supply = <&mt6359p_vsram_md_reg>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_APU>;
clocks = <&topckgen CLK_TOP_DSP_SEL>, /* CONN */
<&topckgen CLK_TOP_IPU_IF_SEL>; /* VCORE */
clock-names = "clk_top_dsp_sel",
"clk_top_ipu_if_sel";
};
apusys_power: apusys_power@0x190f1000 {
compatible = "mediatek,apusys_power";
reg = <0 0x190f1000 0 0x1000>,
<0 0x190f0000 0 0x1000>,
<0 0x19029000 0 0x1000>;
reg-names = "apusys_pcu",
"apusys_rpc",
"apusys_vcore";
nvmem-cells = <&efuse_segment &apu_pod19 &apu_pod26>;
nvmem-cell-names = "efuse_segment", "efuse_pod19", "efuse_pod26";
vvpu-supply = <&mt6359p_vproc1_reg>;
vmdla-supply = <&mt6359p_vproc2_reg>;
vsram_apu-supply = <&mt6359p_vsram_md_reg>;
vcore-supply = <&dvfsrc_vcore>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_APU>;
clocks = <&topckgen CLK_TOP_DSP_SEL>, /* CONN */
<&topckgen CLK_TOP_DSP1_SEL>, /* VPU_CORE0 */
<&topckgen CLK_TOP_DSP1_NPUPLL_SEL>, /* VPU_CORE0 */
<&topckgen CLK_TOP_DSP2_SEL>, /* VPU_CORE1 */
<&topckgen CLK_TOP_DSP2_NPUPLL_SEL>, /* VPU_CORE1 */
<&topckgen CLK_TOP_DSP5_SEL>, /* MDLA0 */
<&topckgen CLK_TOP_DSP5_APUPLL_SEL>, /* MDLA0 */
<&topckgen CLK_TOP_IPU_IF_SEL>, /* VCORE */
<&apu0 CLK_APU0_JTAG>,
<&apu0 CLK_APU0_AXI_M>,
<&apu0 CLK_APU0_APU>,
<&apu1 CLK_APU1_JTAG>,
<&apu1 CLK_APU1_AXI_M>,
<&apu1 CLK_APU1_APU>,
<&apu_mdla0 CLK_APU_MDLA0_CG0>,
<&apu_mdla0 CLK_APU_MDLA0_CG1>,
<&apu_mdla0 CLK_APU_MDLA0_CG2>,
<&apu_mdla0 CLK_APU_MDLA0_CG3>,
<&apu_mdla0 CLK_APU_MDLA0_CG4>,
<&apu_mdla0 CLK_APU_MDLA0_CG5>,
<&apu_mdla0 CLK_APU_MDLA0_CG6>,
<&apu_mdla0 CLK_APU_MDLA0_CG7>,
<&apu_mdla0 CLK_APU_MDLA0_CG8>,
<&apu_mdla0 CLK_APU_MDLA0_CG9>,
<&apu_mdla0 CLK_APU_MDLA0_CG10>,
<&apu_mdla0 CLK_APU_MDLA0_CG11>,
<&apu_mdla0 CLK_APU_MDLA0_CG12>,
<&apu_mdla0 CLK_APU_MDLA0_APB>,
<&apu_mdla0 CLK_APU_MDLA0_AXI_M>,
<&apu_conn CLK_APU_CONN_AHB>,
<&apu_conn CLK_APU_CONN_AXI>,
<&apu_conn CLK_APU_CONN_ISP>,
<&apu_conn CLK_APU_CONN_CAM_ADL>,
<&apu_conn CLK_APU_CONN_IMG_ADL>,
<&apu_conn CLK_APU_CONN_EMI_26M>,
<&apu_conn CLK_APU_CONN_VPU_UDI>,
<&apu_conn CLK_APU_CONN_EDMA_0>,
<&apu_conn CLK_APU_CONN_EDMA_1>,
<&apu_conn CLK_APU_CONN_EDMAL_0>,
<&apu_conn CLK_APU_CONN_EDMAL_1>,
<&apu_conn CLK_APU_CONN_MNOC>,
<&apu_conn CLK_APU_CONN_TCM>,
<&apu_conn CLK_APU_CONN_MD32>,
<&apu_conn CLK_APU_CONN_IOMMU_0>,
<&apu_conn CLK_APU_CONN_MD32_32K>,
<&apu_vcore CLK_APU_VCORE_AHB>,
<&apu_vcore CLK_APU_VCORE_AXI>,
<&apu_vcore CLK_APU_VCORE_ADL>,
<&apu_vcore CLK_APU_VCORE_QOS>,
<&clk26m>,
<&topckgen CLK_TOP_MAINPLL_D4_D2>,
<&topckgen CLK_TOP_UNIVPLL_D4_D2>,
<&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_MMPLL_D6>,
<&topckgen CLK_TOP_MMPLL_D5>,
<&topckgen CLK_TOP_MMPLL_D4>,
<&topckgen CLK_TOP_UNIVPLL_D5>,
<&topckgen CLK_TOP_UNIVPLL_D4>,
<&topckgen CLK_TOP_UNIVPLL_D3>,
<&topckgen CLK_TOP_MAINPLL_D6>,
<&topckgen CLK_TOP_MAINPLL_D4>,
<&topckgen CLK_TOP_MAINPLL_D3>,
<&topckgen CLK_TOP_TVDPLL>,
<&topckgen CLK_TOP_APUPLL>,
<&topckgen CLK_TOP_NPUPLL>,
<&apmixedsys CLK_APMIXED_APUPLL>,
<&apmixedsys CLK_APMIXED_NPUPLL>;
clock-names = "clk_top_dsp_sel",
"clk_top_dsp1_sel",
"clk_top_dsp1_npupll_sel",
"clk_top_dsp2_sel",
"clk_top_dsp2_npupll_sel",
"clk_top_dsp5_sel",
"clk_top_dsp5_apupll_sel",
"clk_top_ipu_if_sel",
"clk_apu_core0_jtag_cg",
"clk_apu_core0_axi_m_cg",
"clk_apu_core0_apu_cg",
"clk_apu_core1_jtag_cg",
"clk_apu_core1_axi_m_cg",
"clk_apu_core1_apu_cg",
"clk_apu_mdla0_cg_b0",
"clk_apu_mdla0_cg_b1",
"clk_apu_mdla0_cg_b2",
"clk_apu_mdla0_cg_b3",
"clk_apu_mdla0_cg_b4",
"clk_apu_mdla0_cg_b5",
"clk_apu_mdla0_cg_b6",
"clk_apu_mdla0_cg_b7",
"clk_apu_mdla0_cg_b8",
"clk_apu_mdla0_cg_b9",
"clk_apu_mdla0_cg_b10",
"clk_apu_mdla0_cg_b11",
"clk_apu_mdla0_cg_b12",
"clk_apu_mdla0_apb_cg",
"clk_apu_mdla0_axi_m_cg",
"clk_apu_conn_ahb_cg",
"clk_apu_conn_axi_cg",
"clk_apu_conn_isp_cg",
"clk_apu_conn_cam_adl_cg",
"clk_apu_conn_img_adl_cg",
"clk_apu_conn_emi_26m_cg",
"clk_apu_conn_vpu_udi_cg",
"clk_apu_conn_edma_0_cg",
"clk_apu_conn_edma_1_cg",
"clk_apu_conn_edmal_0_cg",
"clk_apu_conn_edmal_1_cg",
"clk_apu_conn_mnoc_cg",
"clk_apu_conn_tcm_cg",
"clk_apu_conn_md32_cg",
"clk_apu_conn_iommu_0_cg",
"clk_apu_conn_md32_32k_cg",
"clk_apusys_vcore_ahb_cg",
"clk_apusys_vcore_axi_cg",
"clk_apusys_vcore_adl_cg",
"clk_apusys_vcore_qos_cg",
"clk_top_clk26m",
"clk_top_mainpll_d4_d2",
"clk_top_univpll_d4_d2",
"clk_top_univpll_d6_d2",
"clk_top_mmpll_d6",
"clk_top_mmpll_d5",
"clk_top_mmpll_d4",
"clk_top_univpll_d5",
"clk_top_univpll_d4",
"clk_top_univpll_d3",
"clk_top_mainpll_d6",
"clk_top_mainpll_d4",
"clk_top_mainpll_d3",
"clk_top_tvdpll_ck",
"clk_top_apupll_ck",
"clk_top_npupll_ck",
"clk_apmixed_apupll_rate",
"clk_apmixed_npupll_rate";
};
seninf1@1a004000 {
compatible = "mediatek,seninf1";
reg = <0 0x1a004000 0 0x1000>;
};
seninf2@1a005000 {
compatible = "mediatek,seninf2";
reg = <0 0x1a005000 0 0x1000>;
};
seninf3@1a006000 {
compatible = "mediatek,seninf3";
reg = <0 0x1a006000 0 0x1000>;
};
seninf4@1a007000 {
compatible = "mediatek,seninf4";
reg = <0 0x1a007000 0 0x1000>;
};
seninf5@1a008000 {
compatible = "mediatek,seninf5";
reg = <0 0x1a008000 0 0x1000>;
};
seninf6@1a009000 {
compatible = "mediatek,seninf6";
reg = <0 0x1a009000 0 0x1000>;
};
seninf7@1a00a000 {
compatible = "mediatek,seninf7";
reg = <0 0x1a00a000 0 0x1000>;
};
seninf8@1a00b000 {
compatible = "mediatek,seninf8";
reg = <0 0x1a00b000 0 0x1000>;
};
seninf_top:seninf_top@1a004000 {
compatible = "mediatek,seninf_top";
reg = <0 0x1a004000 0 0x1000>;
#if 0
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
#endif
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_SENINF>,
<&topckgen CLK_TOP_SENINF_SEL>,
<&topckgen CLK_TOP_SENINF1_SEL>,
<&topckgen CLK_TOP_SENINF2_SEL>,
<&topckgen CLK_TOP_SENINF3_SEL>,
<&topckgen CLK_TOP_CAMTG_SEL>,
<&topckgen CLK_TOP_CAMTG2_SEL>,
<&topckgen CLK_TOP_CAMTG3_SEL>,
<&topckgen CLK_TOP_CAMTG4_SEL>,
<&topckgen CLK_TOP_CAMTG5_SEL>,
<&topckgen CLK_TOP_CAMTG6_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_UNIVPLL_192M_D8>,
<&topckgen CLK_TOP_UNIVPLL_D6_D8>,
<&topckgen CLK_TOP_UNIVPLL_192M_D4>,
<&topckgen CLK_TOP_CSW_F26M_D2>,
<&topckgen CLK_TOP_UNIVPLL_192M_D16>,
<&topckgen CLK_TOP_UNIVPLL_192M_D32>;
clock-names = "CAMSYS_SENINF_CGPDN",
"TOP_MUX_SENINF",
"TOP_MUX_SENINF1",
"TOP_MUX_SENINF2",
"TOP_MUX_SENINF3",
"TOP_MUX_CAMTG",
"TOP_MUX_CAMTG2",
"TOP_MUX_CAMTG3",
"TOP_MUX_CAMTG4",
"TOP_MUX_CAMTG5",
"TOP_MUX_CAMTG6",
"TOP_CLK26M",
"TOP_UNIVP_192M_D8",
"TOP_UNIVPLL_D6_D8",
"TOP_UNIVP_192M_D4",
"TOP_F26M_CK_D2",
"TOP_UNIVP_192M_D16",
"TOP_UNIVP_192M_D32";
operating-points-v2 = <&opp_table_cam>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
};
kd_camera_hw1:kd_camera_hw1@1a004000 {
compatible = "mediatek,imgsensor";
};
camsys: camsys@1a000000 {
compatible = "mediatek,mt8192-camsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
cam_qos_legacy {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam_qos_legacy";
operating-points-v2 = <&opp_table_cam>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
};
cam_mem {
compatible = "mediatek,cam_mem";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = /* imgsys_config, msf_b and wpe */
<&iommu0 M4U_PORT_L9_IMG_IMGI_D1>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_D1>,
<&iommu0 M4U_PORT_L9_IMG_DMGI_D1>,
<&iommu0 M4U_PORT_L9_IMG_DEPI_D1>,
<&iommu0 M4U_PORT_L9_IMG_ICE_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_D2>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_D1>,
<&iommu0 M4U_PORT_L9_IMG_CRZO_D1>,
<&iommu0 M4U_PORT_L9_IMG_IMG3O_D1>,
<&iommu0 M4U_PORT_L9_IMG_VIPI_D1>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_D5>,
<&iommu0 M4U_PORT_L9_IMG_TIMGO_D1>,
<&iommu0 M4U_PORT_L9_IMG_UFBC_W0>,
<&iommu0 M4U_PORT_L9_IMG_UFBC_R0>,
<&iommu0 M4U_PORT_L11_IMG_IMGI_D1>,
<&iommu0 M4U_PORT_L11_IMG_IMGBI_D1>,
<&iommu0 M4U_PORT_L11_IMG_DMGI_D1>,
<&iommu0 M4U_PORT_L11_IMG_DEPI_D1>,
<&iommu0 M4U_PORT_L11_IMG_ICE_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTI_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTO_D2>,
<&iommu0 M4U_PORT_L11_IMG_SMTO_D1>,
<&iommu0 M4U_PORT_L11_IMG_CRZO_D1>,
<&iommu0 M4U_PORT_L11_IMG_IMG3O_D1>,
<&iommu0 M4U_PORT_L11_IMG_VIPI_D1>,
<&iommu0 M4U_PORT_L11_IMG_SMTI_D5>,
<&iommu0 M4U_PORT_L11_IMG_TIMGO_D1>,
<&iommu0 M4U_PORT_L11_IMG_UFBC_W0>,
<&iommu0 M4U_PORT_L11_IMG_UFBC_R0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4>,
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0>,
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1>,
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1>,
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0>,
<&iommu0 M4U_PORT_L11_IMG_WPE_WDMA>,
/* camsv */
<&iommu0 M4U_PORT_L13_CAM_CAMSV1>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV2>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV3>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV4>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV5>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV6>,
/* isp p1 */
<&iommu0 M4U_PORT_L16_CAM_IMGO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_IMGO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_LTMSO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_LTMSO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_RRZO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_RRZO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_LCESO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_LCESO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_AAHO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_AAHO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_AAO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_AAO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_AAO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_FLKO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_FLKO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_AFO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_AFO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_AFO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_RSSO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_RSSO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_CRZO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_CRZO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_YUVO_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_YUVO_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R2_A>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R2_C>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R3_A>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R3_C>,
<&iommu0 M4U_PORT_L16_CAM_BPCI_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_BPCI_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_CQI_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_CQI_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_CQI_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_LSCI_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_LSCI_R1_C>,
<&iommu0 M4U_PORT_L16_CAM_UFDI_R2_A>,
<&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B>,
<&iommu0 M4U_PORT_L18_CAM_UFDI_R2_C>,
/* rsc */
<&iommu0 M4U_PORT_L20_IPE_RSC_RDMA0>,
<&iommu0 M4U_PORT_L20_IPE_RSC_WDMA>;
mediatek,larbs =
<&larb9 &larb11 &larb20>;
};
camisp_legacy: camisp_legacy@1a000000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camisp_legacy";
reg = <0 0x1a000000 0 0x10000>;
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
#clock-cells = <1>;
/* Camera CCF */
power-domains = <&scpsys MT6873_POWER_DOMAIN_MDP>;
mediatek,larbs = <&larb13 &larb14>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAMTG>,
<&camsys CLK_CAM_CAMSV0>,
<&camsys CLK_CAM_CAMSV1>,
<&camsys CLK_CAM_CAMSV2>,
<&camsys CLK_CAM_CAMSV3>,
<&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_CCU0>,
<&camsys CLK_CAM_SENINF>,
<&camsys CLK_CAM_CAM2MM_GALS>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_rawa CLK_CAM_RAWA_CAM>,
<&camsys_rawa CLK_CAM_RAWA_CAMTG>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_rawb CLK_CAM_RAWB_CAM>,
<&camsys_rawb CLK_CAM_RAWB_CAMTG>,
<&camsys_rawc CLK_CAM_RAWC_LARBX>,
<&camsys_rawc CLK_CAM_RAWC_CAM>,
<&camsys_rawc CLK_CAM_RAWC_CAMTG>,
<&topckgen CLK_TOP_CCU_SEL>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "CAMSYS_CAM_CGPDN",
"CAMSYS_CAMTG_CGPDN",
"CAMSYS_CAMSV0_CGPDN",
"CAMSYS_CAMSV1_CGPDN",
"CAMSYS_CAMSV2_CGPDN",
"CAMSYS_CAMSV3_CGPDN",
"CAMSYS_LARB13_CGPDN",
"CAMSYS_LARB14_CGPDN",
"CAMSYS_CCU0_CGPDN",
"CAMSYS_SENINF_CGPDN",
"CAMSYS_MAIN_CAM2MM_GALS_CGPDN",
"CAMSYS_RAWALARB16_CGPDN",
"CAMSYS_RAWACAM_CGPDN",
"CAMSYS_RAWATG_CGPDN",
"CAMSYS_RAWBLARB17_CGPDN",
"CAMSYS_RAWBCAM_CGPDN",
"CAMSYS_RAWBTG_CGPDN",
"CAMSYS_RAWCLARB18_CGPDN",
"CAMSYS_RAWCCAM_CGPDN",
"CAMSYS_RAWCTG_CGPDN",
"TOPCKGEN_TOP_MUX_CCU",
"TOPCKGEN_TOP_MUX_CAMTM";
};
cam1_legacy@1a030000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam1_legacy";
reg = <0 0x1a030000 0 0x8000>;
interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWA>;
mediatek,larb = <&larb16>;
};
cam1_inner_legacy@1a038000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam1_inner_legacy";
reg = <0 0x1a038000 0 0x8000>;
};
camsys_rawa_legacy: camsys_rawa_legacy@1a04f000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsys_rawa_legacy";
reg = <0 0x1a04f000 0 0x1000>;
#clock-cells = <1>;
};
cam2_legacy@1a050000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam2_legacy";
reg = <0 0x1a050000 0 0x8000>;
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWB>;
mediatek,larb = <&larb17>;
};
cam2_inner_legacy@1a058000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam2_inner_legacy";
reg = <0 0x1a058000 0 0x8000>;
};
camsys_rawb_legacy: camsys_rawb_legacy@1a06f000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsys_rawb_legacy";
reg = <0 0x1a06f000 0 0x1000>;
#clock-cells = <1>;
};
cam3_legacy@1a070000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam3_legacy";
reg = <0 0x1a070000 0 0x8000>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWC>;
mediatek,larb = <&larb18>;
};
cam3_inner_legacy@1a078000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,cam3_inner_legacy";
reg = <0 0x1a078000 0 0x8000>;
};
camsys_rawc_legacy: camsys_rawc_legacy@1a08f000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsys_rawc_legacy";
reg = <0 0x1a08f000 0 0x1000>;
#clock-cells = <1>;
};
camsv1_legacy@1a090000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv1_legacy";
reg = <0 0x1a090000 0 0x1000>;
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv2_legacy@1a091000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv2_legacy";
reg = <0 0x1a091000 0 0x1000>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv3_legacy@1a092000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv3_legacy";
reg = <0 0x1a092000 0 0x1000>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv4_legacy@1a093000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv4_legacy";
reg = <0 0x1a093000 0 0x1000>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv5_legacy@1a094000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv5_legacy";
reg = <0 0x1a094000 0 0x1000>;
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv6_legacy@1a095000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv6_legacy";
reg = <0 0x1a095000 0 0x1000>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv7_legacy@1a096000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv7_legacy";
reg = <0 0x1a096000 0 0x1000>;
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
};
camsv8_legacy@1a097000 {
/* non-v4l2 legacy camera */
compatible = "mediatek,camsv8_legacy";
reg = <0 0x1a097000 0 0x1000>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
};
flashlight_core: flashlight_core {
compatible = "mediatek,flashlight_core";
};
mtk_composite_v4l2_1: mtk_composite_v4l2_1 {
compatible = "mediatek,mtk_composite_v4l2_1";
};
mtk_composite_v4l2_2: mtk_composite_v4l2_2 {
compatible = "mediatek,mtk_composite_v4l2_2";
};
larb13: larb@1a001000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1a001000 0 0x1000>;
mediatek,larb-id = <13>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_LARB13>;
clock-names = "apb", "smi";
};
larb14: larb@1a002000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1a002000 0 0x1000>;
mediatek,larb-id = <14>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_LARB14>;
clock-names = "apb", "smi";
};
cam_smi_subcom@1a00c000 {
compatible = "mediatek,cam_smi_subcom",
"mediatek,mt6873-smi-common";
reg = <0 0x1a00c000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>;
clock-names = "apb", "smi", "gals0", "gals1";
};
cam_smi_subcom@1a00d000 {
compatible = "mediatek,cam_smi_subcom",
"mediatek,mt6873-smi-common";
reg = <0 0x1a00d000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAM>;
clock-names = "apb", "smi", "gals0", "gals1";
};
larb16: larb@1a00f000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1a00f000 0 0x1000>;
mediatek,larb-id = <16>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWA>;
clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_rawa CLK_CAM_RAWA_CAM>;
clock-names = "apb", "smi";
};
larb17: larb@1a010000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1a010000 0 0x1000>;
mediatek,larb-id = <17>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWB>;
clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_rawb CLK_CAM_RAWB_CAM>;
clock-names = "apb", "smi";
};
larb18: larb@1a011000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1a011000 0 0x1000>;
mediatek,larb-id = <18>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWC>;
clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
<&camsys_rawc CLK_CAM_RAWC_CAM>;
clock-names = "apb", "smi";
};
camsys_rawa: camsys_rawa@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa", "syscon";
reg = <0 0x1a04f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawb: camsys_rawb@1a06f000 {
compatible = "mediatek,mt8192-camsys_rawb", "syscon";
reg = <0 0x1a06f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawc: camsys_rawc@1a08f000 {
compatible = "mediatek,mt8192-camsys_rawc", "syscon";
reg = <0 0x1a08f000 0 0x1000>;
#clock-cells = <1>;
};
remoteproc_ccd: remoteproc_ccd {
compatible = "mediatek,ccd";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L16_CAM_IMGO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_RRZO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_CQI_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_BPCI_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_YUVO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_UFDI_R2_A>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R2_A>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R3_A>,
<&iommu0 M4U_PORT_L16_CAM_AAO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_AFO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_FLKO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LCESO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_CRZO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LTMSO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_RSSO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_AAHO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LSCI_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_CQI_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B>,
<&iommu0 M4U_PORT_L17_CAM_AAO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_AFO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_IMGO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_RRZO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_CQI_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_BPCI_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_YUVO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_UFDI_R2_C>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R2_C>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R3_C>,
<&iommu0 M4U_PORT_L18_CAM_AAO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_AFO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_FLKO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LCESO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_CRZO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LTMSO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_RSSO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_AAHO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LSCI_R1_C>;
mediatek,larbs = <&larb16 &larb17 &larb18>;
reg = <0 0x1a030000 0 0x8000>,
<0 0x1a050000 0 0x8000>,
<0 0x1a070000 0 0x8000>;
status = "okay";
msg_dev {
mtk,rpmsg-name = "mtk_ccd_msgdev";
status = "okay";
};
};
camisp: camisp {
compatible = "mediatek,camisp";
mediatek,ccd = <&remoteproc_ccd>;
reg = <0 0x1a000000 0 0x1000>;
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L16_CAM_IMGO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_RRZO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_CQI_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_BPCI_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_YUVO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_UFDI_R2_A>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R2_A>,
<&iommu0 M4U_PORT_L16_CAM_RAWI_R3_A>,
<&iommu0 M4U_PORT_L16_CAM_AAO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_AFO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_FLKO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LCESO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_CRZO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LTMSO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_RSSO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_AAHO_R1_A>,
<&iommu0 M4U_PORT_L16_CAM_LSCI_R1_A>,
<&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_CQI_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B>,
<&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B>,
<&iommu0 M4U_PORT_L17_CAM_AAO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_AFO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B>,
<&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B>,
<&iommu0 M4U_PORT_L18_CAM_IMGO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_RRZO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_CQI_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_BPCI_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_YUVO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_UFDI_R2_C>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R2_C>,
<&iommu0 M4U_PORT_L18_CAM_RAWI_R3_C>,
<&iommu0 M4U_PORT_L18_CAM_AAO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_AFO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_FLKO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LCESO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_CRZO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LTMSO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_RSSO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_AAHO_R1_C>,
<&iommu0 M4U_PORT_L18_CAM_LSCI_R1_C>;
/* SCP_SYS_MDP */
power-domains = <&scpsys MT6873_POWER_DOMAIN_MDP>;
mediatek,larbs = <&larb16 &larb17 &larb18>;
operating-points-v2 = <&opp_table_cam>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
};
cam1@1a030000 {
compatible = "mediatek,isp6s-cam";
reg = <0 0x1a030000 0 0x8000>,
<0 0x1a038000 0 0x8000>;
reg-names = "reg";
mediatek,cam-id = <0>;
interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
#clock-cells = <1>;
/**
* Mapping to MTK's old style clk SCP_SYS_CAM_RAWA,
* connect to SCP_SYS_CAM, SCP_SYS_DIS
*/
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWA>;
mediatek,larb = <&larb16>;
/**
* Mapping to MTK's old style clk definition:
* CAMSYS_MAIN_CAM_CGPDN, CAMSYS_MAIN_CAMTG_CGPDN,
* CAMSYS_RAWA_LARBX_CGPDN, CAMSYS_RAWA_CAM_CGPDN,
* CAMSYS_RAWA_CAMTG_CGPDN, TOP_MUX_CAMTM
*/
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAMTG>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_rawa CLK_CAM_RAWA_CAM>,
<&camsys_rawa CLK_CAM_RAWA_CAMTG>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_cam_cgpdn",
"camsys_camtg_cgpdn",
"camsys-cama-larb-cgpdn",
"camsys-cama-cgpdn",
"camsys-camatg-cgpdn",
"topckgen-top-muxcamtm";
status = "okay";
};
cam2@1a050000 {
compatible = "mediatek,isp6s-cam";
reg = <0 0x1a050000 0 0x8000>,
<0 0x1a058000 0 0x8000>;
reg-names = "reg";
mediatek,cam-id = <1>;
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
#clock-cells = <1>;
/**
* Mapping to MTK's old style clk SCP_SYS_CAM_RAWB,
* connect to SCP_SYS_CAM, SCP_SYS_DIS
*/
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWB>;
mediatek,larb = <&larb17>;
/*
* Mapping to MTK's old style clk definition:
* CAMSYS_MAIN_CAM_CGPDN, CAMSYS_MAIN_CAMTG_CGPDN,
* CAMSYS_RAWB_LARBX_CGPDN, CAMSYS_RAWB_CAM_CGPDN,
* CAMSYS_RAWB_CAMTG_CGPDN, TOP_MUX_CAMTM
*/
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAMTG>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_rawb CLK_CAM_RAWB_CAM>,
<&camsys_rawb CLK_CAM_RAWB_CAMTG>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_cam_cgpdn",
"camsys_camtg_cgpdn",
"camsys-camb-larb-cgpdn",
"camsys-camb-cgpdn",
"camsys-cambtg-cgpdn",
"topckgen-top-muxcamtm";
status = "okay";
};
cam3@1a070000 {
compatible = "mediatek,isp6s-cam";
reg = <0 0x1a070000 0 0x8000>,
<0 0x1a078000 0 0x8000>;
reg-names = "reg";
mediatek,cam-id = <2>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
#clock-cells = <1>;
/**
* Mapping to MTK's old style clk SCP_SYS_CAM_RAWB,
* connect to SCP_SYS_CAM, SCP_SYS_DIS
*/
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM_RAWC>;
mediatek,larb = <&larb18>;
/**
* Mapping to MTK's old style clk definition:
* CAMSYS_MAIN_CAM_CGPDN, CAMSYS_MAIN_CAMTG_CGPDN,
* CAMSYS_RAWB_LARBX_CGPDN, CAMSYS_RAWB_CAM_CGPDN,
* CAMSYS_RAWB_CAMTG_CGPDN, TOP_MUX_CAMTM
*/
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_CAMTG>,
<&camsys_rawc CLK_CAM_RAWC_LARBX>,
<&camsys_rawc CLK_CAM_RAWC_CAM>,
<&camsys_rawc CLK_CAM_RAWC_CAMTG>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_cam_cgpdn",
"camsys_camtg_cgpdn",
"camsys-camc-larb-cgpdn",
"camsys-camc-cgpdn",
"camsys-camctg-cgpdn",
"topckgen-top-muxcamtm";
status = "okay";
};
ccu: ccu@1a101000 {
compatible = "mediatek,ccu";
power-domains = <&scpsys MT6873_POWER_DOMAIN_CAM>;
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L13_CAM_CCUI>,
<&iommu0 M4U_PORT_L13_CAM_CCUO>;
reg = <0 0x1a101000 0 0x1000>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&camsys CLK_CAM_CCU0>,
<&topckgen CLK_TOP_CCU_SEL>;
clock-names = "CCU_CLK_CAM_CCU",
"CCU_CLK_TOP_MUX";
};
ipesys: ipesys@1b000000 {
compatible = "mediatek,mt8192-ipesys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
aie@1b001000 {
compatible = "mediatek,mt6873-aie", "mediatek,aie-hw2.0";
reg = <0 0x1b001000 0 0x1000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_IPE>;
clocks = <&ipesys CLK_IPE_FD>;
clock-names = "aie";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L20_IPE_FDVT_RDA>,
<&iommu0 M4U_PORT_L20_IPE_FDVT_RDB>,
<&iommu0 M4U_PORT_L20_IPE_FDVT_WRA>,
<&iommu0 M4U_PORT_L20_IPE_FDVT_WRB>;
mediatek,larb = <&larb20>;
};
hcp: hcp@0 {
compatible = "mediatek,hcp";
};
rsc@1b003000 {
compatible = "mediatek,rsc";
mediatek,larb = <&larb20>;
mediatek,hcp = <&hcp>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_IPE>;
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L20_IPE_RSC_RDMA0>,
<&iommu0 M4U_PORT_L20_IPE_RSC_WDMA>;
reg = <0 0x1b003000 0 0x1000>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
mboxes = <&gce 13 0 CMDQ_THR_PRIO_1>;
gce-event-names = "rsc_eof";
gce-events = <&gce CMDQ_EVENT_RSC_DONE>;
clocks = <&ipesys CLK_IPE_RSC>,
<&ipesys CLK_IPE_LARB20>;
clock-names = "RSC_CLK_IPE_RSC",
"RSC_CLK_IPE_LARB20";
};
ipe_smi_subcom@1b00e000 {
compatible = "mediatek,ipe_smi_subcom",
"mediatek,mt6873-smi-common";
reg = <0 0x1b00e000 0 0x1000>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_IPE>;
clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_SMI_SUBCOM>;
clock-names = "apb", "smi", "gals0", "gals1";
};
larb20: larb@1b00f000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1b00f000 0 0x1000>;
mediatek,larb-id = <20>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_IPE>;
clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_LARB20>;
clock-names = "apb", "smi";
};
dvs: dvs@1b100000 {
compatible = "mediatek,dvs";
reg = <0 0x1b100000 0 0x1000>;
#clock-cells = <1>;
};
dvp: dvp@1b100800 {
compatible = "mediatek,dvp";
reg = <0 0x1b100000 0 0x1000>;
#clock-cells = <1>;
};
larb19: larb@1b10f000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1b10f000 0 0x1000>;
mediatek,larb-id = <19>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_IPE>;
clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_LARB19>;
clock-names = "apb", "smi";
};
mdpsys: mdpsys@1f000000 {
compatible = "mediatek,mt8192-mdpsys", "syscon";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
mdpsys_config: mdpsys_config@1f000000 {
compatible = "mediatek,mdpsys_config", "syscon";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
clocks = <&mdpsys CLK_MDP_IMG_DL_ASYNC0>,
<&mdpsys CLK_MDP_IMG_DL_ASYNC1>,
<&mdpsys CLK_MDP_IMG_DL_RELAY0_ASYNC0>,
<&mdpsys CLK_MDP_IMG_DL_RELAY1_ASYNC1>,
<&mdpsys CLK_MDP_APB_BUS>;
clock-names = "MDP_IMG_DL_ASYNC0",
"MDP_IMG_DL_ASYNC1",
"MDP_IMG0_IMG_DL_ASYNC0",
"MDP_IMG0_IMG_DL_ASYNC1",
"MDP_APB_BUS";
dma-ranges = <0x2 0x0 0x2 0x0 0x1 0x0>;
iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>,
<&iommu0 M4U_PORT_L2_MDP_RDMA1>,
<&iommu0 M4U_PORT_L2_MDP_WROT0>,
<&iommu0 M4U_PORT_L2_MDP_WROT1>;
dma_mask_bit = <35>;
};
mdp: mdp@1f000000 {
compatible = "mediatek,mdp";
reg = <0 0x1f000000 0 0x1000>;
thread_count = <24>;
mboxes = <&gce 19 0 CMDQ_THR_PRIO_1>,
<&gce 20 0 CMDQ_THR_PRIO_1>,
<&gce 21 0 CMDQ_THR_PRIO_1>,
<&gce 22 0 CMDQ_THR_PRIO_1>,
<&gce 10 0 CMDQ_THR_PRIO_1>;
mmsys_config = <&mdpsys_config>;
mm_mutex = <&mdp_mutex>;
mdp_rdma0 = <&mdp_rdma0>;
mdp_rdma1 = <&mdp_rdma1>;
mdp_rsz0 = <&mdp_rsz0>;
mdp_rsz1 = <&mdp_rsz1>;
mdp_wrot0 = <&mdp_wrot0>;
mdp_wrot1 = <&mdp_wrot1>;
mdp_tdshp0 = <&mdp_tdshp0>;
mdp_tdshp1 = <&mdp_tdshp1>;
mdp_aal0 = <&mdp_aal0>;
mdp_aal1 = <&mdp_aal1>;
mdp_color0 = <&mdp_color0>;
mdp_color1 = <&mdp_color1>;
mdp_hdr0 = <&mdp_hdr0>;
mdp_hdr1 = <&mdp_hdr1>;
mediatek,larb = <&larb2>;
g3d_config_base = <0x13000000 0 0xffff0000>;
mmsys_config_base = <0x14000000 1 0xffff0000>;
disp_dither_base = <0x14010000 2 0xffff0000>;
mm_na_base = <0x14020000 3 0xffff0000>;
imgsys_base = <0x15020000 4 0xffff0000>;
vdec_gcon_base = <0x18800000 5 0xffff0000>;
venc_gcon_base = <0x18810000 6 0xffff0000>;
conn_peri_base = <0x18820000 7 0xffff0000>;
topckgen_base = <0x18830000 8 0xffff0000>;
kp_base = <0x18840000 9 0xffff0000>;
scp_sram_base = <0x10000000 10 0xffff0000>;
infra_na3_base = <0x10010000 11 0xffff0000>;
infra_na4_base = <0x10020000 12 0xffff0000>;
scp_base = <0x10030000 13 0xffff0000>;
mcucfg_base = <0x10040000 14 0xffff0000>;
gcpu_base = <0x10050000 15 0xffff0000>;
usb0_base = <0x10200000 16 0xffff0000>;
usb_sif_base = <0x10280000 17 0xffff0000>;
audio_base = <0x17000000 18 0xffff0000>;
vdec_base = <0x17010000 19 0xffff0000>;
msdc2_base = <0x17020000 20 0xffff0000>;
vdec1_base = <0x17030000 21 0xffff0000>;
msdc3_base = <0x18000000 22 0xffff0000>;
ap_dma_base = <0x18010000 23 0xffff0000>;
gce_base = <0x18020000 24 0xffff0000>;
vdec2_base = <0x18040000 25 0xffff0000>;
vdec3_base = <0x18050000 26 0xffff0000>;
camsys_base = <0x18080000 27 0xffff0000>;
camsys1_base = <0x180a0000 28 0xffff0000>;
camsys2_base = <0x180b0000 29 0xffff0000>;
dip_cq_thread0_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0>;
dip_cq_thread1_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1>;
dip_cq_thread2_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2>;
dip_cq_thread3_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3>;
dip_cq_thread4_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4>;
dip_cq_thread5_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5>;
dip_cq_thread6_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6>;
dip_cq_thread7_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7>;
dip_cq_thread8_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8>;
dip_cq_thread9_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9>;
dip_cq_thread10_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10>;
dip_cq_thread11_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11>;
dip_cq_thread12_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12>;
dip_cq_thread13_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13>;
dip_cq_thread14_frame_done =
<CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14>;
dip_cq_thread21_frame_done =
<CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC>;
dip_cq_thread23_frame_done =
<CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC>;
wpe_a_frame_done =
<CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC>;
dip2_cq_thread0_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0>;
dip2_cq_thread1_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1>;
dip2_cq_thread2_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2>;
dip2_cq_thread3_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3>;
dip2_cq_thread4_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4>;
dip2_cq_thread5_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5>;
dip2_cq_thread6_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6>;
dip2_cq_thread7_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7>;
dip2_cq_thread8_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8>;
dip2_cq_thread9_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9>;
dip2_cq_thread10_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10>;
dip2_cq_thread11_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11>;
dip2_cq_thread12_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12>;
dip2_cq_thread13_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13>;
dip2_cq_thread14_frame_done =
<CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14>;
dip2_cq_thread21_frame_done =
<CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC>;
dip2_cq_thread23_frame_done =
<CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC>;
wpe_b_frame_done =
<CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC>;
mdp_rdma0_sof = <256>;
mdp_rdma1_sof = <257>;
mdp_aal_sof = <258>;
mdp_aal1_sof = <259>;
mdp_hdr0_sof = <260>;
mdp_hdr1_sof = <261>;
mdp_rsz0_sof = <262>;
mdp_rsz1_sof = <263>;
mdp_wrot0_sof = <264>;
mdp_wrot1_sof = <265>;
mdp_tdshp_sof = <266>;
mdp_tdshp1_sof = <267>;
img_dl_relay_sof = <268>;
img_dl_relay1_sof = <269>;
mdp_color_sof = <270>;
mdp_color1_sof = <271>;
mdp_wrot1_write_frame_done = <290>;
mdp_wrot0_write_frame_done = <291>;
mdp_tdshp1_frame_done = <294>;
mdp_tdshp_frame_done = <295>;
mdp_rsz1_frame_done = <302>;
mdp_rsz0_frame_done = <303>;
mdp_rdma1_frame_done = <306>;
mdp_rdma0_frame_done = <307>;
mdp_hdr1_frame_done = <308>;
mdp_hdr0_frame_done = <308>;
mdp_color1_frame_done = <312>;
mdp_color_frame_done = <313>;
mdp_aal1_frame_done = <316>;
mdp_aal_frame_done = <317>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0)
&mmqos SLAVE_LARB(2)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1)
&mmqos SLAVE_LARB(2)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0)
&mmqos SLAVE_LARB(2)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1)
&mmqos SLAVE_LARB(2)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGBI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_DMGI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_DEPI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_ICE_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_D2)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_CRZO_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMG3O_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_VIPI_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_D5)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TIMGO_D1)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_UFBC_W0)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_UFBC_R0)
&mmqos SLAVE_LARB(9)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMGI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMGBI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_DMGI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_DEPI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_ICE_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTO_D2)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTO_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_CRZO_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_IMG3O_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_VIPI_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_SMTI_D5)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_TIMGO_D1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_UFBC_W0)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_UFBC_R0)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_RDMA1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_RDMA0)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_WDMA)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA0)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA1)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA2)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA3)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA4)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_RDMA5)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_WDMA0)
&mmqos SLAVE_LARB(11)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_MFB_WDMA1)
&mmqos SLAVE_LARB(11)>;
interconnect-names =
"mdp_rdma0",
"mdp_rdma1",
"mdp_wrot0",
"mdp_wrot1",
"l9_img_imgi_d1",
"l9_img_imgbi_d1",
"l9_img_dmgi_d1",
"l9_img_depi_d1",
"l9_img_ice_d1",
"l9_img_smti_d1",
"l9_img_smto_d2",
"l9_img_smto_d1",
"l9_img_crzo_d1",
"l9_img_img3o_d1",
"l9_img_vipi_d1",
"l9_img_smti_d5",
"l9_img_timgo_d1",
"l9_img_ufbc_w0",
"l9_img_ufbc_r0",
"l11_img_imgi_d1",
"l11_img_imgbi_d1",
"l11_img_dmgi_d1",
"l11_img_depi_d1",
"l11_img_ice_d1",
"l11_img_smti_d1",
"l11_img_smto_d2",
"l11_img_smto_d1",
"l11_img_crzo_d1",
"l11_img_img3o_d1",
"l11_img_vipi_d1",
"l11_img_smti_d5",
"l11_img_timgo_d1",
"l11_img_ufbc_w0",
"l11_img_ufbc_r0",
"l11_img_wpe_rdma1",
"l11_img_wpe_rdma0",
"l11_img_wpe_wdma",
"l11_img_mfb_rdma0",
"l11_img_mfb_rdma1",
"l11_img_mfb_rdma2",
"l11_img_mfb_rdma3",
"l11_img_mfb_rdma4",
"l11_img_mfb_rdma5",
"l11_img_mfb_wdma0",
"l11_img_mfb_wdma1";
mdp-opp = <&opp_table_mdp>;
isp-opp = <&opp_table_img>;
mdp-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
isp-dvfsrc-vcore-supply = <&dvfsrc_vcore>;
dre30_hist_sram_start = /bits/ 16 <1536>;
};
mdp_mutex: mdp_mutex@1f001000 {
compatible = "mediatek,mdp_mutex";
reg = <0 0x1f001000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_MUTEX0>;
clock-names = "MDP_MUTEX0";
};
mdp_rdma0: mdp_rdma0@1f003000 {
compatible = "mediatek,mdp_rdma0";
reg = <0 0x1f003000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_RDMA0>;
clock-names = "MDP_RDMA0";
};
mdp_rdma1: mdp_rdma1@1f004000 {
compatible = "mediatek,mdp_rdma1";
reg = <0 0x1f004000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_RDMA1>;
clock-names = "MDP_RDMA1";
};
mdp_aal0: mdp_aal0@1f005000 {
compatible = "mediatek,mdp_aal0";
reg = <0 0x1f005000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_AAL0>;
clock-names = "MDP_AAL0";
};
mdp_aal1: mdp_aal1@1f006000 {
compatible = "mediatek,mdp_aal1";
reg = <0 0x1f006000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_AAL1>;
clock-names = "MDP_AAL1";
};
mdp_hdr0: mdp_hdr0@1f007000 {
compatible = "mediatek,mdp_hdr0";
reg = <0 0x1f007000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_HDR0>;
clock-names = "MDP_HDR0";
};
mdp_hdr1: mdp_hdr1@1f008000 {
compatible = "mediatek,mdp_hdr1";
reg = <0 0x1f008000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_HDR1>;
clock-names = "MDP_HDR1";
};
mdp_rsz0: mdp_rsz0@1f009000 {
compatible = "mediatek,mdp_rsz0";
reg = <0 0x1f009000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_RSZ0>;
clock-names = "MDP_RSZ0";
};
mdp_rsz1: mdp_rsz1@1f00a000 {
compatible = "mediatek,mdp_rsz1";
reg = <0 0x1f00a000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_RSZ1>;
clock-names = "MDP_RSZ1";
};
mdp_wrot0: mdp_wrot0@1f00b000 {
compatible = "mediatek,mdp_wrot0";
reg = <0 0x1f00b000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_WROT0>;
clock-names = "MDP_WROT0";
};
mdp_wrot1: mdp_wrot1@1f00c000 {
compatible = "mediatek,mdp_wrot1";
reg = <0 0x1f00c000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_WROT1>;
clock-names = "MDP_WROT1";
};
mdp_tdshp0: mdp_tdshp0@1f00d000 {
compatible = "mediatek,mdp_tdshp0";
reg = <0 0x1f00d000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_TDSHP0>;
clock-names = "MDP_TDSHP0";
};
mdp_tdshp1: mdp_tdshp1@1f00e000 {
compatible = "mediatek,mdp_tdshp1";
reg = <0 0x1f00e000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_TDSHP1>;
clock-names = "MDP_TDSHP1";
};
mdp_color0: mdp_color0@1f00f000 {
compatible = "mediatek,mdp_color0";
reg = <0 0x1f00f000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_COLOR0>;
clock-names = "MDP_COLOR0";
};
mdp_color1: mdp_color1@1f010000 {
compatible = "mediatek,mdp_color1";
reg = <0 0x1f010000 0 0x1000>;
clocks = <&mdpsys CLK_MDP_COLOR1>;
clock-names = "MDP_COLOR1";
};
larb2: larb@1f002000 {
compatible = "mediatek,mt6873-smi-larb";
mediatek,smi = <&smi_common>;
reg = <0 0x1f002000 0 0x1000>;
mediatek,larb-id = <2>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_MDP>;
clocks = <&mdpsys CLK_MDP_SMI0>,
<&mdpsys CLK_MDP_SMI0>;
clock-names = "apb", "smi";
};
dispsys_config: dispsys_config@14000000 {
compatible = "mediatek,mt6873-mmsys";
power-domains = <&scpsys MT6873_POWER_DOMAIN_DISP>;
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
mediatek,larb = <&larb1>;
fake-engine = <&larb0 M4U_PORT_L0_DISP_FAKE0>,
<&larb1 M4U_PORT_L1_DISP_FAKE1>;
clocks = <&mmsys CLK_MM_26MHZ>,
<&mmsys CLK_MM_DISP_CONFIG>,
<&mmsys CLK_MM_DISP_MUTEX0>;
clock-num = <3>;
operating-points-v2 = <&opp_table_disp>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects = <&mmqos SLAVE_LARB(23) &mmqos SLAVE_COMMON(0)>;
interconnect-names = "disp_hrt_qos";
/* define threads, see mt6873-gce.h */
mediatek,mailbox-gce = <&gce>;
mboxes = <&gce 0 0 CMDQ_THR_PRIO_4>,
<&gce 5 0 CMDQ_THR_PRIO_4>,
<&gce 2 0 CMDQ_THR_PRIO_4>,
<&gce 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
<&gce 1 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_6>,
<&gce 4 0 CMDQ_THR_PRIO_4>,
<&gce 6 0 CMDQ_THR_PRIO_3>;
gce-client-names = "CLIENT_CFG0",
"CLIENT_CFG1",
"CLIENT_CFG2",
"CLIENT_TRIG_LOOP0",
"CLIENT_SODI_LOOP0",
"CLIENT_SUB_CFG0",
"CLIENT_DSI_CFG0";
/* define subsys, see mt6873-gce.h */
gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
<&gce 0x14010000 SUBSYS_1401XXXX>,
<&gce 0x14020000 SUBSYS_1402XXXX>;
/* define subsys, see mt6873-gce.h */
gce-event-names = "disp_mutex0_eof",
"disp_mutex1_eof",
"disp_token_stream_dirty0",
"disp_token_sodi0",
"disp_wait_dsi0_te",
"disp_token_stream_eof0",
"disp_dsi0_eof",
"disp_token_esd_eof0",
"disp_rdma0_eof0",
"disp_wdma0_eof0",
"disp_token_stream_block0",
"disp_token_cabc_eof0",
"disp_wdma0_eof2",
"disp_dsi0_sof0";
gce-events =
<&gce CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<&gce CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>,
<&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY>,
<&gce CMDQ_SYNC_TOKEN_SODI>,
<&gce CMDQ_EVENT_DSI0_TE_ENG_EVENT>,
<&gce CMDQ_SYNC_TOKEN_STREAM_EOF>,
<&gce CMDQ_EVENT_DSI0_FRAME_DONE>,
<&gce CMDQ_SYNC_TOKEN_ESD_EOF>,
<&gce CMDQ_EVENT_DISP_RDMA0_FRAME_DONE>,
<&gce CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
<&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK>,
<&gce CMDQ_SYNC_TOKEN_CABC_EOF>,
<&gce CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
<&gce CMDQ_EVENT_DSI0_SOF>;
helper-name = "MTK_DRM_OPT_STAGE",
"MTK_DRM_OPT_USE_CMDQ",
"MTK_DRM_OPT_USE_M4U",
"MTK_DRM_OPT_SODI_SUPPORT",
"MTK_DRM_OPT_IDLE_MGR",
"MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE",
"MTK_DRM_OPT_IDLEMGR_BY_REPAINT",
"MTK_DRM_OPT_IDLEMGR_ENTER_ULPS",
"MTK_DRM_OPT_IDLEMGR_KEEP_LP11",
"MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING",
"MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ",
"MTK_DRM_OPT_MET_LOG",
"MTK_DRM_OPT_USE_PQ",
"MTK_DRM_OPT_ESD_CHECK_RECOVERY",
"MTK_DRM_OPT_ESD_CHECK_SWITCH",
"MTK_DRM_OPT_PRESENT_FENCE",
"MTK_DRM_OPT_RDMA_UNDERFLOW_AEE",
"MTK_DRM_OPT_DSI_UNDERRUN_AEE",
"MTK_DRM_OPT_HRT",
"MTK_DRM_OPT_HRT_MODE",
"MTK_DRM_OPT_DELAYED_TRIGGER",
"MTK_DRM_OPT_OVL_EXT_LAYER",
"MTK_DRM_OPT_AOD",
"MTK_DRM_OPT_RPO",
"MTK_DRM_OPT_DUAL_PIPE",
"MTK_DRM_OPT_DC_BY_HRT",
"MTK_DRM_OPT_OVL_WCG",
"MTK_DRM_OPT_OVL_SBCH",
"MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK",
"MTK_DRM_OPT_MET",
"MTK_DRM_OPT_REG_PARSER_RAW_DUMP",
"MTK_DRM_OPT_VP_PQ",
"MTK_DRM_OPT_GAME_PQ",
"MTK_DRM_OPT_MMPATH",
"MTK_DRM_OPT_HBM",
"MTK_DRM_OPT_LAYER_REC",
"MTK_DRM_OPT_CLEAR_LAYER";
helper-value = <0>, /*MTK_DRM_OPT_STAGE*/
<1>, /*MTK_DRM_OPT_USE_CMDQ*/
<1>, /*MTK_DRM_OPT_USE_M4U*/
<0>, /*MTK_DRM_OPT_SODI_SUPPORT*/
<1>, /*MTK_DRM_OPT_IDLE_MGR*/
<0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/
<1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/
<0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/
<0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/
<0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/
<1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/
<0>, /*MTK_DRM_OPT_MET_LOG*/
<1>, /*MTK_DRM_OPT_USE_PQ*/
<1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/
<1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/
<1>, /*MTK_DRM_OPT_PRESENT_FENCE*/
<0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/
<1>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/
<1>, /*MTK_DRM_OPT_HRT*/
<1>, /*MTK_DRM_OPT_HRT_MODE*/
<0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/
<1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/
<0>, /*MTK_DRM_OPT_AOD*/
<1>, /*MTK_DRM_OPT_RPO*/
<0>, /*MTK_DRM_OPT_DUAL_PIPE*/
<0>, /*MTK_DRM_OPT_DC_BY_HRT*/
<1>, /*MTK_DRM_OPT_OVL_WCG*/
<0>, /*MTK_DRM_OPT_OVL_SBCH*/
<1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/
<0>, /*MTK_DRM_OPT_MET*/
<0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/
<0>, /*MTK_DRM_OPT_VP_PQ*/
<0>, /*MTK_DRM_OPT_GAME_PQ*/
<0>, /*MTK_DRM_OPT_MMPATH*/
<0>, /*MTK_DRM_OPT_HBM*/
<0>, /*MTK_DRM_OPT_LAYER_REC*/
<1>; /*MTK_DRM_OPT_CLEAR_LAYER*/
};
disp_mutex0: disp_mutex@14001000 {
compatible = "mediatek,disp_mutex0",
"mediatek,mt6873-disp-mutex";
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
};
disp_ovl0: disp_ovl0@14005000 {
compatible = "mediatek,disp_ovl0",
"mediatek,mt6873-disp-ovl";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0)
&mmqos SLAVE_LARB(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0)
&mmqos SLAVE_LARB(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0)
&mmqos SLAVE_LARB(0)>;
interconnect-names = "DDP_COMPONENT_OVL0_qos",
"DDP_COMPONENT_OVL0_fbdc_qos",
"DDP_COMPONENT_OVL0_hrt_qos";
};
disp_ovl0_2l: disp_ovl0_2l@14006000 {
compatible = "mediatek,disp_ovl0_2l",
"mediatek,mt6873-disp-ovl";
reg = <0 0x14006000 0 0x1000>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0)
&mmqos SLAVE_LARB(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0)
&mmqos SLAVE_LARB(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0)
&mmqos SLAVE_LARB(1)>;
interconnect-names = "DDP_COMPONENT_OVL0_2L_qos",
"DDP_COMPONENT_OVL0_2L_fbdc_qos",
"DDP_COMPONENT_OVL0_2L_hrt_qos";
};
disp_rdma0: disp_rdma0@14007000 {
compatible = "mediatek,disp_rdma0",
"mediatek,mt6873-disp-rdma";
reg = <0 0x14007000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
&mmqos SLAVE_LARB(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
&mmqos SLAVE_LARB(0)>;
interconnect-names = "DDP_COMPONENT_RDMA0_qos",
"DDP_COMPONENT_RDMA0_hrt_qos";
};
disp_rsz0: disp_rsz0@14008000 {
compatible = "mediatek,disp_rsz0",
"mediatek,mt6873-disp-rsz";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_RSZ0>;
};
disp_color0: disp_color0@14009000 {
compatible = "mediatek,disp_color0",
"mediatek,mt6873-disp-color";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
};
disp_ccorr0: disp_ccorr0@1400a000 {
compatible = "mediatek,disp_ccorr0",
"mediatek,mt6873-disp-ccorr";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
};
disp_aal0: disp_aal0@1400b000 {
compatible = "mediatek,disp_aal0",
"mediatek,mt6873-disp-aal";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
aal_dre3 = <&mdp_aal4>;
mtk_aal_support = <1>;
mtk_dre30_support = <0>;
};
disp_gamma0: disp_gamma0@1400c000 {
compatible = "mediatek,disp_gamma0",
"mediatek,mt6873-disp-gamma";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
};
disp_postmask0: disp_postmask0@1400d000 {
compatible = "mediatek,disp_postmask0",
"mediatek,mt6873-disp-postmask";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
};
disp_dither0: disp_dither0@1400e000 {
compatible = "mediatek,disp_dither0",
"mediatek,mt6873-disp-dither";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
disp_dsc_wrap: disp_dsc_wrap@1400f000 {
compatible = "mediatek,disp_dsc_wrap",
"mediatek,mt6873-disp-dsc";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_DSC_WRAP0>;
};
mipi_tx_config0: mipi_tx_config@11e50000 {
compatible = "mediatek,mipi_tx_config0",
"mediatek,mt6873-mipi-tx";
reg = <0 0x11e50000 0 0x1000>;
clocks = <&clk26m>;
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx0_pll";
};
dsi0: dsi@14010000 {
compatible = "mediatek,dsi0",
"mediatek,mt6873-dsi";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DSI0>,
<&mmsys CLK_MM_DSI_DSI0>,
<&mipi_tx_config0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx_config0>;
phy-names = "dphy";
};
disp_wdma0: disp_wdma0@14011000 {
compatible = "mediatek,disp_wdma0",
"mediatek,mt6873-disp-wdma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_WDMA0>;
};
disp_ufbc_wdma0@14012000 {
compatible = "mediatek,disp_ufbc_wdma0";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,larb = <&larb1>;
};
disp_ovl2_2l: disp_ovl2_2l@14014000 {
compatible = "mediatek,disp_ovl2_2l",
"mediatek,mt6873-disp-ovl";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA2)
&mmqos SLAVE_LARB(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA2)
&mmqos SLAVE_LARB(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA2)
&mmqos SLAVE_LARB(1)>;
interconnect-names = "DDP_COMPONENT_OVL2_2L_qos",
"DDP_COMPONENT_OVL2_2L_fbdc_qos",
"DDP_COMPONENT_OVL2_2L_hrt_qos";
};
disp_rdma4: disp_rdma4@14015000 {
compatible = "mediatek,disp_rdma4",
"mediatek,mt6873-disp-rdma";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA4)
&mmqos SLAVE_LARB(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA4)
&mmqos SLAVE_LARB(1)>;
interconnect-names = "DDP_COMPONENT_RDMA4_qos",
"DDP_COMPONENT_RDMA4_hrt_qos";
};
dpi0@14016000 {
compatible = "mediatek,dpi0";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
};
mdp_aal4: mdp_aal4@1401a000 {
compatible = "mediatek,mdp_aal4",
"mediatek,mt6873-dmdp-aal";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_MDP_AAL4>;
clock-names = "DRE3_AAL0";
};
wifi: wifi@18000000 {
compatible = "mediatek,wifi";
reg = <0 0x18000000 0 0x100000>;
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH 0>;
memory-region = <&wifi_mem>;
};
consys: consys@18002000 {
compatible = "mediatek,mt6873-consys";
#thermal-sensor-cells = <0>;
#address-cells = <2>;
#size-cells = <2>;
/*CONN_MCU_CONFIG_BASE */
reg = <0 0x18002000 0 0x1000>,
/*TOP_RGU_BASE */
<0 0x10007000 0 0x0100>,
/*INFRACFG_AO_BASE */
<0 0x10001000 0 0x1000>,
/*SPM_BASE */
<0 0x10006000 0 0x1000>,
/*CONN_HIF_ON_BASE */
<0 0x18007000 0 0x1000>,
/*CONN_TOP_MISC_OFF_BASE */
<0 0x180b1000 0 0x1000>,
/*CONN_MCU_CFG_ON_BASE */
<0 0x180a3000 0 0x1000>,
/*CONN_MCU_CIRQ_BASE */
<0 0x180a5000 0 0x800>,
/*CONN_TOP_MISC_ON_BASE */
<0 0x180c1000 0 0x1000>,
/*CONN_HIF_PDMA_BASE */
<0 0x18004000 0 0x1000>,
/* INFRASYS_COMMON AP2MD_PCCIF4_BASE */
<0 0x1024C000 0 0x40>,
/*INFRA_AO_PERICFG_BASE */
<0 0x10003000 0 0x1000>;
/*BGF_EINT */
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH 0>,
/*WDT_EINT */
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0>,
/*conn2ap_sw_irq*/
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT6873_POWER_DOMAIN_CONN>;
clocks = <&infracfg CLK_INFRA_CCIF4_AP>;
clock-names = "ccif";
pmic = <&pmic>;
memory-region = <&consys_mem>;
};
clock_buffer_ctrl: clock_buffer_ctrl {
compatible = "mediatek,clock_buffer";
mediatek,clkbuf-quantity = <7>;
mediatek,clkbuf-config = <2 1 1 2 0 0 1>;
mediatek,clkbuf-output-impedance = <6 6 4 6 0 0 4>;
mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>;
mediatek,bring-up = "disable";
mediatek,bblpm-support = "enable";
pwrap-dcxo-en = <0x188 0 0x188 1 0x188 0>;
pwrap-dcxo-cfg = <0x18c 0x19c>;
spm-pwr-status = <0x180 0 0x180 1>;
pwrap = <&pwrap>;
sleep = <&sleep>;
};
};
dsi_te: dsi_te {
compatible = "mediatek, dsi_te-eint";
status = "disabled";
};
mtkfb: mtkfb@0 {
compatible = "mediatek,mtkfb";
};
slbc: slbc {
compatible = "mediatek,mtk-slbc";
status = "enable";
};
sound: sound {
compatible = "mediatek,mt6873-mt6359p-sound";
mediatek,snd_audio_dsp = <&snd_audio_dsp>;
mediatek,headset-codec = <&accdet>;
mediatek,platform = <&afe>;
};
/* feature : $enable $dl_mem $ul_mem $ref_mem $size */
snd_audio_dsp: snd_audio_dsp {
compatible = "mediatek,snd_audio_dsp";
mtk_dsp_voip = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x30000>;
mtk_dsp_primary = <0x5 0xffffffff 0xffffffff \
0xffffffff 0x30000>;
mtk_dsp_offload = <0x1d 0xffffffff 0xffffffff \
0xffffffff 0x400000>;
mtk_dsp_deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
mtk_dsp_playback = <0x1 0x4 0xffffffff 0x14 0x30000>;
mtk_dsp_music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>;
mtk_dsp_capture1 = <0x0 0xffffffff 0xd 0x13 0x20000>;
mtk_dsp_a2dp = <0x0 0xffffffff 0xffffffff 0xffffffff 0x40000>;
mtk_dsp_dataprovider = <0x0 0xffffffff 0xf 0xffffffff 0x30000>;
mtk_dsp_call_final = <0x5 0x4 0x10 0x14 0x18000>;
mtk_dsp_fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>;
mtk_dsp_ktv = <0x1 0x8 0x12 0xffffffff 0x10000>;
mtk_dsp_capture_raw = <0x0 0xffffffff 0xffffffff 0xffffffff 0x20000>;
mtk_dsp_ver = <0x1>;
swdsp_smartpa_process_enable = <0x5>;
mtk_dsp_mem_afe = <0x1 0x40000>;
is_shared_dram_mpu = <0x1>;
};
mtk_lpm: mtk_lpm {
compatible = "mediatek,mtk-lpm";
#address-cells = <2>;
#size-cells = <2>;
ranges;
suspend-method = "enable";
logger-enable-states = "mcusysoff", "system_mem",
"system_pll", "system_bus";
mcusys-cnt-chk = <1>;
irq-remain = <&edge_keypad &edge_mdwdt>,
<&level_mali0 &level_mali1>,
<&level_mali2 &level_mali3 &level_mali4>,
<&level_mtk_mdla>,
<&level_usb_host &level_ufshci>;
resource-ctrl = <&bus26m &infra &syspll>,
<&dram_s0 &dram_s1>;
constraints = <&rc_bus26m &rc_syspll &rc_dram>,
<&rc_cpu_buck_ldo>;
spm-cond = <&spm_cond_cg &spm_cond_pll>;
cg-shift = <0>; /* cg blocking index */
pll-shift = <16>; /* pll blocking index */
power-gs = <&gs_6359p &gs_6315_1 &gs_6315_2 &gs_6315_3>;
cpupm_sysram: cpupm-sysram@0011b000 {
compatible = "mediatek,cpupm-sysram";
reg = <0 0x0011b000 0 0x500>;
};
mcusys_ctrl: mcusys-ctrl@0c53a000 {
compatible = "mediatek,mcusys-ctrl";
reg = <0 0x0c53a000 0 0x1000>;
};
lpm_sysram: lpm_sysram@0011b500 {
compatible = "mediatek,lpm-sysram";
reg = <0 0x0011b500 0 0x300>;
};
irq-remain-list {
level_ufshci: level_ufshci {
target = <&ufshci>;
value = <0 0 0 0>;
};
edge_keypad: edge_keypad {
target = <&keypad>;
value = <1 0 0 0x04>;
};
edge_mdwdt: edge_mdwdt {
target = <&mddriver>;
value = <1 0 0 0x02000000>;
};
level_mali0: level_mali0 {
target = <&mali>;
value = <0 0 0 0>;
};
level_mali1: level_mali1 {
target = <&mali>;
value = <0 1 0 0>;
};
level_mali2: level_mali2 {
target = <&mali>;
value = <0 2 0 0>;
};
level_mali3: level_mali3 {
target = <&mali>;
value = <0 3 0 0>;
};
level_mali4: level_mali4 {
target = <&mali>;
value = <0 4 0 0>;
};
level_mtk_mdla: level_mtk_mdla {
target = <&mtk_mdla>;
value = <0 0 0 0>;
};
level_usb_host: level_usb_host {
target = <&usb_host>;
value = <0 0 0 0>;
};
};
resource-ctrl-list {
bus26m: bus26m {
id = <0x00000000>;
value = <0>;
};
infra: infra {
id = <0x00000001>;
value = <0>;
};
syspll: syspll {
id = <0x00000002>;
value = <0>;
};
dram_s0: dram_s0 {
id = <0x00000003>;
value = <0>;
};
dram_s1: dram_s1 {
id = <0x00000004>;
value = <0>;
};
};
constraint-list {
rc_bus26m: rc_bus26m {
rc-name = "bus26m";
id = <0x00000000>;
value = <1>;
cond-info = <1>;
};
rc_syspll: rc_syspll {
rc-name = "syspll";
id = <0x00000001>;
value = <1>;
cond-info = <1>;
};
rc_dram: rc_dram {
rc-name = "dram";
id = <0x00000002>;
value = <1>;
cond-info = <1>;
};
rc_cpu_buck_ldo: rc_cpu_buck_ldo{
rc-name = "cpu-buck-ldo";
id = <0x00000003>;
value = <1>;
cond-info = <0>;
};
};
spm-cond-list {
spm_cond_cg: spm_cond_cg {
cg-name = "MTCMOS_0",
"INFRA_0",
"INFRA_1",
"INFRA_2",
"INFRA_3",
"INFRA_4",
"INFRA_5",
"MMSYS_0",
"MMSYS_1",
"MMSYS_2";
};
spm_cond_pll: spm_cond_pll {
pll-name = "UNIVPLL",
"MFGPLL",
"MSDCPLL",
"TVPLL",
"MMPLL",
"USBPLL",
"ADSPPLL",
"APLL1",
"APLL2",
"APUPLL",
"NPUPLL";
};
};
power-gs-list {
gs_6359p: gs_6359p {
target = <&pmic>;
value = "mediatek,mt6359p-regulator";
};
gs_6315_1: gs_6315_1 {
target = <&spmi>;
value = "mediatek,mt6315_6-regulator";
};
gs_6315_2: gs_6315_2 {
target = <&spmi>;
value = "mediatek,mt6315_7-regulator";
};
gs_6315_3: gs_6315_3 {
target = <&spmi>;
value = "mediatek,mt6315_3-regulator";
};
};
};
};
&pio {
aud_clk_mosi_off: aud_clk_mosi_off {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO214__FUNC_GPIO214>;
input-enable;
bias-pull-down;
};
pins_cmd1_dat {
pinmux = <PINMUX_GPIO215__FUNC_GPIO215>;
input-enable;
bias-pull-down;
};
};
aud_clk_mosi_on: aud_clk_mosi_on {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>;
input-schmitt-enable;
bias-disable;
};
pins_cmd1_dat {
pinmux = <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_mosi_off: aud_dat_mosi_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO216__FUNC_GPIO216>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO217__FUNC_GPIO217>;
input-enable;
bias-pull-down;
};
};
aud_dat_mosi_on: aud_dat_mosi_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_mosi_ch34_off: aud_dat_mosi_ch34_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO196__FUNC_GPIO196>;
input-enable;
bias-pull-down;
};
};
aud_dat_mosi_ch34_on: aud_dat_mosi_ch34_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso0_off: aud_dat_miso0_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO218__FUNC_GPIO218>;
input-enable;
bias-pull-down;
};
};
aud_dat_miso0_on: aud_dat_miso0_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso1_off: aud_dat_miso_off {
pins_cmd2_dat {
pinmux = <PINMUX_GPIO219__FUNC_GPIO219>;
input-enable;
bias-disable;
};
};
aud_dat_miso1_on: aud_dat_miso_on {
pins_cmd2_dat {
pinmux = <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso2_off: aud_dat_miso2_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO199__FUNC_GPIO199>;
input-enable;
bias-pull-down;
};
};
aud_dat_miso2_on: aud_dat_miso2_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>;
input-schmitt-enable;
bias-disable;
};
};
vow_dat_miso_off: vow_dat_miso_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO218__FUNC_GPIO218>;
input-enable;
bias-pull-down;
};
};
vow_dat_miso_on: vow_dat_miso_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>;
input-schmitt-enable;
bias-disable;
};
};
vow_clk_miso_off: vow_clk_miso_off {
pins_cmd3_dat {
pinmux = <PINMUX_GPIO219__FUNC_GPIO219>;
input-enable;
bias-pull-down;
};
};
vow_clk_miso_on: vow_clk_miso_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>;
input-schmitt-enable;
bias-disable;
};
};
aud_nle_mosi_off: aud_nle_mosi_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO197__FUNC_GPIO197>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO198__FUNC_GPIO198>;
input-enable;
bias-pull-down;
};
};
aud_nle_mosi_on: aud_nle_mosi_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>;
input-schmitt-enable;
bias-disable;
};
};
aud_gpio_i2s0_off: aud_gpio_i2s0_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO34__FUNC_GPIO34>;
input-enable;
bias-pull-down;
};
};
aud_gpio_i2s0_on: aud_gpio_i2s0_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO34__FUNC_I2S0_DI>;
input-schmitt-enable;
bias-disable;
};
};
aud_gpio_i2s1_off: aud_gpio_i2s1_off {
};
aud_gpio_i2s1_on: aud_gpio_i2s1_on {
};
aud_gpio_i2s2_off: aud_gpio_i2s2_off {
};
aud_gpio_i2s2_on: aud_gpio_i2s2_on {
};
aud_gpio_i2s3_off: aud_gpio_i2s3_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO32__FUNC_GPIO32>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO33__FUNC_GPIO33>;
input-enable;
bias-pull-down;
};
pins_cmd3_dat {
pinmux = <PINMUX_GPIO35__FUNC_GPIO35>;
input-enable;
bias-pull-down;
};
};
aud_gpio_i2s3_on: aud_gpio_i2s3_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO33__FUNC_I2S3_LRCK>;
input-schmitt-enable;
bias-disable;
};
pins_cmd3_dat {
pinmux = <PINMUX_GPIO35__FUNC_I2S3_DO>;
input-schmitt-enable;
bias-disable;
};
};
aud_gpio_i2s5_off: aud_gpio_i2s5_off {
};
aud_gpio_i2s5_on: aud_gpio_i2s5_on {
};
aud_gpio_i2s6_off: aud_gpio_i2s6_off {
};
aud_gpio_i2s6_on: aud_gpio_i2s6_on {
};
aud_gpio_i2s7_off: aud_gpio_i2s7_off {
};
aud_gpio_i2s7_on: aud_gpio_i2s7_on {
};
aud_gpio_i2s8_off: aud_gpio_i2s8_off {
};
aud_gpio_i2s8_on: aud_gpio_i2s8_on {
};
aud_gpio_i2s9_off: aud_gpio_i2s9_off {
};
aud_gpio_i2s9_on: aud_gpio_i2s9_on {
};
/* ATF logger */
atf_logger {
compatible = "mediatek,atf_logger";
};
};
#include "trusty.dtsi"
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